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An et al., 2014 - Google Patents

Speeding up FPGA placement: Parallel algorithms and methods

An et al., 2014

View PDF
Document ID
18347224353684293949
Author
An M
Steffan J
Betz V
Publication year
Publication venue
2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

External Links

Snippet

Placement of a large FPGA design now commonly requires several hours, significantly hindering designer productivity. Furthermore, FPGA capacity is growing faster than CPU speed, which will further increase placement time unless new approaches are found. Multi …
Continue reading at www.eecg.utoronto.ca (PDF) (other versions)

Classifications

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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
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