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Vandooren et al., 2019 - Google Patents

Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V th tuning and RF shielding applications

Vandooren et al., 2019

Document ID
1904160100709032611
Author
Vandooren A
Wu Z
Khaled A
Franco J
Parvais B
Li W
Witters L
Walke A
Peng L
Rassoul N
Matagne P
Debruyn H
Jamieson G
Inoue F
Devriendt K
Teugels L
Heylen N
Vecchio E
Zheng T
Radisic D
Rosseel E
Vanherle W
Hikavyy A
Chan B
Besnard G
Schwarzenbach W
Gaudin G
Radu I
Nguyen B
Waldron N
De Heyn V
Demuynck S
Boemmels J
Ryckaert J
Collaert N
Mocuta D
Publication year
Publication venue
2019 Symposium on VLSI Technology

External Links

Snippet

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a …
Continue reading at ieeexplore.ieee.org (other versions)

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