Packirisamy et al., 2009 - Google Patents
Exploring speculative parallelism in SPEC2006Packirisamy et al., 2009
View PDF- Document ID
- 1906779162408940112
- Author
- Packirisamy V
- Zhai A
- Hsu W
- Yew P
- Ngai T
- Publication year
- Publication venue
- 2009 IEEE International Symposium on Performance Analysis of Systems and Software
External Links
Snippet
The computer industry has adopted multi-threaded and multi-core architectures as the clock rate increase stalled in early 2000's. It was hoped that the continuous improvement of single- program performance could be achieved through these architectures. However, traditional …
- 238000000034 method 0 abstract description 10
Classifications
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- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution from multiple instruction streams, e.g. multistreaming
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- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G06F11/3466—Performance evaluation by tracing or monitoring
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