Pacholik et al., 2005 - Google Patents
Real Time Constraints in System Level Specifications Improving the Verification Flow of Complex SystemsPacholik et al., 2005
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- 1971973711231423636
- Author
- Pacholik A
- Fengler W
- Salzwedel H
- Vinogradov O
- Publication year
- Publication venue
- Net. ObjectDays
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Complex real time systems like large system on chips need to be verified to assure quality and save time. Today verification activities are restricted to the register transfer level or one design step above. A complete flow from early specifications down to physical …
- 230000002123 temporal effect 0 abstract description 28
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- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
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