Sima et al., 2004 - Google Patents
Pel reconstruction on FPGA-augmented TriMediaSima et al., 2004
View PDF- Document ID
- 2363708395153636860
- Author
- Sima M
- Cotofana S
- Vassiliadis S
- van Eijndhoven J
- Vissers K
- Publication year
- Publication venue
- IEEE transactions on very large scale integration (VLSI) systems
External Links
Snippet
This paper presents a TriMedia processor extended with three reconfigurable designs for entropy decoding (ED), inverse quantization (IQ), and two-dimensional (2-D) inverse discrete cosine transform (IDCT), and assesses the performance gain that is provided by …
- 230000003213 activating 0 abstract description 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Lee | Accelerating multimedia with enhanced microprocessors | |
| Masera et al. | Adaptive approximated DCT architectures for HEVC | |
| US9665540B2 (en) | Video decoder with a programmable inverse transform unit | |
| US6963341B1 (en) | Fast and flexible scan conversion and matrix transpose in a SIMD processor | |
| Kammoun et al. | Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application | |
| Shahbahrami | Algorithms and architectures for 2D discrete wavelet transform | |
| Hartenstein et al. | Reconfigurable machine for applications in image and video compression | |
| Shahbahrami et al. | Matrix register file and extended subwords: two techniques for embedded media processors | |
| Tung et al. | MMX-based DCT and MC algorithms for real-time pure software MPEG decoding | |
| Sima et al. | Pel reconstruction on FPGA-augmented TriMedia | |
| US6292814B1 (en) | Methods and apparatus for implementing a sign function | |
| Simat et al. | MPEG-compliant Entropy Decoding on FPGA-augmented TriMedia/CPU64 | |
| Sima et al. | MPEG macroblock parsing and pel reconstruction on an FPGA-augmented TriMedia processor | |
| Verderber et al. | HW/SW codesign of the MPEG-2 video decoder | |
| Wong et al. | Coarse reconfigurable multimedia unit extension | |
| Davare et al. | Jpeg encoding on the intel mxp5800: A platform-based design case study | |
| Verderber et al. | HW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder | |
| Sima et al. | Inverse Quantization on FPGA-augmented TriMedia | |
| Molloy et al. | A 110-K transistor 25-Mpixels/s configurable image transform processor unit | |
| Bagni et al. | Efficient IDCT implementations on VLIW processors | |
| Sekhar | Precision-Aware and Quantization of Lifting Based DWT Hardware Architecture | |
| Hunter et al. | Rapid design of discrete cosine transform cores | |
| Chen et al. | Application-specific data path for highly efficient computation of multistandard video codecs | |
| Shrestha | MIPS augmented with Wavelet Transform, Performance Analysis | |
| Shafer | Embedded vector processor architecture for real-time wavelet video compression |