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Gray et al., 2018 - Google Patents

Towards an area-efficient implementation of a high ILP EDGE soft processor

Gray et al., 2018

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Document ID
246212116677976888
Author
Gray J
Smith A
Publication year
Publication venue
arXiv preprint arXiv:1803.06617

External Links

Snippet

In-order scalar RISC architectures have been the dominant paradigm in FPGA soft processor design for twenty years. Prior out-of-order superscalar implementations have not exhibited competitive area or absolute performance. This paper describes a new way to …
Continue reading at arxiv.org (PDF) (other versions)

Classifications

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