[go: up one dir, main page]

Hoffman et al., 1973 - Google Patents

An 8K b random-access memory chip using the one-device FET cell

Hoffman et al., 1973

Document ID
2825770321039313881
Author
Hoffman W
Kalter H
Publication year
Publication venue
IEEE Journal of Solid-State Circuits

External Links

Snippet

Describes the design, fabrication, and testing of an 8192-b p-channel fully-functional random access memory. Novel features of this device are discussed. Among these are the following: inversion layer capacitor one-device cell; the use of a high speed buffer to …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write (R-W) circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Similar Documents

Publication Publication Date Title
Taguchi et al. A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture
Stein et al. Storage array and sense/refresh circuit for single-transistor memory cells
Wade et al. Dynamic cross-coupled bit-line content addressable memory cell for high-density arrays
Hoffman et al. An 8K b random-access memory chip using the one-device FET cell
Matsumiya et al. A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture
Dennard Evolution of the MOSFET dynamic RAM—A personal view
Oowaki et al. A 33-ns 64-Mb DRAM
US4233675A (en) X Sense AMP memory
Mano et al. Circuit techniques for a VLSI memory
Mano et al. A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology
Blalock et al. An experimental 2T cell RAM with 7 ns access time at low temperature
US6504788B1 (en) Semiconductor memory with improved soft error resistance
Terman et al. Overview of CCD memory
Chu et al. A 25-ns low-power full-CMOS 1-Mbit (128 K* 8) SRAM
Sunaga et al. DRAM macros for ASIC chips
Fujii et al. A 50-μA standby 1M x 1/256K× 4 CMOS DRAM with high-speed sense amplifier
Kirihata et al. A 14-ns 14-Mb CMOS DRAM with 300-mW active power
US4308594A (en) MOS Memory cell
Nagai et al. a 17-ns 4-Mb CMOS Dram
Haraszti A novel associative approach for fault-tolerant MOS RAMs
Barnes et al. A high performance sense amplifier for a 5 V dynamic RAM
Mohsen et al. The design and performance of CMOS 256K bit DRAM devices
Nogami et al. 1-Mbit virtually static RAM
Fuji et al. A low-power sub 100 ns 256K bit dynamic RAM
Pohm High-speed memory systems