[go: up one dir, main page]

Rossi et al., 2005 - Google Patents

Multiple transient faults in logic: An issue for next generation ICs?

Rossi et al., 2005

Document ID
2935932928654647579
Author
Rossi D
Omana M
Toma F
Metra C
Publication year
Publication venue
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

External Links

Snippet

In this paper, we first evaluate whether or not a multiple transient fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. varying supply voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protection against loss of information
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

Similar Documents

Publication Publication Date Title
Rossi et al. Multiple transient faults in logic: An issue for next generation ICs?
Mohanram et al. Cost-effective approach for reducing soft error failure rate in logic circuits
Nicolaidis Soft errors in modern electronic systems
Nguyen et al. A systematic approach to SER estimation and solutions
Mitra et al. Logic soft errors in sub-65nm technologies design and CAD challenges
Sayil Soft error mechanisms, modeling and mitigation
Tang et al. Soft error reliability in advanced CMOS technologies-trends and challenges
Toro et al. Soft error detection and correction technique for radiation hardening based on C-element and BICS
Joshi et al. Logic SER reduction through flip flop redesign
Veeravalli et al. An infrastructure for accurate characterization of single-event transients in digital circuits
Maharrey et al. Dual-interlocked logic for single-event transient mitigation
US20090230988A1 (en) Electronic device having logic circuitry and method for designing logic circuitry
Narsale et al. Variation-tolerant hierarchical voltage monitoring circuit for soft error detection
Neto et al. Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic
Kumar et al. A low power soft error suppression technique for dynamic logic
Niaraki Asli et al. High efficiency time redundant hardened latch for reliable circuit design
Prasanth et al. Reduced overhead soft error mitigation using error control coding techniques
Tajima et al. A low power soft error hardened latch with schmitt-trigger-based C-Element
Anghel et al. Multi-level fault effects evaluation
Bonnoit et al. SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core
Sootkaneung et al. Gate input reconfiguration for combating soft errors in combinational circuits
Wali Circuit and system fault tolerance techniques
Omana et al. Model for transient fault susceptibility of combinational circuits
Ebrahimi et al. Cross-layer approaches for soft error modeling and mitigation
Kalbarczyk et al. Hierarchical approach to accurate fault modeling for system evaluation