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Gupta, 2009 - Google Patents

Design Decisions for Tiled Architecture Memory Systems

Gupta, 2009

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Document ID
3152805054555294407
Author
Gupta A
Publication year
Publication venue
Retrieved from<>, Sep

External Links

Snippet

Tiled architectures have emerged as a solution to translate an increasing number of transistors into single application performance while keeping programming complexity under control through automatic parallelization. Tiled architectures primarily consist of an …
Continue reading at cseweb.ucsd.edu (PDF) (other versions)

Classifications

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    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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