Kolodny, 2009 - Google Patents
Interconnects in ULSI Systems: Cu Interconnects Electrical PerformanceKolodny, 2009
- Document ID
- 3706620513548235558
- Author
- Kolodny A
- Publication year
- Publication venue
- Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications
External Links
Snippet
Integrated electronic systems have advanced in complexity at an exponential rate during the last four decades, as measured by the number of transistors on a single silicon chip [1, 2]. This growth, which had major implications on economy and society, was enabled by …
- 238000005516 engineering process 0 abstract description 21
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5077—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30861—Retrieval from the Internet, e.g. browsers
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Pavlidis et al. | Three-dimensional integrated circuit design | |
| Sylvester et al. | Impact of small process geometries on microarchitectures in systems on a chip | |
| Pavlidis et al. | 3-D topologies for networks-on-chip | |
| Pavlidis et al. | Interconnect-based design methodologies for three-dimensional integrated circuits | |
| Feero et al. | Networks-on-chip in a three-dimensional environment: A performance evaluation | |
| US7739624B2 (en) | Methods and apparatuses to generate a shielding mesh for integrated circuit devices | |
| Mui et al. | A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation | |
| US8881086B2 (en) | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices | |
| Naeemi et al. | Optimal global interconnects for GSI | |
| Elgamel et al. | Interconnect noise analysis and optimization in deep submicron technology | |
| Pavlidis et al. | Interconnect delay minimization through interlayer via placement in 3-D ICs | |
| Moiseev et al. | Multi-Net Optimization of VLSI Interconnect | |
| Khasanvis et al. | Architecting connectivity for fine-grained 3-D vertically integrated circuits | |
| Kolodny | Interconnects in ULSI Systems: Cu Interconnects Electrical Performance | |
| Durrani | Power and thermal modeling approach for homogeneously stacked butterfly fat tree architecture in 3D ICs | |
| Naeemi et al. | Analysis and optimization of coplanar RLC lines for GSI global interconnection | |
| Pavlidis et al. | Physical analysis of NoC topologies for 3-D integrated systems | |
| Mondal et al. | An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC | |
| Balachandran et al. | Package level interconnect options | |
| Moiseev et al. | An overview of the vlsi interconnect problem | |
| Avdalyan et al. | Development of a Method for Reducing the Impact of Metal Interconnection Parameters on the Speed of VLSI | |
| Bamberg et al. | Introduction to 3D Technologies | |
| Ouellette | Analysis, Design and Implementation of High Speed Electrical Interconnects in Si VLSI | |
| Feero et al. | Three-dimensional networks-on-chip: performance evaluation | |
| Pandini et al. | Design methodologies and architecture solutions for high-performance Interconnects |