[go: up one dir, main page]

Di et al., 2014 - Google Patents

Ultra-low power multi-threshold asynchronous circuit design

Di et al., 2014

View PDF
Document ID
3997309999158149823
Author
Di J
Smith S
Publication year

External Links

Snippet

Ultra-low power multi-threshold asynchronous Page 1 University of Arkansas, Fayetteville ScholarWorks(DUARK Patents Granted 3-4-2014 Ultra-low power multi-threshold asynchronous CirCuit design Jia Di University of Arkansas, Fayetteville Scott C. Smith University of Arkansas …
Continue reading at scholarworks.uark.edu (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making or -braking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices using field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
US8207758B2 (en) Ultra-low power multi-threshold asynchronous circuit design
Zimmermann et al. Low-power logic styles: CMOS versus pass-transistor logic
US5796282A (en) Latching mechanism for pulsed domino logic with inherent race margin and time borrowing
JP4417552B2 (en) High speed ratio type CMOS logic structure for pulse input
US7932745B2 (en) Inverting flip-flop for use in field programmable gate arrays
Mukherjee et al. Design & study of a low power high speed full adder using GDI multiplexer
Kong et al. Charge recycling differential logic (CRDL) for low power application
Uma et al. New low power adders in self resetting logic with gate diffusion input technique
Musala et al. Self testing and fault secure XOR/XNOR circuit using FinFETs
Di et al. Ultra-low power multi-threshold asynchronous circuit design
Lee et al. Low power null convention logic circuit design based on DCVSL
Di et al. Ultra-low power multi-threshold asynchronous circuit design
Haulmark et al. Comprehensive comparison of null convention logic threshold gate implementations
KR20220136582A (en) Memory-type camouflaged logic gate using transistors with different threshold voltages
Lo et al. Design of low power differential logic using adiabatic switching technique
Chaitanya Kommu The Mixed Logic Style based Low Power Combinational circuits for ASIC designs at 32nm Technology
Munteanu et al. Single ended pass-transistor logic
Kong et al. CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI
Vishnu et al. Comparative Analysis of Adder for Various CMOS Technologies
Kommu et al. The mixed logic style based low power and high speed 3-2 compressor for ASIC designs at 32nm technology
Kim et al. Camouflaged Logic Gates Using Threshold-Voltage-Defined Memory Cells
Tiwari et al. 2: 1 MUX Design Using Multitudinous Logic Families at 45nm Technology
Charles et al. Delay Optimized Full Adder Design for High Speed VLSI Applications
Abbasian et al. Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications
Uma et al. New low power adders in Self Resetting Logic