CA1058469A - Fluid flow control system for parenteral administration of fluids - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
This invention relates to improvements in fluid flow control systems for partneral administration of medical fluids. Prior art control systems are generally adaptable for only a single type of output device and are often deficient in their regulating accurately over a wide range of flow rates. The present invention overcomes these deficiencies by providing an apparatus and method for improved accuracy of parenteral administration of medical fluids. The inven-tion includes producing a pulse train of variable frequency and pulse width from a digital pulse generation and control system, the frequency and pulse width of the pulses in the pulse train being selected and controlled by the system to establish drop flow rates with digital precision over an extremely wide dynamic range. The invention pro-vides for monitoring the pulse train driving an output control device used in administration of the fluids, in order to detect a abnormal operation of he administration system. The monitoring involves searching for a first pulse width in a prescribed sequence and searching for a second pulse width in the prescribed sequence dif-ferent from the first pulse width to provide an alarm indication.
Duty cycle limitation, appropriate to the particular operating characteristics of the electromechanical output device utilized, is implemented to avoid inducing run-away free flow conditions. Addi-tionally, appropriate alarms respond to system malfunctions to alert medical personnel.

Description

1~5~3469 Tnis lnvention relates generally to improvements in fluld flow control systems and more particularly, to a new and lmproved automatlc, ~elf-regulating, hlghly accur-ate drop flow control system for parenteral admlnlstration o~ medlcal rlulds over a wlde range of fluid ~low rates and capable of utilizlng a variety of different electromechan-lcal output devlces, such as posltive pressure infu~lon pumps uslng stepping motors or the like, as well as con-trollers uslng electrically actuated I.V. tube plnchers.
The usual medlcal procedure for the gradual par-enteral admlnistratlon of liqulds into the human body, such as llquid nutrients, blood or plasma, makes use of appara-tus which is commonly referred to ln the medical art as an lntravenous admlnistration set. The lntravenous set usual- -ly comprises a bottle of liquid, normally upported in an inverted position, an intravenous ~eedlng tube, typically o~ clear plastlc, and a suitable valve mechani~m, such as a roll clamp, which allows the liquld to drlp out of the bottle at a selectively ad~ustable rate into a transparent 20 drlp chamber below the bottle. The drip chamber serve3 the dual ~unction of allowing a n~rse or other attendant to observe the rate at which the liquld drips out o~ the bottle and also creates a reservoir for the liquld at the lower end of the drip chamber to insure that no air enters the ma~n feeding tube leading to the patient~
While observation of the rate of drop ~low via the drip chamber is a simple way of controlllng the amount o~ liquid ~ed to a patient over a periGd of time, its ultl-mate e~ectiveness requires that a relatlvely con3tant 30 vigll be maintalned on the drop flow, lest lt cease entlre-ly due to exhaustlon of the llquid supply or become a contlnuous stream and perhaps lncrease the rate o~ liquid introduction to the patient to dangerous levels.

~ 58 ~

By way of example, it has been the general prac-tlce ln hospltals to have nurses perlodlcally monitor drop flow rate at each intravenous feedlng or parenteral ln-fuslon station. Such monitoring of drop ~low is a tedlous and tlme consumlng process, prone to error and a~sociated, posslble serlous consequences~ and resulting ln a substan-tial reduction of the available tlme of qualified medical personnel for other important dutles. Typlcally, the nurse monitoring drop flow rate wlll use a watch to time the number of drops flowlng in an lnterval of one or more minutes~ and she will then mentally perform the mathematics necessary to convert the observed data to an appropriate fluld flow rate, e.g. J ln cubic centlmeters per hour or drops per minute. If the calculated flow rate ls substan-tially different than the prescribed rate, the nurse must manually ad~ust the roll clamp for a new rate, count drops again, and recalculate to measure the new rate.
Obviously, each of the aforedescribed measurements and calculations and flow rate ad~ustments usually take several minutes time whlch, when multiplied by the number of stations being monitored and the number of times each station should be monitored per day, can result in a sub-stantial percentage of total personnel time available. In addltion, under the pressure of a heavy schedule, the ob-.servations and calculations performed by a harried nurse in measurlng and ad~usting flow rate may not alway~ prove to be reliable and, hence, errors to occur resulting in undesired, possibly dangerous infusion flow rates.
In addition to the aforedescrlbed difficulties, the parenteral admlnistratlon of medlcal liquids by gravity induc~d hydrostatic pressure infu~ion of the liquid from a hottle or other contalner suspended above a patlent, is very susceptlble to fluid flow rate varlation due to changes ~058~t;9 ln the liquld level ln the bottle, changes ln temperature, changes ln the venous or arterial pressure of the patlent, patient movement, and drlf`t in the effectlve ~etting of the roll clamp or other valve mechanism pinchlng the feed-ing tube. Moreover, there are a number of sltuations, such as ln intenslve care, cardlac and pediatric patients~ or where rather potent drugs are being adminlste~, where the desired drop flow rate must be capable of preclse selectlon and must not drift beyond certaln prescrlbed llmits. In additlon~ it ls extremely important ln ~uch sltuatlons for medlcal personnel to be informed of undeslred fluc-tuations in flow rate, ~allure of the fluld dellvery system, or exhaustion of llquld supply when the bottle ls emptled.
It will be apparent, therefore, that some of the most critical problems confrontlng hospital personnel faced wlth an overwhelmlng duty schedule and llmited time avail-abllity are the problems of qulckly, easily, reliably and accurately monitorlng and regulatlng drop flow rate ln the parenteral administratlon of medlcal llquids.
In recent years, a number of electrical monitor-ing systems, drop ~low oontrollers and lnfusion pumps have been developed to accompllsh the varlous tasks of ~enslng and regulating drop flow rates. Some of these devlces have also been capable of activating alarms when a poten-tially dangerous condition exists, thus freeing medical personnel to some extent for other duties. However, while such monitoring and drop rate control devices have gener-ally served thelr purpose, they have not always proven 30 entlrely satlsfactory from the standpoint of cost, com-plexity, stability, reliability, accuracy, adaptability to different types Or electromechanical ~utput devices, or precision of ad~u~tment over a wide range of selected J~05B469 flow rates. In addltlon, such systems have sometlmes been aub~ect to drift and substantial flow rate varlatlons due to changes in temperature feeding tube crimps, variations ln venous or arterial pressure of the patient, or variatlons in the height of the bottle or solution level wlthln the bottle. Substantial dlfficultles have been experlenced partlcularly ln connection with establishing and maintalning such accurate drop flow at very low ~low rates.
Hence, those concerned with the deveiopment and 10 use of parenteral fluid admlnlstration systems~ and particu- -larly those concerned wlth the design of automatic fluid flow control systems, have long recognlzed the need for improved, relatively slmple, economical, adaptable, rella-able, stable and accurate devlces for fluid flow control whlch obviates the aforedescribed difficultles. The present invention clearly fulfllls this need.
Brlefly, and in general terms, the present inven-tlon provldes a new and improved method and apparatus for controlllng drop flow ln the parenteral admlnlætration o~
20 medical llquids, wherein the frequency and pulse wldth of electrical output control pulaes which operate an electro-mechanlcal output control device regulatlng liquld flow in a ~eedlng tube are controlled by a unique digltal system cap-able of senaing and regulating drop ~low rate very accurate-ly over a wide range of ~low rates and wlth a variety of di~ferent electromechanlcal output devices.
The system for establishing the frequency o~ the output pulses to the electromechan~cal control devlce regu-latlng fluld flow is an open loop digltal command system 30 embodying an all digital pulse generation and rate selection subsyatem wherein the output pulse frequency represer,tlng dealred drop flow rate la a relatlvely hlgh, preferably non-lntegral multiple Or the actual drop flow rate rrequencyO

In the case Or ~ome electromechanlcal output control de-vices, as reciprocating I.V. tube pinchers, ~uch a relation-shlp between the commanded output pulse frequency and the deslred drop rate frequency tends to produce less drop dls-tortlon and more consistently repeatable drop size from one drop to another Addltional control over drop flow rate is accom-pllshed by varying the pulse width of the output electrlcal pulses to the electromechanlcal control device, i.e., the time duratlon of the period of energization of the output control device provided by the output pulse. This output pulse width is precisely controlled by a closed loop dlgi-tal system whlch varies the pulse width in dlgital servo ~ashion to establish the desired drop ~low rate while main-talnlng the aforedescribed relationship between the com-manded output pulse frequency and the desired drop ~low rate frequency.
The width of the electrical output pulses to the electromechanical control device is uniquely determined by a dlgital memory subsystem which includes a pair of counters, one counter embodying a ~canning control regi~-ter, the other counter embodying a pulse width register.
The scanning control regl~ter determines the duration of each counting cycle for ltself and the pulse width regis-~er, by initiating and terminating the counting cycle for both registers, the normal rest state ~or the scannlng reg-lster between counting cycles (i.e., the initlal and final state ~or each counting cycle) being its "zero" state.
Initiation of each counting cycle, and each out-put electrical pulse from the overall control system, occurswith each pulse generated by the open loop pulse generation and rate selection subsystem. Each output pulse i~ term-lnated whenever the pulse width register is counted to lts ~ 058469 "æero" state. The count ln the pulse width register at the termination of each counting cycle i8 a measure of the pulse wldth for the electrical output pulse to be gener-ated by the digital system on the next succeeding counting cycle. In thls regard, the pulse width of the output pulse, expres3ed as a function of the content of the pulse wldth register is determlned by the number of counts re-quired to count up the pulse width register from its lni-tlal count state (which is the last count state in the 10 irJmedlately precedlng counting cycle) to lts "zero state, the output pulse being terminated as the pulse width reg-i~ter is counted through "zero".
The pulse width register comes to rest in each counting cycle at a count which determlnes the pulse width for the next output pulse to be generated, each counting cycle being terminated when the scanning control register has counted to "zero". Hence, a unique pulse width digi- ~ -tal memory is provided by the present invention.
In accordance with the invention, the pulse width register is uniformly decremented by a predetermined num-ber of counts relatlve to the scanning control register during each counting cycle, to provlde output electrical pulses of gradually increasing pulse width. The pulse wldth reglster is also incremented a prescrlbed number of counts relative to the scanning control register, each tlme a drop is detected by the system, thereby narrowing the pulse width whenever a drop is detected. The ratio of the number of counts by which the pulse width register is lncremented each time a drop is detected, to the number of counts the pulse width register is decremented during each counting cycle, is the same as the aforedescribed ratio of output pulse frequency to desired drop flow rate ~requency.
Hence, the desired frequency relatlonship is precisely -6~

~()SI51469 establlshed with digital preclslon.
A duty cycle llmltation subsystem overrides the pulse wldth determlnation by the digital memory subsystem ln the event the pulse width prescrlbed by the memory sub-system would exceed an approprlate maximum duty cycle suited to the partlcular electromechanlcal output control device belng utilized, in order to avoid the posslbility o~ lnduclng runaway free flow condltions, due to mechanical limitatlons in the output control devlce, and consequènt 0 108S of control.
The duty cycle llmitation subsystem monitors the commanded period between quccessive initiations of electrl-cal output pulses and, at the desired duty cycle limita-tion point selected for the particular electromechanical output control device being ut81ized, terminates the out-put pulse, providing an instantaneous limltation on the electrlcal output to the mechanlcal subsystem, whlle slmul-taneously speedlng up the counting rate to the digltal memory so that the counting cycle ls completed more rapid-ly. This latter feature also lnsures that the digltal memory will always have completed the last counting cycle prior to lnitiatlon of the next counting cycle, in the event a high pulse frequency is commanded with a perlod between initiation of output pulses shorter than the count-lng cycle o~ the memory at the normal counting rate. How-ever, the accelerated countlng rate to the digltal memory provided by the duty cycle llmltation subsystem insures completion of each counting cycle even at the h~ghe~t sele~
ted output pulse rates.
A start-up subsystem, effectlve only during inl-tial operation of the system or after comlng out of an alarm state, temporarily controls the rate selectlon and memory subsystems and accelerates inltlal pulse wldth .

lOS~469 regulation to more rapidly achieve normal operating con-ditlons. In this connection, the pulse wldth reglster i~
decremented by a greater number of counts per counting cycle during the start~up phase to increa~e the width o~
the electrical output pulses more rapidly. In addition, -and only during the start-up phase, the rate selection subsystem is preset internally to a prescrlbed rate, to ; insure that the output pulses are not comlng too slowly or too rapidly during initlal ad~ustment of the overall 10 system. The start-up phase continues untll a prescribed number of initlal drops have been detected, at which time the start-up subsystem relinqulshes control, and normal pulse rate control and output pulse width ad~ustment occurs for subsequent drop flow beyond the initial few drops de- -tected.
For certain types of electromechanical output control devices, partlcularly those capable o~ runctioning properly with very narrow pulse width input, the system of the present lnventlon is capable of functioning normally on an expanded low level operational basis, without going into alarm, by storing and processing the equivalent of negative pulse width in the digital memory. Thls condition may occur with normal low level operation in whlch ex-tremely narrow pulse wldths are generated, so that further incrementlng of the pulse width register upon detection of drops causes the pulse width register to overflow.
Overflow of the pulse width register countwise is equlvalent to underflow of pulse width, i.e., negative pulse width, whlch is manifested by the sudden transition ~rom a very narrow output pulse (a high count in the pulse width register) to a very wide output pulse (a very low count in the pulse width reglster~. Assuming the system 18 operating to provlde normal fluid flow, i.e., there are no flow condltlons warranting generation of an alarm state, the negatlve pulse wldth condltion will be only tran~l-tory, and successive decrementing of the pulse wldth regis-ter in succeeding counting cycle~ should bring the digltal memory out of the negatlve pul~e wldth region and restore normal narrow output pulse generatlon. Hence, the cap-abllity of operatlon ln the negative pulse width region by the system of the present inventlon enables an expanded dynamic range of operatlon wlthout the need for expanding the count capaclty of the digital memory.
The electromechanical output control devlces which may be utllized with the system of the present invention generally fall lnto one of two categories,.positlve pres-8ure infuslon devlces such as pumps, or devlces which sim-ply open and close a feedlng tube and are dependent upon gravlty lnduced hydrostatic pres~ure for produclng drop flow. The latter category lncludes I.V. tube pincher de-vices whereln a feeding tube clamplng member, normally ln the tube shut-off positlon, is repeatedly moved to the tube 20 open posltlon by a suitable electromechanical driver whlch ls, ln turn, energized by the electrical output pulses from the previously descrlbed dlgltal system.
Since ~ravity induced hydrostatic pressure ls a function of such parameters as the height of the bottle, the liquid level in the bottle, and the size and flexi-bility of the feeding tube, and each of these parameters can be altered, it i8 deslrable to vlsually observe an indicatlon of the output pulse width operating range ~o that, ln the event pulse width is not in the optlmum range, ~;
suitable ad~ust~ents can be made, such as raising or lower-ing the helght of the bottle, to establish hydrostatlc pressure levels in the feedlng tube approprlate to pulse wldth generatlon in the optimum region Or operation. The *0584tj9 pre~ent system provides such a vl~ual indicatlon by moni-torlng the status of the pulse wldth reglster and lndlca-tlng, by means of a pair of lights) whether the electrical output pulses being generated by the system ~all wlthin the high, low or optlmum pulse wldth ranges.
The dlgltal memory ~tatus ls al~o monitored so that out-of-llmit condltlon~ calllng for flow rate~ in excess o~ system delivery capablllty, or lndlcatlng a leakage ~low rate which cannot be terminated by the output control device, trigger appropriate alarm subsystems The ~ystem provides the flexibillty of a hlgh level alarm which lndicate~ a demand fo. too wide an output pulse, a varlety Or low level alarms responsive to speclfied non-tolerated sequences of pul~e widths, includlng excessive negative pulse widths for certain types of output control devices.
In addition, in order to warn approprlate medical personnel of an exhausted liquld supply or any other condi-tion in the administration ~et preventlng ~luld dellvery, the alarm subsystem system is responsive.to a lack of drop flow detected in a predetermined perlod of time and as a function of a predetermlned number of electrical events in the control system. In this regard, the system alarm~ i~
no drops are detected after a prescribed number of output pulses have been commanded by the open loop pulse genera-tion subsystem, and the system wlll also alarm lf no drop~
or output electrical pulses have occurred ln a prescribed time interval.
The new and improved fluid flow control system o~
the present invention ls extremely accurate, reliable and 30 easy to use. The sy~tem provldes enhanced dlgital pre-cislon ln selecting and maintainlng drop flow rates through-out a wlde range, and the system is qulck to lnform med-lcal personnel of any condltlons whlch mlght pose a hazard to the patient. Hence, the system of the present invention minimizes the time cons~ming and error prone aspects of human monitoring and flow rate adjustment and provides substantial improvement in economy, adaptability to a var-iety of different mechanical output control devices, reli-ability, stability and accuracy over previous automatic control systems.
In one aspect of this invention there is prov~d~d a method used in the parenteral administration of medical lQ liquids via an output control device. The method comprises the steps of: monitoring a pulse train representing output pulse intedded to be generated for driving the output control device; searching for a first pulse width in a prescribed sequence; and searching for a second pulse width in said prescribed sequence. The second pulse width is of different duration than said first pulse width to provide an alarm indi-cation.
These and other objects, advantages and aspects of the invention will become apparent from the following more de-2Q tailed description, when taken in conjuction with the accompanying drawings of illustrative embodiments.
FIGURE 1 is a block diagram of an overall system in which some of the basic concepts of the fluid flow con-trol system of the present invention are embodied;
FIGURE 2 is a graphical representation illustra-ting typical drop size as a function of putput pulse fre-quency;
FIGURE 3 is a graphical representation of output pulse width as a function of time;
FIGURES 4a, 4b and 4c are combined block diagrams and electrical schematics of one embodiment of an overall fluid flow control system in accordance with the present .

105~346~

invention, FIGURE 4a being primarily directed to the input and timing subsystem and the output subsystem, FIGURE 4b being primarily directed to the memory and control sub-systems, FIGURE 4c being primarily directed to the visual pulse width monitoring subsystem and alarm subsystem;
FIGURES 5a-5h are graphical representations illus-trating various electrical states in the overall control -: system of FIGURES 4a, 4b and 4c for a variety of conditmons of operation which demonstrate the functioning of the duty cycle limita~on subsystem;
FIGURES 6a-6g are tables illustrating register and ~lla~

~ 05846~
~llp-flop ~tates in the overall system of FIGU~ES 4a-4c ~or a varlety of dlf~erent conditlons under whlch drops may be detected;
FIGURES 7a and 7b and FIGURES 8a-8d are waveforms ~or various portions of the overall 3y~tem o~ FIGURES 4a-4c when the ~ystem ls being operated ln the pump mode; and FIG~RES 9a, 9b, lOa and lOb are waveforms for various portlons of the overall system of FIGURES 4a-4c when the system ls belng operated in the controller mode.
Referring now to FIGURE 1 of the drawlngs, there is ~hown a new and improved system for fluld flow control embodying features of the present lnventlon. In the en-suing description, while reference wlll be made to the term "I.V." normally connotlng lntravenous adminl~tration, it ls to be understood that thl3 is by way of example only, and the flow control system o~ the present lnventlon i9 suit-able ~or other forms of parenteral administration as well a~ intravenouB admlnistration.
In order to control drop flow rate, it is neces-sary to continuously monltor the actual drop flow as itoccurs ln an I.V. administration set. This is accom-pllshed in the system of FIG~RE 1 by a drop detectlon sub-system 11 which lncludes a drop sensor lla and a pulse generator llb, both well known in the art, adapted to detect each drop as it falls and generate electrlcal pulses at a frequency equal to the drop flow rate.
The drop sensor lla monitors drop flow in a drip chamber (not shown) of the I.V administratlon set and typlcally may lnclude a sensor housing (not shown) con-taining a reference llght source located a flxed distance from a photocell to deflne an optical senslng gap there-between, wlth a re~erence light beam normally implnging upon the photocell. Th~ houslng ls appropriately clamped ~0584~9 upon the drip chamber of the I.V setJ wlth the transparent drlp chamber positioned withln the senslng gap to lnter-cept the reference beam. A falling drop of liquid wlthln the drip chamber interrupts the reference beam, and the variation ln electrical response of the photocell ls dlrected to appropriate circuitry indicating the presence of a drop. One example of a suitable drop sensor lla ls set forth in ~. S Patent No. 3,596,515, inventor, Richard A. Cramer. While a photocell monitoring device is ldeally sulted for the drop sensor lla, it will be appreciated that any drop sensing device capable of provlding an elec-trlcal indication of the detection of a drop may be used wlthout departing from the spirit and scope of the inven-tion.
The pulse generator llb is typically a conven-tional monostable flip-flop (one-shot) which provides an output pulse each tlme a drop is detected by the drop sen~or lla, the output pulses having a presorlbed pulse width and amplitude compatible wlth the input clrcult re-quirements of the particular monitoring and control systemutillzed. The pulse output from the pulse generator llb, representing the detected drop flow rate, is directed a~
one input to a memory control subsystem 13, and is also d irected as input to an alarm subsystem 14.
Fluld flow in the feeding tube of the I.V. admln-l~tratlon set is regulated by the system of the present invention vla an electromechanical output control device 15 whlch, in turn, is periodlcally energized by receiving a~ 01ectrical input the pulsed output over line 17 from an output pulse control subsystem 16.
A variety of different electromechar.ical output control devices 15 can be used with the system of the present invention, such as positive pressure infusion ~058469 pump~, driven by a d.c stepping motor, or other type~ ofa.c. or d.c. motor~, or devlces which slmply open and close a feeding tube and are dependent upon gravity in-duced hydrostatlc pre~sure for drop flow, l.e., a drop flow controller rather than a pump. By way of example, the sy~tem of the present invention is described in con-nectlon with the operatlon o~ two di~ferent types o~ out-put control devices, one from each of the aforedescrlbed categorle~.
In the ln~uslon pump categoryJ a d.c. stepplng motor i8 employed as a drlve for the lnfusion pump to provlde a stepped incremental mechanlcal output to a ~lurallty of cam followers or the like (not shown) whlch ma~age the I.V feeding tube and generate a peristaltic pumping action capable o~ developing a substantlal posi-tiYe pressure in the feedlng tube.
In the flow controller category, the controller lncludes an I.V tube pincher device wherein a feeding tube clamping member, normally spring biased to the tube shut-off position, iB repetltlvely moved tothe tube-open po3ition by a suitable electromagnetic driver which ls, in turn, energized by the electrical output pulses over line 17 from the pulse control subsystem 16. Each output pulse directed to the output control device 15. in the case of the controller, causes the clamplng member to be retracted and thereby opens the feedlng tube ~or the duratlon of the output energlzing pulse width. ~y way of example, the I.V. controller output control device 15 may be o~ the type set forth in U.S Patent No. 3,756,556, inventor, Helnz W. Georgi.
In the case of the stepping motor infuslon pump, each electrical output pulse over line 17 from the pulse control ~ubsystem 16 gates on a burst of ~tepplng motor 105~3469 driver pulses, the duration of the drlver pulse burst substantially ~atching the duration of the output ener-gizlng pulse width. Each driver pulse steps the motor a precisely defined rotational increment and thereby peris-taltically induces fluid flow in the feeding tube by ad-vanclng a body of fluid trapped between the cam followers.
While the invention ls described in detail, by way of illustration, ~n connection with the aforementioned stepplng motor infusion pump and I.V. controller as typical output control device~ 15, it will be appreciated that other output control devices can be readily utilized within the ~ramework of the system d~scribed~ without departing from the spirit and scope of the invention. .
A pul8e generation and rate selection sub~ystem 18, which is an open loop digital command subsystem, e~tablishes the frequency of the output pulses produced b~
the system over line 17 to the output control device 15.
The subsystem 18 is an all digital pulse generatlon sub-system which generates a pulse frequency output over line 19 to the output pulse control subsystem 16 and directs the same output over line 20 to a digital memory subsystem 21.
The deslred drop flow rate ls selected by the operator through ad~ustment of the pulse generation and rate selection subsystem 18. The output pulse frequency from the subsystem 18 ls, ln accordance wlth the lnventlon, not the actual drop flow rate deslred, but rather a rela-tively high, preferably non-lntegral multiple of the actual drop flo~ rate frequency, e.g., typically a ratlo Or 10-1/2.
In the case of some electromechanlcal output control de-vlces 15, such as reciprocating I.V. tube pinchers, such a relatlonship between the commanded output pulse fre-quency and the deslred drop rate frequency tends to produce lOS8469 les~ drop distortion and more consistently repeatable drop 3ize from one drop to another. This is apparent from FIG~RE 2 o~ the drawings whlch illustrates typical drop size as a functlon o~ output pulse frequency using an I.V.
controller. The baslc concept of uslng such a high, non-integral ratlo of output pulse ~requency to desired drop flow rate frequency wlth I.V. controllers has been pre-viously set forth ln ~.S Patent No. 3,800,794, issued April 2, 1974, to the same inventor as the pre~ent appli-10 cation. However, an analog memory and dlf~erent type ofcontrol subsystem ~s taught in the aforementioned U. S.
Patent No. 3,800,794 than in the present appllcatlon.
The command pulses ~enerated ove~ line 19 to the output pulse control subsystem 16 determine the initiation of each output pulse over line 17 to the output contro~
devlce 15, whereas the termination of each output pulse i8 determlned by the digital memory subsystem 21 which dlrects an input over line 22 to the ~ulse control sub-system 16. Henc, ln addition to the output pulse ~re-20 quency control provided by the pulse generatlon and rateselection subsystem 18, addltional control over drop flow rate is accompllshed by var~ing the pulse wldth of the output electrical pulses to the control devlce 15, l.e. J
the tlme duration of the perlod o~ energizatlon of the output control device provlded by each electrical output pulse on line 17. The outp~lt pulse wldth is preclsely controlled by a closed loop dlgital subsystem, whlch in-cludes the digi~al memory subsystem 21, and which varles the pulse wldth ln digital servo fashion to establish the desired drop flow rate while always maintaining the afore-described relationship between the comman* outpllt pulse ~requency and the desired drop ~low rate.
The wldth of the electrlcal output pulses to the , ~058469 output control device 15 is uniquely determined in the Aystem of the present invention by the diglral memory sub-system 21 in con~unctlon with the memory control subsystem 13, which, in turn, receives lnformatlon not only from the digital memory subsystem but also from the drop de-tection subsystern 11 whlch includes the drop sensor lla and pulse generator llb.
The digital memory subsystem 21 includes a palr o~ dlglbal counters, one counter embodying a scarning control reglster, the other counter embodying a pulse width reglster. These registers undergo a countlng cycle whlch is lnltiated each tlme a pulse is generated over llne 20 by the pulse generation and rate selection sub-system 18, and each counting cycle must be completed be-fbre the next pulse ls produced on line 20. The scanning control reglster determines the duration of each counting cycle, for ltself and for the pulse width register, by inltlating and terminating the counting cycle for both regi3ters, the normal rest state for the scannlng register between countlng cycles (l.e., the initial and ~inal state for each counting cycle) belng its "zero" state.
As prevlously lndlcated, not only is initiatlon of eaah counting cycle determlned, but each output elec-trlcal pulse from the system over line 17 1~ also ini-.tiated, with each pulse generated by the open loop pulse generatlon and rate selection subsystem 18. Each output pulse over line 17 to the control device 15 ls ter~inated whenever the pulse width register of the memory subsystem 21 is counted to its "zero" state.
The final count in the pul~e width register at the termination of each counting cycle is a measure of the pulse wldth for the very r~xt electrlcal output pulse to be generated by the system over line 17 on the next _~7_ - 1~58469 succeedlng counting cycle. In this regardJ the pulse width of the output pulse over line 17 to the control device 15, expressed as a function of the pulse width register count, is determlned by the number of counts required to count up the pulse width register from lts lnitlal count state (which is the final count state in the immediately preceding counting cycle) to lt~ "zero"
state, the output energizing pulse to the control devlce 15 being terminated as the pulse width register is counted through æero. The latter state if communicated over llne 22 to the output pulse control subsystem 16.
The pulse wldth reglster comes to rest in each counting cycle at afinal count which determines the pulse wldth for the next output pulse to be generated over line 17, each countlng cycle being terminated when the scannlng control register has counted to lts "zero" state.
In accordance with the invention, the pulse width register in the digital memory subsystem 21 ls uniformly decremented by a predetermined number of counts relative 2n to the scanning control register durlng each counting cycle, to provide output electrical pulses of gradually increaslng pulse width. The pulse width reglster i~ al~o lncremented a prescrlbed number of counts relative to the scanning control register each time a drop is detected by the drop sensor 11J thereby narrowing the pulse width whenever a drop ls detected. This ls accompllshed vla the memory control subsystem 13.
The ratio of the number of counts by which the pulse width reglster is incremented each time a drop is detected, to the number Or counts the pulse width register is decremented during each counting cycle, is the same as the aforedescribed ratio of commanded output pulse fre-quency to desired drop flow rate frequency. ~y way of ~ 1~584~9example, in a presently prererred embodlment of the system of the present inventlon, the pulse wldth reglster i8 de-cremented by 2 counts durlng each counting cycle and in-cremented by 21 ~ounts each time a drop is detected by the drop sensor lla. Hence, the deslred input to output fre-quency ratio of 10~ ls precisely established ln the digital memory subsystem 21.
The manner in which ~he output pulse wldth over line 17, lndicated in terms o~ the counts stored in the pulse wldth reglster o~ the memory subsystem 21, varles as a runction of tlme ls illu~trated in FIG~RE 3 o~ the draw-ing~. It will be apparent from FIG~RE 3 that the output pulse wldth varies as a staircase ~unctlon, with each in-crea3e in pulse width being 2 counts decremented ~rom the pul~e width register and each decrease ln pulse width being 21 counts lncremented lnto the pulse wldth reglster at the point Or drop detectlon.
The wldth Or each step ~n the stalrca~e waveform i~ a ~ime perlod whlch is the reclprocal of the output 0 pulse frequency on llne 17, or _1 x drop rate. It 103~-will be noted that each stalrcase pattern between succes-slve drop detectlon events varles ln the number o~ pulse periods or steps included, the patterns alternatlng in 10 and 11 pulse perlod groupings to provide an average lnter-val between successive drop detections Or 10~ pulse periods, the desired ratio.
A start-up subsystem 12 is erfectlve during lnl-tlal start-up of the overall system, as well as each time the system is brought out Or an alarm state. In this re-gard, the system starts out with both Or the reglsters ofthe digital memory subsystem 21 reset to their "zero"
states, so thst normal operatlon Or the system would pro-duce extremely narrow inltlal output pulses over llne 17.

-lg-105~3469 The start-up subsystem alters the normal operation of the memory control subsystem 13 by accelerating inltlal pulse wldth regulation by the digital memory subsystem 21 to more rapidly achieve optlmum performance conditlons by qulckly brlnging the output pulse wldth o~er line 17 closer to its ultimate range of pre~erred operation. In order to accompllsh thls, the pulse width register ls caused to be decremented by a greater number o~ counts per counting cycle during the start~up phase, to increase the width of the electrlcal output pulses more rapidly. Typically, lnstead of increasing pulse wldth by only 2 counts in the pulse width register each counting cycle, as is done during normal operation~ the pulse width is increased by 9 counts during each counting cycle. This increases the width of electrical output pulses much more rapldly than would occur if the optimum pulse width operating range were approached by the much slower 2 count per counting cycle incresse in pulse width.
In addition, and only while a start-up phase o~
operation is in ef~ect, the pulse generation and rate selection subsystem 18 is temporarily set internally by the start-up system 12 to a pr0determined output pulse rate most suitable for initial ad~ustment o~ pulse width.
The start-up phase continues until a prescribed number of initial drops, typically two drops, have been detected by the drop sensor lla, at which time the start-up subsystem 12 relinquishes control, and normal ~utput pulse wldth ad~ustment, l.e., 2 counts of the p~lse wldth reg~ster per counting cycle, occurs for all subsequent drop 30 flow beyond the initial two drops detected.
A duty cycle limitation subsystem 23 overrides the pulse wldth determination by the dlgital memory sub-system 21 in the event the pulse width prescribed by the ~ 05~3469 memory subsystem would exceed an appropriate maximum duty cycle for the particular output control devlce 15 being utillzed by the system, in order to avoid the posslbillty Or inducing runaway free flow condltions. Such runaway conditions may occur due to mechanical llmltatlonsJ e.g., lnertla, of the output control devlce 15, and consequent lo~s of control over ~luid ~low in the feedlng tube may result. The duty cycle of the output control devlce 15 ls de~lned as the ratio of the time that the output control device is energized, to the total period o~ time between lnitiatlons of successive outputpul~es over llne 17 driving the output control device.
The duty cycle limltation subsystem 23 receives input over line 24 ~rom the pulse generation and rate sele~
tlon subsystem 18 to enable the duty cycle subsystem to monltor the commanded perlod between lnltlation of suc-cessive electrical output pulses, as specifled by the pulse generation and rate selectlon subsystem. At the desired duty cycle limitatlon point for the particular electro-20 mechanlcal output control device 15 belng utilized, thed~ty cycle subsystem 23 termlnates the output pulse on line 17 (1~ it has not otherwise been terminated by the memory subsystem 21), by directing a termination input over llne 25 to the output pulse control subsystem 16, thus providing an instantaneous limitation on the electrical output to the mechanical subsystem. Slmultaneously, the duty cycle lim~tation subsystem 23 speeds up the counting rate to the ~gital memory subsystem 21 so that the countlng cycle is completed more rapidly. The latter ~eature i~ lndicated 30 schematically by an lnput over line 26 to the memory sub-~ystem 21 from the duty cycle subsystem 23, to alter the counting rate normally provided by a clocklng subsystem 27 provlding an input over llne 28 to the memory subsystem.

~58469 The clocking subsystem 27 ls also illustrated as driving the pulse generation and rate selection subsystem 18. In this regard, the clocking subsystem 27, whlle shown for purposes o~ simpllcity as providing inputs only to the pulse generation and rate selection subsystem 18 and dlgl-tal memory subsystem 21, actually provides clocking inputs to all o~ the subsystems to maintain synchronous operation wherever required.
The manner in which the duty cycle llmitation sub-10 syatem 23 increases the counting rate to the digltal memory subsystem 21 is by switching, at the duty cycle llmlta-tlon point, from a countlng rate which is normally at one-tenth of the full clock rate, to countlng at the full clock rate, whereby completion of the counting cycle is accelerated. The latter feature also lnsures that the digital memory subsystem 21 will always have completed its last counting cycle prior to initiat~on of the next count-ing cycle by a pulse received over llne 20 from the pulse generation and rate selection subsystem 18. In the event 20 a high pulse frequency is commanded by the pulse generation and rate selection subsystem 18, the perlod between ini-tiation of pulses over line 20 may be considerably shorter than the period requlred for the countlng cycle of the dlgital memory subsystem 21 at the normal counting rate.
However, the accelerated countlng rate lntroduced by the duty cycle llmltatlon subsystem 23 insures completion of each countlng cycle by the digital memory subsystem 21 even at the highest selected output pulse rates whlch the over-all system is designed to produce.
It has been determined, by experlence, that the maxlmum duty cycle suitable ~or a typical I.Y. controller using an electromagnetically reciprocated I.Y. tube pincher, is considerably less than the maximum duty cycle ~05846~

permissible with a stepping motor lnfusion pump. The reason for thls is that the mechanical inertla of the spring-biased I.V tube pincher is typically of sufflcient magnltude that, i~ the duty cycle ls made too large, the plncher cannot close off the feed~ng tube completely be-fore being required by the next output pulse on line 17 to re-open the feeding tube. This can result in a floating action which fails to completely pinch off the ~eedlng tu4e and consequently may produce a free flow state~ Once such continuous ~low occurs, the fluid ~low may no longer be divided into incremented drop flow. When no drops are detected by the system, the pulse width will normally be made even wider, making condltions still worse.
It hss been empirically determined that, ~or I.V.
controller applications using an electromagnetically reciprocated tube pincher, a duty cycle limitation o~ 40 percent is pre~erable, whereas a duty cycle limitatlon o~
75 percent is typically suitable for a positive pressure infusion pump using a d~c. stepping motor drlve. Where other types of electromechanical output control devices 15 are utllized, it will be appreciated7 o~ course, that other duty cycle limitations sultable to the particular control device selected, may be prescribed in accordance with the teachings of the present invention.
~ In the case of the I.V. controller, which is de-pendent upon gravity induced hydrostatic pressure ~or ln-duclng drop flow, it is desirable to vlsually observe an indlcatlon of the output pulse width to the control devlce 15 so that, in the event pulse width is not in the optlmum operatlng range, sultable ad~ustments can be made in the external I.V. administration system, such as raising or lowering the height of the bottle, to establish proper hydrostatic pressure levels in the feedlng tube appropriate ~ OS8469to pulse wldth generatlon ln the desired region of opera-tlon. In this connectlon, a visual pulse wldth indicatlon ~ubsystem 29 r~celves lnformatlon over line 30 from the pulse wldth register of the digital memory subsystem 21 and decodes the pulse width into pulse width operation ranges .
By means of a pair o~ lights, the pulse width indlcatlon subsystem 29 indicates whether the electrical - output pulses being generated by the overall syste~ on lO line 17 to the output control device 15 fall within de-fln~d hlgh. low or optimum pulse width ranges In a presently preferred embodiment o~ a visual pulse width indicatlon subsystem sultable ~or use with an I.V. con-troller~ a green light indicates the low pulse width range, a red light indicates the hlgh pulse width range, while energization of both a red and ~ green light lndicates that operation is in an optimum pulse width range.
An alarms subsystem 14 receives inputs from a : tlmer 31, and ~rom portions o~ the pulse generatlon and 20 rate selection subsystem 18, the digital memory subsystem 21, the output pulse control subs~Jstem 16, the memory con-trol 3ubsystem 13, the start-up subsystem 12 and the pulse generator llb o~ the drop detection subsystem. These in-puts are used, in a manner to be speclfically described :
hereinafterJ to monitor system performance so that out-of-llmit conditlons calling ~or flow rates ln excess o~ system -~
dellvery capability, or indicating a leakage flow rate which cannot be terminated by the output control devlce, ~rigger an alarm state which resets the entire system and 30 prevents further system operation until the alarm condl-tlons have been corrected and another start-up phase has been lnltiated.
The alarms SUbsystem 14 provides a hi2h level ~ 0584bi9 alarm responsive to a demand for an excessive output pulse width over llne 17. The ~ub~ystem 14 also provides a pair o~ low level alarm~) each one sultable to a di~erent type of output control device 15J and each responsive to speclfied non-tolerated sequences of pulse width. As will become apparent in connectlon with the descriptlon of the preferred embodiment, the stepping motor infusion pump may operate properly ln the negatlve pulse width region o~
the pul~e width register and, in thi~ regard, the low level alarm provlded by the system of the present lnventlon will !`` only be responslve to a requlrement for excessive negatlve pulse width which indicate~ the posslblllty of a runaway free flow condltlon with the pump. However, whlle the ~ystem may continue to operate electrlcally in the negative pulse region, electrical output to the output control devlce 15 19 gated off during this perlod of operation and this ls lndicated schematically b~J an input over llne 33 to the output pul~e control subsystem 16 from the alarms subsystem 14 In addition to the high level and low level alarms, the alarms subsystem 14 is responsive to a lack of detection o~ any drop ~low within a predetermined period o~ time and as a function o~ various electrical events occurring in the pulse generation and rate selectlon sub-system 18, the memory control subsystem 13, the start-up subsystem 12 and the output pul~e control subsystem 16.
In t~l~ connection, the alarms sub~ystem 14 generates an alarm state i~ no drops are detected after a prescrlbed number o~ pul~es has been generated by the pulqe generatlon and rate selection subsystem.
In addition, the systeni will also alarm in a "no action" mode i~ in any pre3cribed time period dur~ng normal operatlon, there are no drops detected by the drop -~5-.. .

` ~05~a~69 sen~or lla nor electrical output pulses occurring on line 17. The prescribed time period for the "no action" alarm, is typically approximately six minutes a time interval compatlble with the lowest drop rate frequencies which the system might be utilized to generate in normal operation.
Referring now to FIGU~ES 4a, 4b and 4c o~ the drawings each of these figures are comblned block dlagrams and electrical schematic~ of portions of a fluld flow control system ~n accordance wlth the present lnvention, and the figures are arranged wlth thelr respectlve input and output connectlons allgn~d so that the three figures can be used as a Ringle drawing for the entlre fluid ~low control system. In this regard, the various subsystem electrical connections overlap with each other to such a degree that the system ls best described wlth regard to the combined figures, and the balance ofthe description will accordlngly be made with reference to such a composite drawing.
Prior to a detalled descriptio~ of the operation o~ the overall system depicted ln FIGURES 4a, 4b and 4c, the main elements of each ma~or subsystem area, and their , functions, will rirst be summarized.
FIG~RE 4a primarlly ls directed to the lnput, tlming and output sections of the overall system whlch would include, ref`errlng to FIGURE 1 prevlously dlscussed, the pulse generatlon and rate selection subsystem 13. the duty cycle limitation subsystem 23, the clocking subsystem 27, the output pulse control subsystem 16 and the output control device 15.
FIGURE 4b relates prlmarily to the memory and control sectlons of the overall system and, referrlng agaln to FIGURE 1, primarlly includes the digltal-memory subsystem 21, the drop detectlon su~system 11, the memory 105~4~j~

control subsystem 13 and the start-up subsystem 12.
FIG~RE 4c is dlrected prlmarily to the details o~
the alarms subsystem 14, the visual pulse width indication subsystem 29 and the tlmer 31.
Referring now to FIGU~ES 4a, 4b and 4c as a composite system diagram, a conventional clock generator 40 directs pulses over line 41 to a conventional digltal xate multiplier 42 which embodies a plurallty o~ digital rate selector switches 42a.
The rate multiplier 42 multiplies the input fre~
quency by a maximum factor o~ unlty. The output of the rate multiplier 42 over line 43 is a pulse rate propor-tional to the setting of the rate selector switches 42a and, therefore; proportlonal to the desired drop flow rate to which the system is lntended to stabilize. The output of rate multiplier 42 over line 43 is not a continuous pulse train, but rather an irregular burst of pulses, due to the nature of the fractional multlplication which can occur in the rate multiplier. The typically non-uniform 20 pulse train on line 43 is directed to a conventional divider 44 which smooths out the ~itter in the pulse train.
The electrical output o~ the divider 44 is direc-ted to a decoder 45 whlch decodes out different states of the divider 44 for duty cycle limltation purposes and to generate the reference pulse train for the system which controls the initiation of each counting cycle and the initiation of outputpulses from the overall system. The latter ls the pulse generated each time the divider 44 is counted to its "zero" state (hereinafter referred to as 30 the "DRZ" slgnal) and corresponds to the output of the pulse generation and rate selection subsy~tem 18 o~ FIG-URE 1. `
The clock frequency generated by the clock 40 is ~05~3~69 ln a presently preferred embodiment of the inventlon,selected to be 71.68 kilohertz. The rate multiplier 42 multiples the clock frequency by l/lOOth of the drop rate selected and dialed in on the rate selector switch~s 42a.
For example, assuming a selected drop rate Or 30 drops per mlnute, the output frequency on llne 43 would be:
input frequency to divlder 44 = 71.6180x~ 30 c 21.504 kilohertz The dlvider 44 ls selected as a register having a count capaclty of 212 or 4096. Therefore, the output frequency o~ the DRZ pulse train is:
DRZ frequency = ~ 046X 10 = 5.25 hertz = 315 pulset It will be noted that the latter result is exactly 10-1/2 tlmes the selected drop rate of 30 drops per mlnute.
Hence, the clock 40, rate multlpller 42 and divider 44 are selected to provlde the de~ired frequency ratio relatlon~
ship between the output pulse train and the drop flow rate deslred The DRZ slgnal output from the decoder 45 is an open loop command s~gnal directed over line ~6 to other portlons of the system.
Two other output lines 47, 48 ~rom the decoder 45 decode out those states whlch represent certaln count-lng ranges o~ the divider 44. The output llne 47 from the decoder 45 represents a count o~ 3072-4095 o~ the divider 44 which iB the last 25 percent o~ the count capaclty o~ the dlvlder The line 48 represents a count range of 1664-4095 and represents the last 60 percent of the count capacity of the dlvider 44 Therefore, ~or the time period between successive DRZ pulses generated by the decoder 45 over line 46, the decoder output llne 48 wlll be "false" ~or the first 40 percent o~ the period and wlll be "ture" ~or the last 60 S84~6~

percent of the perlod up to the next DRZ pulse. The other output line 47 from the decoder wll~ be "false" for the first 75 percent of the period between DRZ pulses and "true" ~or the last 25 percent. These slgnals on output lines 47, 48 from the decoder 45 control the duty cycle llmltation subsystem. The signals on lines 47 and 48 are fed to a pair of AND gates 49, 50, respectively, which, in turnS direct their outputs to an OR gate 51. The output from gate 51 over line 52 ls the duty cycle limitation 10 control signal.
Slnce the overall system of FIG~RES 4a, 4b and 4c, is lntended for use with elther a pump or a controller, the gates 49 and 50 are used to select the particular duty cycle limltation deslred. either a 40 percent or a 75 percent output limitation depending upon the particular output control devlce intended to be utilized with the system. This is accomplished by a ~umper connection 53 which ls selectlvely lnstalled elther in the "controller"
positlon or the "pump" position.
Depending upon which operatlonal ml,de is ~elec-ted, either an electrical "zero" or an electrical "1"
signal le fed over line 54 as input to the duty cycle ~ub-system. When the "controllerl mode o~ operatlon i8 selec-ted, the "zero" input passes over line 55 as a ~alse"
input to the A~D gate 49, thus disabling the gate 49. In contrast, the "zero" lnput is inverted, by an inverter 56, to provide a "true" input over line 57 to the AND
gate 50 which will thereby have an output dependent upon the ~tatus o~ line 48 from the decoder 45. Tllus~ the 30 output of the gate 50, which also passes through the OR
gate 51, will be "true" dur~ng the last 60 percent of the period between each palr of DRZ pulses.
Similarly, if the "pump" mode is selected, a .

1~)584~;9 "l" ~lgnal lnput will be directed over line 54 to the duty cycle llmltatlon subsy~tem and, hence, gate 49 will be enabled and gate 50 will be disabled, whereby the status Or the output line 47 from the decoder 45 wlll be passed a~ "true" lnput to the OR gate 51 whose output over llne ~2 wlll be "true" only during the la~t 25 percent of the period between each pair o~ DRZ pul~es.
Hence, lt will be apparent that, depending upon which mode o~ operatlon ls selected, "controller" or "pump", a duty cycle limltation of elther 40 percent or 75 percent, respectively, will be lmposed on the sy~tem as represented by the signal on line 52.
~ he output nf the clock generator 40 i~ also directed over llne 58 to a divlde by ten counter 59 which dlvides the clock frequency by a factor of lO and feed6 the reduced clock frequency over line 60 to an OR gate ; 61. m e OR gate 61 also receives an input over line 62 ~rom an AND gate 63 which has a~ lts input~ the duty cycle control signal on line 64 and the full rate clock slgnal on line 65. Hence, the output of the OR gate 61 over llne 75 is the clocking signal (hereinafter referred to a~ the "CLK" slgnal) for the entire system.
The CLK slgnal will, however, change lts fre-quency from the full clock rate produced by the clock generator 40 to l/lOth of the maximum clock rate depending upon whether or not the duty cycle llmitation signal ls "true". There~ore, depending upon whether the "controller"
or "pump" mode has been selected, the CLK signal wlll start out, after a DRZ pulse, at l/lOth o~ the maxlmum 30 clock rate and~ when the duty cycle control signal on llne 52 is "true", the CLK slgnal wlll lncrease lts fre-quency to the full clock rate for either the last 60 percent (controller mode) or the la~t 25 percent (pump -3o-lOSt'3~69 mode) of the perlod prior to the next DRZ pulse. A~ will subsequently be apparent, ~ince the CLK signal count~ up the memory 3ubsystem, the portion of` a counting cycle ~hlch follows after a "true " duty cycle limitatlon signal on llne 52 1~ counted up at an accelerated rate.
The output of the divlder 59 ls al~o ~ed over llne 66 to another divlder 67 whlch divides the pul~e rre- :
quency by two to provide an output rrequency over llne 68 whlch l~ the pulse drive source u~ed to run the ~tepping 10 motor o~ a pump. In thls regard, the pul~e traln over l~ne ~8 i8 passed through an AND gate 69 over l~ne 70 to the stepplng motor driver 71 only when an enabling input ~ver llne 72 ~rom the output pulse control ~ub~ystem 1~
al~o dlrected to the gate 69. The particular dlvlders 59 and 67 convenlently provlde a drlver pulse source ~or the ~tepplng motor driver 71 at a selected stepping ~requency o~ 360 hertz. This stepping motor ~requency is computed by divldlng the clock frequency o~ 71.68 kilohertz by lO
and then by 20 to obtain a pulse rrequency of approxlmate-20 ly 360 hertz. Thls arrangement avold~ the necesslty ofprovldlng a Qeparate drlver pulse ~ource ~or the st~pping motor drlver.
The output control pulse provlded on llne 72 as lnput to the gate 69 is also dlrected over llne 73 to a plncher driver 74 when the sy~tem t~ being used in the "¢ontroller" mode of operatlon. In the case oP the con-; trollerJ the output control pulse ls actually the ener-gizlng pulse ltself for the output control devlce, wherea~
in the case o~ a stepplng motor pump, the output pulse 30 slmply controls the duration or gating o~ a bur3t o~
pulse~ ~rom the ~tepplng motor drlver pul~e ~ource.
Re~errlng now more partlcularly to FIGURE 4b, the d~gltal memory ~ubsystem lncludes a pair of counter~, the 1058~6~
scanning control register 83 and the pulse width regi~ter 85. A decoder 84 is associated with the scanning control reglster 83~ while a decoder 86 ls associated with the pulse width register 85. The scanning control regl~ter 83 i~ controlled by an input AND gate 87 and the pulse width reg~ater 85 ls controlled by an input AND gate 88 The gates 87, 88 gate the counting signal CLK lnto their re-spectlve registers at the appropriate times. As wlll be recalled rrom the previous descriptlon o~ the duty cycle subsystem, the CLK signal may be elther the full rate clock 3 ignal o~ 71.68 kilohertz or lt can be only l/lOth of that frequency, i.e., 7.168 kllohertz. The higher rate clock slgnal is ln e~ect whenever the duty cycle llmitation ls imposed.
Each of the reglster~ 83 and 85 has a count capac-lty of 21 or 1024. Paslcally, what occurs in the digital memory and control subsystems is that the scanning control reglster 83 and the pulse wldth reglster 85 undergo a counting cycle which is initiated each time a DRZ pul~e ls generated at the output o~ the decoder 45 on llne 46, and each countlng cycle mu~t be completed be~ore the next DRZ
pulse i~ produced.
The control register 83 determlnes the duration Or each counting cycle ~or itselr and the pulse width regi~ter 85, by inltiating the countlng cycle from its "zero" state upon recelpt of a DRZ pul~e, and terminatlng the counting cycle when lt counts to 1024 (the return to lts "zero" state). The control register 83 then remains ln it~ "zero" state untll the next DRZ pulse is produced at the output of the decoder 45.
Normally, the pul~e width register 85 is caused to lag the control register 83 by two counts durlng each counting cycle, thereby increa~ing the pulse wldth of the output pulses controlled by the reglster 85, as ~asured by the dlf~erence between the count ln the reglster 85 and its "1024" ("zero") overflow state.
Each time a drop ls detectedJ the pul~e width register 85 ls lncremented by 21 counts relative to the oontrol register 83 to narrow the effectlve output pulse width as measured by the count in the register 85. This establishes the desired _~ or 10-1/2 ratlo desired for the output pulse ~requency to the drop flow rate frequency. In e~sence, the pulse width is servoed in a closed digital loop to preserve the deslred 10-1/2 ratlo whlch is ~orced on the æystem by the DRZ pulse rate produced by the pulse generatlon and rate selection subsystem.
The decrementing of the register 85 relatlve to the control register 83 ls accompllshed in each counting cycle by holdlng off CLK pulses from the register 85 ~or the first 2 counts received by the control register 83 during each counting cycle. The incrementing of the pulse wldth reglster 85 relative to the control reglster 83, each time a drop is detected, is accomplished by holding of~
CLK pulses ~rom the control register 83 when the pulse width register 85 reaches lks "zero" state a~ter drop deteotion, and resumlng countlng o~ the control reglster 83 only a~ker the pulse width reglster has reached a count of "21". Hence, pulse wldth is e~fectively increased and decreased by altering the relatlve counting states or phase existing between the scanning control reglster 83 and the pulse wldth reg~ster 85 in the digital memory subsystem.
As prevlously indicated, during the start-up phase o~ operation, defined a~ the time to receive the ~irst two drops a~ter inltlally turnlng on the system or comlng out of an alarm state, the control xelatlonshlp between the control regl~ter 83 and the pulse wldth register 85 -` ~05846~3 ls altered so that pulse width ls increased by 9 count~
during each countlng cycle, rather than by only two counts to more rapldly bring the system up to its normal pulse width operating region.
The slze~ l.e., count capaclty, of the reglsters 83 and 85, and the number of counts by whlch pulæe width is 1ncreaqed and decreased, 13 determined ln accordance w~th the deslred resolution of the overall system and the loop galn desired. It has been determlned empirically, for the type of output control devlces utilized and the degree o~
stabllity deslred that, ~or a system capable of generatlng (~n the "ump" mode) a drop rate o~ 99 drops per minute, a ~ull range count capaclty of 50 drops for the registers, with a loop gain of approximately 2 percent 18 deslrable.
For a full range of 50 drops, at an increment o~
21 counts for each drop detected, a register count capaclty of 1024 appear~ to be optimum. This is also deslrable since the maximum lncrement of 21 counts per drop detected i8 approximately 2 percent of the count capacity, which 20 sati8~1es the loop gain requirements. Too high a loop gain, i.e., the percent of change generated ln the system ~or each drop detected, would cau~e the system to react too rapldly wlth possible overshoot and osclllation. A
lower loop gain approaches proportlonal servo control more closely and is much more reliable than the large on-o~f type ~wings in the system which tend to occur with ex-cesslvely high loop gain The count capaclty o~ 1024 for the reglster~ 83 and 85 is also compatlble with the maximum pulse wldth 30 requlrements for the system. In this regard, the output control mechanlsm utlllzed may require a maxlmum pulse wldth of approxlmately 140 mllllseconds and~ therefore, the reglsters 83 and 85 must be capable of a complete counting ~058469 cycle from "zero" to "1024" o~ at least 140 mllllseconds at the countlng rate o~ the CLK ~ignal. In this regardJ
using the normal (no duty cycle llmitaticn imposed) CLK
frequency of 7.168 kilohertz, the maximum pulse wldth PM
capable of generatlon wlth the count capaclty of 1024 ls:

p ~ 1024 3 M 7~1~8 x 10 = 0.1428 ~econds = 142.8 milllseconds Such a maximum pulse width ls normally required only at very low drop flow rates.
In addition, lt wlll be noted that, at the high-est sele¢table drop rate o~ 99 drops per minute typically lntended ~or the system of the present inventlon, the time between DRZ pulses i~ conslderably shorter than the maximum counting cycle period of 143 milliseconds. In this connec-tion, at a selected drop rate of 99 drops per mlnute, the period Pp between DRZ pulses ls:

pp ~ 60 seconds g9 drops/min. x 10.5 = .058 seconds -~ 58 milllseconds However, it can be shown that, at such high drop rates, the duty cycle limltation subsystem will (at 40 percent o~ the period between DRZ pulses ~or the controller mode and at 75 percent o~ the perlod between DRZ pulses ~or the pump mode) swltch the CLK slgnal from 7.168 kilohertz to the maxlmum clock rate of 71.68 kllohertz. This enables the counting cycle to be completed at a very fast rate, termin-ting the output pulse prematurely and thereby limiting it to the de~ignated duty cycle. Inevitably, this also shor-tens the counting cycle su~ficlently to assure completion 3~ of the countlng cycle prlor to appearance o~ the next ~RZ
pulse.
The aforementloned operation o~ the dlgital memory subsystem and the duty cycle llmitatlon subsystem is ~ ~ 58~69illustrated in FIGURES 5a through 5h of the drawings.
FIGURE 5a represents the regular occurrence of DRZ pulses whlch initiate each countlng cycle of the memory ~ubsystem.
FIGURE 5b repre~ents the varlatlon of CLK frequency durlng the perlod between succe~slve DRZ pulse~ and ~how~ the change in frequency ~rom 7.168 kllohertz to a full clock rate ten tlmes greater, or 71.68 kilohertz, a~ter the duty cycle per~od of 40 percent ha~ been reached.
FIGURES 5c, 5d and 5e lllustrate the ~tate3 of - 10 the control register 83 and pulse wldth regl3ter 85 and the nature o~ the output pul~e cn llne 72, where normal opera-tion i8 Such that the duty cycle has no e~ect upon the output pulse width as where narrow output pulæes are called ~or. In contrast, FIGURES 5f, 5g and 5h lllustrate the varlous states of the control reglster 83 and pul~e width reglster 85 and the nature o~ the output pulses on llne 72 where the duty cycle does impo~e a llmitatlon upon output pulse width.
Referring to FIG~RES 5c and 5d, the control regis-ter 83 ~tarts the countlng cycle from ~ts "zer" state, with the pulse width register 85 at an lnltial starting state o~
"924" which is a relatively narrow pulse width. The pulse wldth reglster 85 counts up to its l'zero" state prlor to the duty cycle llmltatlon being imposed and then continues to be counted up until lt reaches lts flnal state o~ "922"
(2 counts les~ than lts origlnal starting state) whlch occurs at the same polnt that the control register 83 passes through lt~ "zero"state. It will also ~e noted that the memory countlng cycle~ are completed considerably 3o more rapidly due to the hlgher frequency of the CLK ~ignal arter imposltlon o~ the duty cycle limltatlon than would have been requlred lf the duty cycle llmltation had not been lmposed, as lndicated by the ~ictitious countlng 105846g tates denoted ln parentheses ln FIGURES 5c and 5d.
The output pulse width on line 72, as lllu~trated ln FIG~RE 5e, ls determined by the pulse wldth reglster 85 in counting ~rom the "924" state to the "zero" ~tate, and de~ines a relatlvely narrow pul~e wldth well wlthin the duty cycle limltatlon.
Referring now to FIG~mES 5f, 5g and 5h, the con-trol register 83 starts out again ln lts "zero" state, the ~econd "zero" posltlon representing the speeded up com-pletlon of the counting cycle, with the thl~d "zero"position indlcatlng the startlng polnt for the next count-ing cycle a~ triggersd by the next DRZ pulse. The "zero"
positlon shown ln parentheses corresponds to the same posi-tlon in FIGURE 5c which indlcates how long it would have taken to complete the countlng cycle if there had been no swltching to a higher CLK ~requency because of the duty cycle limltation.
FIGURE 5g shows the pulse width reglster 85 start-qng out with a relatively low count o~ 124 whlch would norm-20 ally pioduce, in the absence of the duty cycle llmitation,a very wide output pulse on line 72. The ~irst "122"
~tate shown ~or the pulse register 85 represents lt~ state at the end o~ the counting cycle completed on an acceler-ated baQl~. The pulse regi~ter 85 remains ln the "122"
~tate untll the next DRZ pulse. The states indlcated ln parentheses indlcate where the pulse reglster would have been had there been su~lclent tlme for the register to count up wltho~t a duty cycle limitatlon. In thl~ regard the ~igures shown ln parentheses on FIGURES 5c, 5d, 5~ and 5g are sltuat~ons whlch assume that the ~RZ pu~e frequency was sufficiently low, substantlally lower than that lllus-trated ln FIGURE 5a, that the counting cycle could be com-pleted prlor to any duty cycle llmltation belng impo~ed, ~0584~9 i.e , there was adequate tlme left for the counting cycle to be completed at the normal CLX frequency o~ l/lOth o~
the maximum clock rate.
FIG~RE 5h illustrates that the output pulse on llne 72 i9 terminated by imposing the duty cycle llmita-tion, even though the electronics of the memory subsystem contlnue to count up both the control register 83 and the pulse width register 85. In thls regard, note that the output pulse is terminated by the duty cycle limltation rather than the "zero" state of the pulse wldth reglster 85. The dotted curve in FIG~RE 5h illustrates what the pulse width of the outputpulse on line 72 would have been i~ no duty cycle llmitation had been lmposed.
With the a~oredescribed background in mind, the followlng more detailed description of the dlgital logic employed in the overall system will be more readlly under-stood.
~ hen the scannlng control reglster 83 reaches a count Or "1024" during a counting cycle~ i.e., lts "æero"
state, the zero output llne ~rom the decoder 84 provides a "true" output on line 90 which is lnverted by an inverter 91 to di~able an AND gate 92. ~enc~, the output o~ the AND gate 92 on line 93 ls "~alse" whloh produces a "~alse"
output ~rom the OR gate 94 over line 95 to dlsable the lnput AND gate 87 to the control reglster 83~ This pre-vents the CLK slgnal ~rom countlng up the control register 83 any ~urther and ef~ectively terminates the countlng cycle at the "zero" state of the control reglster.
The other input to the OR gate 94, over line 96, i8 the DRZ slgnal whlch passes through the gate 94 and enables AMD gate 87 to again pass the CLK slgnals to the control reglster 83~ thereby initiating a new countlng cycle. Hence, the DRZ signal overrldes the lnhibltlng - 105~3469 e~fect of the "zero" state o~ the control register 83 at the beginning o~ each new countlng cycle.
After the first counting pulse ~DRZ and CLK) i8 received by the control reglster 83, the "zero" output llne 90 from the decoder 84 goes "false" which, ln tu m, makes the output o~ the inverter 9l go "true" and ther~by enables gate 92. The other lnput to the AND gate 92, over line 97, i~ al90 normally "true", 50 that the output line o~ gate 92, over llne 93, passes through OR gate 94 to maintaln the 10 AND gate 87 enabled for ~urther passage of the CLK pulses to the control register 83 even though the DRZ pulse i8 no longer avallable. Hence, the DRZ pulse merely lnitiates the countlng cycle which then contlnues until completion.
The lnput AND gate 88 to the pulse width reglster 85 is likewlse disabled by the "zero" state of the control reglster 83 since it receives the same inverted output as the gate 92. Thus, the pulse wldth register 85 does not yet begin to count when the DRZ pulse causes the control register 83 to count from the "zero" state to the "l"
20 state.
Another lnput to the AND gate 88 o~ the pulse width register, over line 99, is the ~ output o~ a flip-~lop 98. Hence, the flip-~lop 98 must be "~alse" (~ would then be "true") ~or the AND gate 88 to be enabled after the ¢ounting cycle has been initiated. In this regard, the J
input of the flip-~lop 98 ls set by the same DRZ pulse that enables the control register 83 to be counted ~rom zero tQ "l". Therefore, on the very next CLK pulse, which ¢ounts the control register 83 from "zero" to "l", the 30 flip-~lop 98 is set "true" which, o~ course, makes the ~
output over line 99 to gate 88 "~alse". However, the input gate 88 to the pulse wldth register 85 remains dlsabled, even though the input to the gate 88 over line lOO ~rom the inverter 91 is now true" Hence, the control regis-ter 83 has been counted to its "2" state, wlth no counts having yet been passed to the pulse width register 85 during the counting cycle.
From the foregoing analysis, it wlll be apparent that the pulse wldth register 85 wlll not count untll the ~llp-flop 98 is reset so that lts ~ output 1R "true".
Thls requires th~t the K lnput of the ~lip-flop g8 be set.
The K input of fllp-flop 98 is under the control o~ three 10 gates, an OR gate 102 and a pair of AND gates 105, 106 whose outputs are directed over lines 107, 108, respec-tivelyJ as inputs to the OR gate 102.
The AMD gate 106 recelves as lnput, over line 109, the "1" state Or the control reglster 83 decoded out by the decoder 84~ and receives a~ a second input, over llne 110, the ~ output Or a flip-flop 114 whlch i9 the start-up control flip-rlop lndicatlng whether or not the system is ln the start-up phase o~ operatlon. The other AND gate 105 receives as one input~ over the line 111, 20 the "8" state o~ the control reglster 83 ~rom the decoder 84, and recelves as a second input, over llne 112, the Q
output rrom the start-up ~llp-~lop 114.
When the system ls in the start-up phase o~ oper-ation, the fllp-flop 114 wlll be "true" (lts Q output wlll be "true") whereas, when the system ls out of the start-up phase, as wlll typically be the case for the bulk Or normal operation, the fllp-Plop 114 wlll be ~al~e (it~
output wlll be 'true").
Assuming for purposes of the present analysls that the system 18 out of the start-up phase, then the Q
output Or the start-up rllp-flop 114 will be "true".
Therefore, when the control reglster 83 has been counted to lts "1" state, the AND gate 106 will be enabled, and ~(~513469 lts "true" output will be passed by the GR gate 102 to setthe K lnput o~ the flip-flop 98. On the very next CLK
pulse, the control reglster 83 will be counted from its "1"
state to lts "2" state, the pulse width reglster 85 will remain unchanged~ and the flip-flop 98 wlll be re~et ~o that lts ~ output wlll be "truel' prlor to recelpt o~ the next CLK pulse.
At this point, both of the lnputs over llnes g9 and 100 to the pulse wldth reglster input gate 88 are true", 80 that the very next CLK pulse is pa~sed both to the control register 83 and the pulse wldth register 85.
Hence, the pulse wldth regi~ter 85 recelves lts ~irst count a~ the control register 83 1~ counted to lts "3"
state, thereby resultlng in the pulse width reglster havlng been decremented by a count of two relatlve to the count ln the control regi3ter. The gates 87 and 88 contlnue to be enabled ~or the passage of additional CLK countlng pulses ~-~or the balance of the countlng ¢ycle, ln the absence o~
drop detectlon, untll the control regl~ter 83 agaln count3 20 to lts "zero" state, at whlch tlme both o~ the gates 87 and 88 are dlsabled by the "zero" state output ~rom the decoder 84 which is inverted by the inverter 91 ln the manner prevlously described. Hence, durlng each countlng cycle, the pulse wldth re~lster ls decremented by two counts to produce an lncrease in pulse width for the output pulses generated by the sy~tem.
As previously lndlcated, when a drop occurs, lt 1~ desired to lncrement the pulse w~dth register by 21 counts relative to the control reglster 83 ln order to narrow the output pulse wldth ~rom the system. The pulse wldth then lncrea~es in steps o~ two counts each, as previously described in connectlon wlth FIGURE 3 o~ the drawings.
The addltion o~ 21 pulses to the pulse width 1C)58469 reglster 85 during a counting cycle will, o.~ course, alsoinclude a decrement of two pulses during that same counting cycle, in the manner previously set forth, thus resulting in a net lncrease during the countlng cycle followlng drop detection o~ 19 pulses incremented lnto the pulse wldth reglster 85 relatlve to the control regiqter 83.
When a drop occurs, it is detected by a drop detector 115 of the drop detection subsystem, to produce a pulse over line 122 to the "S" or "set" lnput of a drop 10 detection flip-flop 118. The drop detectlon pulse lmmedl-ately sets the flip-flop 118 non-synchronously (lndepen-dent o~ the recelpt o~ a CLK pulse) ln conventlonal set-reset ~lip-~lop manner. Hence, upon drop detectlon, the fllp-flop 118 ls lmmedlately forced lnto lts "true" state whlch makes its Q output on llne 123 go "true" as one lnput to an AND gate 120. The other input to the AND gate 120, over llne 124, i8 the high order flip-flop of the pulse width register 85 lndlcated as the 512-1023 output llne from the decoder 86 o~ the pulse width register.
Assuming for the moment that the pulse width reglster 85 is in its high count state, whlch provides a "true" output over line 124, the output o~ the AND gate 120 wlll be "true" and will set the J input Or a fllp-flop 119. On the ~ery next CLK pulse~ the ~llp-flop 119 will be "set" so that lts Q output will go "true". The "true"
state o~ the flip-flop 119 is fed over line 125 to the K
lnput of the drop detection ~lip-flop 118 so that, on the next CLK pulse, the drop detectlon ~lip-flop ls "reset"
and.the gate 120 ls thus disabled.
Hence, the flip-flop 119 is always set "true"
a~ter the fllp-flop 118 has been set "true" and the pulse wldth reglster 85 has count~d up to the state where lts high order ~lip-rlop is "true". When the Q output of the ~058469 rllp-flop 119 1~ true", its ~ output over llne 127 is false which dlsables one of the lnputs to an OR gate 121. The otler lnput to the OR gate 121 is the hlgh order state of the pulse width reglster 85, over llne 125, from the decoder 86. When the latter line i~ "true", the output of the OR gate 121 is "true " and its input over llne 97 to the AND ~;ate 92, prevlously discussed, contln-ues to enable gate 92 and permit the control register 83 to bP counted at times other than when the control regisi-10 ter is ln its "zero" state.
On the other handJ when the flip-flop 119 is "true" and the pulse width reglster 83 ls not ln lts high order countlng state, e.g.~ when the pulse width register has ~ust gone from its "1023" state to il;s "zero" state, the output on line 124 will be "false and the ~ output on line 127 wlll also be "false ", result~n~; in the gate 92 being disabled so that further counting of the control register 83 i~ arrested. Henc, a~ter a drop has been detected, the control register 83 is gated o~f when the 20 pulse width reglster 85 counts to "zero".
Once the control register 83 is thus gated off, further counting of the control reglster will not re~ume again until either the pulse width register 85 counts to lts hlgh order range 512-1023 or the flip-flop 119 ls set "false" so that its ~ output over line 127 i8 "true".
It will be ob~erved that the K input of the ~lip-flop 119 is set by the "20" output from the pulse width register d ecoder 86 over line 129. ~ence, when the pulse width register 85 has counted to "20", the K input of the flip-30 flop 119 is "seti' andJ on the next CLK pulse, the pulsewidth register counts to its "21'; state whlle the flip-flop 119 is re~et" to make its ~ output "true" over line 127. Therefore, on the next CLK pul~e which counts the pulse width register 85 to its "22" state, the control reglster 83, again enabled by a "true" output from the OR
gate 121, also receives the CLK pulse and i3 counted.
Thls results ln a suppresslon o~ 21 counts in the control register 83 relatlve tc the pulse wldth reglster 85, whlch ls equlvalent to lncrementing the pulse width register relative to the control reglster by 21 counts.
At this polnt, both registers 83 and 85 contlnue to run until the control register 83 agaln goes to "zero", at IO whlch time both registers stop. ~pon recelpt o~ the next DRZ pulse, the control register 83 will again start count-lng, ~ollowed by the pulse width register 85 two counts - later ln the manner previously described.
Havlng thus descrlbed the manner in which the scannl~g control register 83 and the pulse width regls-ter 85 are incremented and decremented relatlve to each other, and the ef~ects o~ counting cycle inltiatlon by the DRZ pulse and o~ drop detectlon, several typical situa-tions will next be illustrated. In this regard, illus-trative cases will be considered where a drop has beendetected between countlng cycles, i.e., after both regls-ters 83 and 85 have come to rest and are awaiting a DRZ
pulse to initlate the next countlng cycle. This category o~ lnvestigatlon will be extended to those situations lnvolving a variety of di~rerent startlng states for the pulse wldth regi~ter 85. In addltion, cases wlll be considered for various relative states o~ the control reglster 83 and pulse width reglster 85, where a drop ls detected while a counting cycle is actually in process.
FIG~RES 6a-6c cover those situations where a drop is detected between counting cycles, whereas FIGURES 6d-6g cover those situatlons where a drop ls detected durlng a counting cycle.

~058469 FIGU~E 6a ls a table of the relatlve state~ of the control register 83 and the pulse register 85, and also show~ the ~tates o~ the ~lip-flops 118 and 119, where the registers came to rest at "zero" ln the control regl~ter and a count o~ "18" ln the pulse wldth register 85 in the precedlng cycle. A drop was then detected which set the fllp-flop 118 "true" immediately. Ultimately, a DRZ pulse occurred which initlated th~ counting cycle. The states shown in the first line of the table are, therefore, the starting states at the beginning of the next countin~ cycle after the drop occurred.
The pulse width reglster 85 is lnhibited by two pulses as the control register 83 is counted, so that the register 85 is counted from "18" to "19" only as the con-trol register is counted from "2" to "3'. The flip-flop 119 which is normally "false" remains "false", because of the "false" output on line 124 from the high order 512-1023 output of the pulse width register decoder 86 which disables the gate 120 input to the flip-flop 119.
Both flip-flops 118 and 119 remain unchanged as the regi~ters 83 and 85 are counted up, untll the pulse wldth register 83 is counted to "512". At the latter count of.the pulse ~idth regi~ter 85, line 124 goes "true ~J enabling the gate 120 and setting the J lnput of the fllp-flop 119, so that on the very next CLK pulse, which counts the pulse width register 85 to "513 ", the fllp-flop 119 is set "true". This disables the Q output of the flip-flop 119 over line 127, which is replaced by the "true ! output on line 124 from the decoder 86, so that the control register 83 can contlnue counting. On the next CLK pul e, which counts the pulse width register 85 to ltg "514" state, the drop detection flip-flop 118 is "reset", its K lnput having been previously "set" by the ~)58469 Q output on li~.e 125 from the fllp-~lop 119.
Both reglsters 83 and 85 are then counted con-tinuously untll the pulse width register is lnlts "zero"
state, at which time the 512-1023 output llne 124 from the decoder 86 goe~ "false". Since the Q output ~rom the fllp-~lop 119 over line 127 is also "false" (the fllp-~lop 119 having prevlously been set "true"), both lnputs to the OR
gate 121 are "false" and the control register 83 ls thus gated o~f at lts count of "1008".
When the pulse wldth register 85 19 counted to lts "20" state, the K input of the flip-~lop 119 1~ "set" and, when the reglster 85 is counted to "21", the CLK pulse also resets the rlip-flop 119 so that the ~ output on line 127 is "trùe". This again enables the control reglster 83, so that the CLK pulse which increments the pulse width reglster 85 to its "22" state is also passed to the control register 83 to count the latter register to "1009".
Both registers continue to count, with both ~lip-flops 118 and 119 "false", untll the control register 83 counts to "zero", at whlch tlme the counting cycle termlnates with a count of "37" ln the pulse wldth register 85. Since the pulse width reglster 85 ~tarted out with a count o~ "18", this represents a relative increment of 19 counts, which includes both the 21 count increment due to drop detection and the normal two count decrement experienced during each counting cycle.
FIG~RE 6b illustrates the sltuatlon where the state of the pulse wldth register 85 was "512" upon com-pletion o~ the prevlous counting cycle and at the beglnnlng o~ the counting cycle illustrated. ~nder those clrcum-stances, ~ince the ~lip-flop 118 was set "true" lmmedi-ately upon detection o~ the drop, and the 512-1023 output line ~rom the decoder 86 provide~ a "true" output over ~L~58469 ~
line 124 to the AND gate 120, the very next CLK pulse sets the fllp-flop 119 "true " and the next CLK pulse after that resets the fllp-flop 118, all prior to the DRZ pulse whlch lnltiates the next countlng cycle. Hence, the countlng cycle starts out with the control reglster 83 ln the "zero"
state, the pulse width reglster 85 ln the "512" state, the fllp-~lop 119 "true" and the flip-flop 118 "false".
When the pulse width reglster 85 is ultimately counted to "zero", the output of the OR gate 121 again 10 goes "false" to gate off the control register 83 tas ln the case illustrated in FIGVRE 6a) until the pulse width register counts to "20". In going from count "20" to count "21" ln the pulse width register 85, the flip-~lop 119 is "reset", making lts 1~ output go "true" on llne 127, thus enabl ing the control register 83. Both counters are con-tinuously counted for the remainder of the countlng cycle as pul~e width reglster 85 is counted by the next CLK pulse to lts "22" state and the control register is counted to state "515". Counting of both registers proceeds until the 20 control register 83 is counted to "zero", ac which time the count in the pulse width register 85 is "531", again 19 counts more than the starting count of 512.
FIG~RE 6c illustrates the case where the state of the pulse width register at the termination o~ the last counting cycle and at the beginnlng of the present count-ing cycle is "1023". For the same reasons as in the case lllustrated ln FIG~RE 6bJ rlip-~lop 119 has been set "true"
and flip-~lop 118 has been reset to its "false " state . The pulse width register 85 ls agaln inhibited ~o~ two counts 30 and thenJ as the control reglster 83 count~ to its "3"
~tate, the pulse width register overflows to "zero" whlch gates off the control register for 21 counts.
As the pulse width r~gist~r 85 is counted to "22", the control regis ter 83, ha~ing been again enabled in the manner previou~ly descrlbed f~or these condltions, is counted to its "4" state. Counting again continues untll the con-trol register 83 is counted to "zero ", thus termlnatlng the counting cycle.
It wlll be noted in FIG~RE 6c that the pulse width register 85 passes through its "zero" state a 3econd time during the counting cycle, but without gatlng of~ the con-trol reglster 83, since the flip-flop 119 ls "false" during 10 this second overflow of the pulse wldth register and, therefore, a Q "true " output over llne 127 to the OR gate 121 continues to enable the control register 83. At the concluslon of the counting cycle, the count in the pulse width register 85 i8 "18" which, again, i8 19 counts more than its star'cing state of "1023 ".
FIGI~RE 6d illustrates the sltuatlon where a drop occurs during a counting cycle when the control register 83 i8 ln its "1" state and the pulse width register 85 ls at count "18". The ~lip-flop 118 is set to its "true" state 20 immediately upon drop detection, but since the 512-1023 output line from the decoder 86 o~ the pulse width register ls "~alse", the Mip-~lop 119 must remain "false" until the pulse width reglster is counted up to 512. It will be apparent, upon comparison, that the sit~ation o~ FIGIJRE 6d ~essentially duplicates that previously described in connec-tion with FIG~RE 6a.
FIGURE 6e illustrates the case where a drop is detected when the control register is ln the "1" state and the pulse width register 85 is already in its hlgh order 30 decade of operation at a count of "512". ~Jnder these circumstances, flip-flop 118 is set "true" immediately on detectlon of the drop and the latter state over line 123 is immediately passed by the AND gate 120 to set the J

~058469 lnput of the ~lip-flop 119. On the next CLK pulse whlch counts the control reglster 83 ~rom "1" t~ "2", the flip-flop 119 is set "true". On the next CLK pulse after that, the drop detection flip-flop 118 is reset. Again, the control register 83 has been counted up whlle the pulse wldth register 85 has been inhibited ~or two counts. At thls point, the counting cycle proceeds exactly as for the case illustrated and described in connection with FIG~RE 6b.
FIG~RE 6f illustrates the case where a drop is detected at that point ln the counting cycle when the con-trol register 83 is a~ a much hlgher count of "500" and the pulse width register is at a count of "15". Agaln, the ~lip-flop 38 is immediately set "true" while the flip-flop 119 remains "false' until the pulse width register counts up to 512, at which time the flip-~lop 39 is set "true"
aa the pulse width register is counted to "513". On the very next CLK pulse, the "true output of the ~lip-flop 39 resets the flip-flop 118 to its "false" state.
At this point, both registers are.counted up until 20 the control register reaches "zero", at which time both registers stop and must wait until the next DRZ pulse to start another counting cycle. It will be apparent, ~rom the counting states depicted in FIG~RE 6f, that, ~or the condition~ stated, the lncrementing o~ the pulse width register in response to drop detection is not accomplished ln the same counting cycle in which the drop is actually detected, but i3 delayed until the next counting cycle.
In this regard, the next DRZ pulse lnitiates the next count-ing cycle, which then inhibits the pulse width register 85 b~r two counts and increments the pulse width register by 21 count~ ln the same manner as previously described in connection with the case illustrated in FIG~RE 6b. Note -~
in FIG~RE 6~ that the pulse width ~egister 85 comes to rest ~58469 at a count of "558" which is 19 count~ more ~an the "539"
state at the beginning of the countlng cycle.
FIG~RE 6g lllustrates the case where a drop is received with a relatively hlgh count of "600" ln the con-trol reglster 83 and wlth a relatlvely low count of "15"
in the pulse width regi~ter 85. The primary distinction between FIG~RE 6g and FIGURE 6f prevlously descrlbed, i~
that the control register 83 overflows to lts "zero" state prior to the pulse width reglster 85 arrivlng at its high 10 order count of 512.
In FIG~RE 6g, the counting cycle ln whlch the drop was actually detected ls again completed without any incrementing of the pulse wldth register 85. As in the case of FIG~RE 6~, the 21 count lncrement is deferred until the next counting cycle.
The next counting cycle begins with a DRZ pul~e, the control register 83 in the "zero state and the pulse width regi~ter at "439" The flip-flop 118 has been set "true" by the drop detection, but the ~llp-flop 119 re-20 mains "false" until the pulse width register 83 counts upto "512". The pul~e width register 83 ls agaln inhibited by two counts as the control register 83 i9 counted up and, when the pulse width register over~lows to its "zero"
state, the control register is inhibited for 21 counts, all e~sentlally as indicated for the case previously de-scribed in connection with FIG~RE 6a. In this regard, note that the final count ln the pulse wldth register 85 is "458" whereas its lnitlal count state at the beginning o~
the last complete counting cycle was "439", representing 30 the deslred net increment of 19 counts.
Normally, ln the "controller" mode, drops come at regular periodic lntervals. However, ln the l'pump" mode o~ operatlon, lt ls possible to recelve a burst o~ drops ln -5o-~058~69 vlew of the larger body o~ llquld typlcally ~rapped between the cam ~ollowers of the pump In the event a ~econd drop occurs before a previous drop has been completely accounted for~ it can be shown that the second drop is ignored by the system. ~or example, if the flip-flop 118 llas been set "true" and the flip-flop 119 is still "false", the second drop has absolutely no effect on the drop detection flip-flop 118 since the latter fllp-flop ls already "S~t". In the sltuation where the drop detection fllp-flop is "false"
10 and the flip-flop 119 is already "true", the drop detec-tion fllp-~lop 118 will immediately be "set" again by the ~econd drop but will also be "reset1' to it~ "false" state agaln on the next CLK pulse, because of the "true" state of the flip-fl~p 119 communicated to the K lnput of the drop detectlon fllp-~lop.
For certain types of electromechanlcal output ¢ontrol devices, particularly those capable of responding properly to very narrow pulse width input, the system of the present invention is capable of functloning normally 23 on an expanded low level operational basis, without going lnto alarm, by storing and processing the equivalent of negative pulse width in the pulse width register 85. In ~;
the embodiment of the invention illustrated, this type o~
operatlon is possible with the system operating in the "pump" mode.
The negative pulse wldth conditlon may occur with normal low level operatlon in whlch extremely narrow pulse wldths are generated, so that further incrementing of the pulse wldth register 85 upon detectlon of drops causes the 30 pulse wldth register to overflow and start counting up again. Over~low of the pulse wldth register countwlse ls equivalent to underflow of pulse width, l.e., negatlve pulse width, which is nanlfested by the sudden transltion ~rom a very narrow output pulse (a hlgh count in the pulse width register) to a very wlde output pulse (a very low count in the pulse width regl~er).
Assuming the system i~ operating to provlde normal fluld flow, i.e., there are no flow condition~ warranting generatlon of an alarm state, the negatlve pulse width condition in the pulse width register 85 will be only transltory and successlve decrementing by two Gounts per counting cycle will cau~e the pulse width regi~ter to 10 underflow and come out of the negative pulae width region, to thereby restore normal narrow outp~t pulse generation ma~lfested by a hlgh count state ln the pulse wldth regls-ter.
.During operation o~ the system with apparent negatlve pulse width, the alarms subsystem generate~ an output (without golng into an alarm state), in a manner to be aubsequently descrlbed, to gate of~ the system output pulses whlch would otherwise normally appear on line 72 (FIGVRE 4a) while allowing the memory ~ubsystem to continue 20 to ~un¢tion normally. This capabillty o~ operation ln the negatlve pulse width region o~ the pulse width reglster enables an expanded dynamlc range o~ operation wlthout the need for expanding the count ¢apaoity o~ the reglaters ln the dlgital memory.
FIGURES 7 and 8 of the drawlngs are next described to ~urther clarlry sy~tem operatlon under negative pulae width condltlons.
FIGURE 7a illustrates a typlcal output pulse on llne 70 to the stepping motor driver 71. FIGURE 7b shows 30 the corre~ponding drive pulses which are passed to energize the atepping motor o~ the puup and it wlll be ob~erved that the response of the motor to the output pulse of FIGURE 7a ia essentially very nearly ~nstantaneou~, with very little '. ' `' '''.' ' ~ ' :

~058469 apparent mechanlcal inertia.
FIG~RE 8a shows a rather narrow memory pulse, which 18 the solid curve ln this figure, while FIG~RE 8b shows a slngle motor drlve pulse generated wlthin the memory pulse perlod, again indicating essentlally no delay in re-sponse of the motor.
FIG. 8a also shows a dotted curve which lndicates a further reduction in pulse width by an incrementing o~ 21 counts and decrementing of two counts ln the pulse width memory 85 during the next counting cycle after a drop has o¢curred. Since the inltlal pulse width in FIG~RE 8a is as~umed to be extremely narrow, the net increment of 19 counts ln the next c,ounting cycle wlll yleld a negative pulse wldth whlch is shown in FIG~RE 8c as an extremely wlde mem-ory pulse due to overflow o~ the pulse wldth register 85.
FIG~RE 8d illustrates that there is no motor pulse output since, ln a manner whlch wlll be subsequently herein~
after descrlbed, the output pulse on line 70 is gated of~
whenever the pulse width reglster is operating in the nega-tive reglon.
FlG~RE 9a lllustrates an output pulse on llne 73~or the controller case. FIa~RE 9b lndioates the corre~-ponding controller mechanlsm response and lllustrates the typlcal ef~ects o~ mechanlcal lnertla encountered wlth such devlce~.
FIG~X~ lOa lllustrates a very narrow memory pulse produced whlle operatlng in the "controller" mode. FIG~RE
lOb lllustrates that, even though the system ls not operat-ing in the negative pulse wldth region, there is no mechan-ical output from the controller because of the mechanicallnertla whlch lntroduces a delay greater than the memory pulse wldth.
The next portlon of the descrlptlon is dlrected to the start-up phase of operatlon of the overall system. As prevlously indicated, the ma~or difference in the start-up mode of operation is that, instead of altering the pulse wldth in the pulse width reglster 83 by only two counts ln each countlng cycle, the pulse width register is decre-mented by nlne counts in each counting cycle untll the ~lrst two drops have been received. Then the system switches back to normal operatlon by contlnuing to decrement the pulse wldth register 83 two counts per countlng cycle. In addition, and only while a start-up phase is in process, the output pulse rate is temporarily set internally to a prescrlbed rate most sultable for inltlal ad~ustment.
When the system first starts out, either during "power on" lnitlalization, or during alarm, all of the rllp-flops and registers are forced into certain specified states. In this regard, both of the reg$sters 83 and 85 are reset to "zero" over llnes 133 and 135, respectlvely.
The ~lip-flops 118 and 119 are "reset" over line 136, fllp-flop 98 is "reset" over line 137, and the start-up fllp-20 flop 114 is set to lts "true" state on llne 138. In addi-tlon, a fllp-flop 140, which 1B part of the start-up sub-system, ls "reset" over line 141. The p~rpose o~ the rllp-flop 140 is to keep track o~ recelpt of the first drop in the start-up phase of operation.
Referring brlefly to FIGURE 4c, when the system is first turned on, a power-on initlallzing clrcuit 144 sets the lnput of an alarm fllp-flop 145 lmmediately so that the Q output of the fllp-flop 145 ls "true" on line 146 and all of the system flip-flops and reglsters can be 3 set and reset approprlately for start-up conditions. A
start~up swltch 147 ls then closed whlch "sets" the K input Or the fllp-flop 145 so that on the next CLK pulse over llne 148, the flip-flop 145 will go "false".

105846~
The fir~t DRZ pulse will start the control regis-ter 83 counting ln the normal ~ashion, witll the initlal counts being inhiblted from the pulse wldth register 85.
However, since the start-up flip-flop 114 has been ~et "true", gate 106 is disabled and gate 105 ls now enabled.
As a result, the "8" state of the control register 83, rather than the "1" st~te, ~rom the decoder 84 is utilized to set the K input o~ the flip-flop 98 so that, lnstead of being decremented b~J two counts relative to the control 10 register during each counting cycle, the pulse wldth regls-ter B5 is now decremented by nine counts during each count-ing cycle. This start-up phase can only be termlnated by resetting the start-up ~lip-~lop 114 and, as will subse-quently become apparent thls will only occur after two drops have been detected.
When a drop is detected, fllp-flop 118 is set "true" immediate~y and it wlll then set the flip-flop 119 "true"J in the ~anner prevlously described ~or nor~al oper-ation. The Q output of the flip-flop 119 ls directed not 20 only over llne 125 to "reset" the M ip-flop 118, but is also dlrected over line 151 as an input to each o~ a pair of AND gates 153 and 154. The other inputs to the AND
gate 153 are the "zero" state of the pulse wldth register from the decoder 86, over llne 155J and the Q output of the start-up fllp-flop 114, over line 156. HenceJ the gate 153 will only be enabled when the system is ln the start-up phase, a drop has been recelved~ and the pulse wldth reglster 85 has been counted to "zero". ~herefore, when the ~lrst drop is detected, and the pulse wldth reglster 30 goes through "zero", the output o~ the gate 153 sets the J
input of the flip-flop 140 so thatJ on the next CLK pulse the fllp-~lop 140 will be set "true".
The flip-flop 119 will be "re,set" as the pulse ~058469 width register ~5 counts past "20", to remove the "true"
output over line 151 ahd thereby disable the gate 153.
Nothing further happens in the start-up subsystem untll a second drop is detected and the fllp-~lop 119 i3 again set "true". At this time, the output of the AND gate 154 will go "true" on line 161 when the pulse width register 85 counts through "zero", since both of the lnputs to gate 154 over lines 151 and 158 will then be "true", and the Q out-put of the flip-flop 140, over llne 159, wlll also be "true" (from the counting cycle when the flrst drop was detected), thus providing the third enabling lnput to the AND gate 154. When the AND gate 154 ~ enabled, lts "true' output resets flip_flop 140 and the start-up flip-flop 114 on the next CLK pulse. This results ln a "true"
output from the flip-flop 114J thus disabling the gate 105 and enabling the gate 106, so that the system exits from the start-up phase and resumes normal operation in de-crementing the pulse width register 83 by two counts during each counting cycle.
During the start-up phase, the "true" state of the Q output from the start-up flip-~lop 114 ls directed, over line 157, to the rate multiplier 42 (FIG. 4a) to tempor-arily override the rate selector switches 42a, and inter-nally force the pulse generation subsystem to a predeter-mined pulse rate most suitable for initlal adJustment of pulse width. This arrangement insures pulse wldth ad~ust-ment at an initial pulse rate which is nelther too slow nor too fast, considering the loop gain of the overall ~ystem. When the start~up phase is termlnated, the Q out-30 put of the ~lip-flop 114 will go "false", and the rate selector switches 42a wlll resume normal rate determinatlon control over the rate multiplier 42a.
It wlll be apparent to those of ordinary skill ln 1058~69 the art that, durlng the start-up phase, the input over llne 157 obviou~ly gates "off" the normal rate selector switch lnputs and gates "in" the prescribed start-up phase rate settlng. For purposes o~ simplicity, the specific gate conflguration, which may assume a wide variety of conven-tional logic conflgurations, has been omitted.
The output pulse control subsystem will be next ~scribed The output pulses are generated over line 72 by the "true" output o~ an output pulse control ~llp-flop 162 10 wh~ch is normally "reset" when the system is flrst ini- - -tialized, over line 163.
The J input of the flip-~lop 162 is under the control of an AND gate 165 which, in turn, has three inputs.
One lnput to the gate 165, over line 166, is the DRZ slgnal.
The other two inputs to the AND gate 165, over lines 167 and 168, are lines which are normally "true" but potentially disabling, the inputs over lines 167 and 168 being from the alarms subsystem whlch will be subsequently described.
Hence, under normal conditions, each time a DRZ pulse ap-20 pears on line 166, the J input of the fllp-flop 162 will be "set" and, on the next CLK pulse, the fllp-~lop 162 will go "true". This initiates the output pulse ~rom the system over line 70 (ln the "pump" mode) or over line 73 (in the "oontroller" mode).
The output pulse to the output control device can ~nly be terminated by resetting the flip-flop 162. In thls regard, the K input o~ the ~lip-flop 162 is controlled by an OR gate 170 having two inputs, one input over llne 171 representlng the "zero" state of the pulse width reglster 85 from the decoder 86, the other input over line 172 being the duty cycle limitatlon slgnal at the output o~ the OR gate 51.
Hence, each output pulse over line 72 ls initiated by a DRZ pulse, and the pulse is te~minated whenever the ~058469 pulse width register 85 overflows to its "zero state", thus determining the pulse wldth of the output pulse. IfJ on the other hand,a pulse wldth is called for beyond the duty cycle llmitation, then, before the pulse width reglster 85 over-flows, the line 172 wlll go "true", setting the K input of the flip-flop 162. On the next CLK pulse, the fllp-flop 162 will be reset" to termlnate the output pulse on line 72 and provide an instantaneous limitation on the mechanical output from the overall system.
Whlle the output pulse lines 70 and 73 are shown as directly driving the partlcular electromechanical output control device utilized, it will be appreciated that, depending upon the characteristics of the particular mechan-ical output, it may be nece~sary to introduce appropriate delays prior to actual energizatlon by the output pulses.
For example, in the "pump" modeJ the pump motor ls normally shut off between output pulses. Therefore, rather than enabling the stepping motor driver 71 immediately by the - output control signal, a delay of a few clock pulses is lntroduced to allow the power signal to the motor to come up to full level before actually allowing stepping motor ~lses to be applied. Hence, a delay of a ~ew milliseconds, while not actually shown in the drawing of the overall system, may be conveniently introduced in any appropriate manner, as by a sultable one-shot, where needed.
The alarm~ subsystem is next descrlbed. An AND
gate 175 controls the high level alarm, that is, the alarm response to a requirement for too wide an output pulse. One input to the AND gate 175 ls the DRZ pulse on line 176 30 which also starts every counting cycle and every output pulse to the output control device. Hence,the AND gate 175 can only be enabled during the one clock period duration of the DRZ pulse, so that each time the DRZ pulse appears at the ~058469 input of the eate 175, the system i8 being tested ~or the ststuQ of the other lnput llnes to that gate. I~ all three other input llnes to the gate 175 are "true", then an ~tput from gate 175 is provlded which is passed by the OR
gate 180 to set the alarm flip-flop 145 which, on the next CLK pulse, goes "true" to energize the alarm display 1~1.
A second input to the gate 175, over line 177, comes from the ~ output of a fllp-~lop 182, so that flip-flop 182 must be in the "reset" condltion for the gate 10 lnput line 177 to be "true". A thlrd input to the gate 175, over line 178, is ~rom the 768-1023 output of the pulse width reglster decoder 86, which is "true" only when the pulse width register 85 ls ln the last 25 percent of lt~ upper countlng range (indlcatlng a very narrow pulse width). The fourth input to the gate 175, over line 179, iQ the ~ output of a flip-flop 183, so that fllp-flop 183 must also be false", as ln the case of the ~llp-flop 182, in order to enable the gate 175.
The only time that the M ip-flop 183 can be "~alse"
20 when a DRZ pulse occurs, is i~ flip-flop 183 has been "reset" on the previous counting cycle. I`,l this regard, the fllp-flop 183 gets either "set" or "reset" a~ter every DRZ
pulse, so that the flip-f`lop 183 ls tested at the start of every counting cycle. The J input o~ the flip-~lop 183 is controlled by an input AND gate 185, and the K input of the flip-~lop 183 ls controlled by an input AND gate 186. Each o~ theae gates receives the DRZ pulse as an lnput over line 187.
The second input to thP gate 185, over llne 190, 30 is the 512-1023 high order flip-flop output of the pulse width register 85 ~rom the decoder 86. This same output on line 190 ls lnverted and then directed as the second input to the gate 186. merefore, ~ the pulse wldth .

~058469 reglster 85 has come to rest in a high count state during the last counting cycle, then the gate 185 will be enabled on the next DRZ pulse to set the flip-flop 183 to its "true" state on the very next CLK pulse. If, on the other hand, the pulse width register 85 ends the preceding count-ing cycle wlth a count below "tl2", then the gate 186 will go "true" on the next DRZ pulse t~ "reset" the ~l~p-~lop 183.
Hence, if a very wide pulse output is produced on the precedlng counting cycle (represented by a low count in the pulse width register 85) the flip-flop 183 will be "reset" cn the next counting cycle and its ~ output will go "true". In contrast, a narrower pulse (pulse width register count of "512" or more)in the preced~ng counting cycle will set the flip-flop 183 so that lts Q output is "true". Thus, the flip-flop 183 e~sentially remembers whether the system had a wide pulse or a narrow pulse on the lmmediately precedlng counting cycle and is used throughout the alarms subsystem for this purpose.
Assumlng the output pulses are getting longer and longer wlth each counting cycle, the flip~flop 183 will llkewlse be reset on each counting cycle to malntaln its output "true" When a counting cycle i9 finally reached where the pulse width register 85 ~ust barely underflows, the output line 768-1023 from the decoder 86 will provide a "true" output, over line 178, to the AND gate 175. This represents a condition where a very wlde output pulse ln one counting cycle ls immediately followed by an extremely narrow output pul~e on the very next countlng cycle, in-3o dlcating that the pulse width register 85 has underflowed.
Since the flip-flop 183 had been "reset" every tlme a long output pulse occurred, it is still "reset"
from the previous counting cycle and, with the 768-1023 -~0-~058469 llne "true", the AMD gate 175 will be enabled i~ th~
output ~rom the ~lip-flop 182 is also "true". The latter flip-flop 182 ls "reset" when the system is turned on and ls, there~ore~ normally "false ! So that lts ~ output on line 177 will also normally be "true". It will be appar-ent, there~ore, that whenever a wide pulse is followed by an extremely narrow pulse, the A~D gate 175 will be enabled and the ~ystem wlll go into high level alarm.
As wlll subsequently become apparent, the flip-10 ~lop 182 ha~ as lts ~unction to remember (in the "pump"
mode of operation) that a very wide pulse width ha~ been produced a~ter a very narrow pulse width, and that it is not yet desired to go into low level alarm because of the capabillty o~ the pump ~or normal operation in the nega-tive pulse width region o~ the pulse width register 85.
An AND gate 195 sets the controller low level alarm. One input to the gate 195, over line 196, is the DRZ si~nal at the geginning of each counting cycle. A
second input, over line 197, is the Q output of the ~llp-~lop 183 (representing a relatively short output pul~e onthe preceding counting cycle). A third inputJ over line 198~ i8 the 0-255 state from the pul~e width register de-coder 86, indicating that the present pulse being called ror has a very long pulse period. A ~ourth input to the gate 195, over line 199, indicates khat the system has been set by the ~umper 53 (FIG. 4a) to operate in the "controller"
mode. ~he fi~th input to the gate 195, over line 201, i~
the ~ output of the start-up ~lip-flop 114 which indicates, when the line 201 is "true", that the system is out o~ the ~tart-up phase. Thls prevents the controller ~rom going lnto alarm during the ~tart-up phase, since the system normally start out with extremely narrow pulses (both regl~ters having been re~et to "zero" lnitlally).

,~
: . .

HenceJ the input lines 19~ and 201 to the AND
gate 195 will always be "tru3" ln normal operation (out-~lde Or the start-up phase). T;~erefore, whenever a very narrow pulse on the immediately preceding counting cycle is being ~ollowed by an extreme~y wide pulæe (a pulse width register count of 255 or less), the AND gate 195 wlll be enabled to pass the very next DRZ pulse and thereby trlg-ger the controller low level alarm through the OR gate 180, to "set" the alarm flip-flop 145.
The transltion from a narrow pulse to an extremely wide pulse indicates that the pulse width regl~ter has underflowed which means, in the "controller" mode, that the sy~tem 19 incapable o~ producing pulses su~ficiently narrow to arrest ~urther ~luid ~low, e.g., either the controller is incapable of clamping o~f the ~eeding tube or a lea~ exists, so lt i~ desirable to go lnto the alarm state.
The pump low level alarm is controlled by an AND
gate 204. The pump low level alarm will not be triggered merely by under~low o~ the pulse width register 83 (neg-ative pulse width), since this may still be normal opera-tion ln the "pump" mode. Rather, it i8 intended that the pump low level alarm will be triggered when the pulse widkh ¢alled ~or in the "pump" mode of operation has exceeded a negative pulse width requirement o~ 25 percent, i.e., the '!' virtual pulse width has gone ~rom ~omething more than 75 percent on the previous counting cycle to less than 75 percent of the maximum pulse width on the present counting cycle. The term "virtual pulse width" i5 utilized because, 30 as will become apparent, the actual output pulse to the output control device tthe stepp~ng motor drlver 71) ls actually gated off when the pulse width register 85 i8 ln the negative region.

. :

105846g The sequence of alarm condltlons for the pump low level alarm is a very narrow pulse, followed by a very wide pulse ~underflow of the pulse width register 85 into tne negative region) followed immediately by a reductlon in that very wide pulse width to a pulse width Ju~t below 75 percent of the max~mum pulse width. E~sentially, thi~ ls very much like the controller low level alarm except that the low level boundary i~ at m~nus 25 percent of the pulse width reglster rather than at the zero level of the pulse ~o width regi~ter, thus provlding enhanced dynamic range for the "pump" mode of operatlon.
The reason for going into pump low level alarm under the a~oredescribed conditlons is that a bur~t of drop from the pump may occur which temporarily may drive the pulse width register 85 into the negative region, all as part o~ the normal operation of the pump. However, ln suah normal operation, the pump will gradually return to a narrow pulse width in the posltive range o~ the pulse width reglster. IfJ on the other hand, the pulse width register 20 85 is continually incremented by more and more drops oall-lng for even larger negatlve pul~e width on a virtual basi~, this indicates that, even with no mechanical output from the pump (the motor i8 gated off when the pulse width register is in the negative region) additional drop flow i~
being produced, and an alarm state should be generated.
The ~lip-flop 182 gets "set" by the same conditions that would trig~er a low level alarm in the "controller"
mQde of operatlon. In thls regard, the J input o~ the fllp-~lop 182 is controlled by an AND gate 205 whlch re-30 ceives as one input, over line 206, the Q output o~ the~lip-flop 183 and, as a second input over llne 207, the 0-255 output from the pulse width register decoder 86. The third input to the AMD gate 205, over line 208, ls the ~RZ

signal.
Hence~ lr there was a very narrow pulse width on precedlng counting cycle, the Q output of the ~lip-~lop 183 will be "true'. If, in addition, a very wide pulse width is being called for on the next counting cycle, the 0-255 decoder output llne from the pulse width register 85 will also be "true" so that, on the next DRZ pulse, the gate 205 will be enabled, the J input of the fllp-flop 182 will be "set and, on the very next CLK pulse, the Q out-put from the flip-~lop 182 will go "true" on line 209 to the gate 204.
~he "~rue output o~ the gate 205 1S also dlrected, over line 210J through an lnverter 212 (FIG~RE 4a) to pro-duce a "false" output on line 168 and disable the lnput AND gate 165 whlch controls the J input of the output pulse control ~lip-~lop 162. This prevents any output pulses from being direcked to the output control device whenever the pulse width register is starting to operate ln the negative pulse width region.
The AND gate 214 controls the K input o~ the flip-~lop 182. One input to the gate 214 is the DRZ slgnal, while the second input to the gate, over line 215, is the 768-1023 output line from the pulse width register decoder 86. Hence, the output o~ the gate 214 will remaln "~alse"
as long as wide pulse widths continue to be generated.
It wiil be apparent, fron the foregoing, that the fllp-~lop 182 gets "set" whenever a narrow pulse width becomes a very wide pulse width (negative pulse width reglon), and the flip-~lop 182 only gets "reset" again in ~oing ~rom a very wide pulse width to a very narrow pulse wldth. As long as the system remains ln the very wlde pulse wldth region, the flip-flop 182 remalns set "true".
In switching back to narrow pulse width operatlon, the output of the fllp-flop 182 is still "false" when the very next DRZ pulse occurs and prevents the high level alarm (the lnput over line 177 to the AND gate 175) from being activated because of the prevlous operation in the wide pulse wldth region.
Another input to the pump low level alarm gate 204, over line 216, is the 256-511 output line from the decoder 86 of the pulse width reglster 85, which represents a pulse width from 1/2 to 3/4 of the maximum pulse width.
The AND gate 204 is only enabled when a short pulse width is followed by a very wlde pulse width whlch ulti-mately drops down to a pulse width of less than 75 percent of the maxlmum pulse width. Thls indicates that drop flow keeps coming, thereby contlnually reducing the pulse width more and more, until a negative pulse width beyond 25 per-cent i8 exceeded, which means that the system cannot prevent flow even when the pump ls turned off, and thus lndicatlng an alarm state.
Again, the sequence for pump low-level alarm must be a short pulse width followed by a long pulse width, folIowed ~urther by an attempt by the system to reduce the pulse width below 75 percent. ~nder these conditions, flip-rlop 182 is "true", and the pulse width register is lnto the second 25 percent o~ its count range (256-511) 80 that line 216 i~ also "true" and, on the next DRZ pulse the gate 204 will be enabled to trigger an alarm state.
The ~ output of the ~lip-flop 182 is also directed over the line 167 as an lnput to the AND gate 165 (FIG. 4a) and, slnce the ~ output is normally "true", it typically does not affect the generation of the output pulse by the ~lip-flop 162, except when the fllp-flop 182 is set "true"
lndicating operation ln the negative region o~ the pulse wldth register 85.

~058469 Once operation in the "pump" mode has gone into the negative pulse wldt`n reglon of the puIse width regis-ter 8~, the system must be capable of comlng out of the pot~ntial alarm state, operatlng with a narrow pul~e width ln the positive region of the pulse width reglster 85, and be prepared to again resp~nd to an lmproper pulse width sequence calling for excesslve negative pulse w~dth. In thls regard, upon the elimination of the transitory con-dition calling ~or negative pulse width, the system should normally begin to produce very naxrow pulse width~, and the 768-1023 output line from the pulse width register decoder 86 should go "true", thu~ enabling the gate 214 on the next DRZ pulse and causing the fllp-~lop 182 to be "reset" on the next CLK pulse. This output conditlon will not cause the hlgh level alarm tAND gate 175) to be en-abled ince the ~ output of the flip-~lop 183 which is also one of the lnputs to the gate 175, will now be "fal~e".
During lnltial start-up of the overall system, :
the flip-~lop 182 is "reset" and the ~lip-flop 183 is set "true". ~he reason for this is that, in the start-up phase Or operatlon, whlch starts out wlth a very wide pulse period, (the pulse wldth register 85 is at "O") the flip-flops 183 and 182 must be lnitially set to indicate the appearance of havlng received a narrow pulse width on a fictitious preceding counting cycle. This will cause flip-flop 182 to be set "true'` by the very first DRZ pulse and al~o disable gate 165 which prevents the first pulse, which is a very wide pulse, from being dlrected to the output control device. The second output pulse, now a 30 very ~hort pulse, is prevented from activating the high level alarm because the ~llp-flop 182 is still "true" and 18 only "reset" a~ter the second output pulse has been lnltlated by a ~R2 pulse. The sequence o~ a slmulated lOS8~69 short pulse perlo~ and an lnltial wide pulse period would also normally activate the low level alarm ln the "con-troller mode". However, thls is prevented by the signal on llne 201 which disables the gate 195 during the start-up phase.
The function o~ the "no-drop" alarm produced by a "true output from the OR gate 225 is to count the number of D~Z pulses, i.e., the number o~ counting cycles ini-tiated ln the digital memory ~ubsy~tem, and to trigger an alarm state in the event no drops are detected wlthln a prescribed number o~ such counting cycles.
The DRZ pulse~ are dlrected over line 226 a~ input to a counter 227, typically a counter with a range of 27.
The output o~ the counter 227 is decoded via a decoder 228 whlch has two output linesJ one output line representing a count of 64 DRZ pulses, the other output line represent-ing a count of 96 DRZ pulse~. The counter 227 is "reset", each time a drop is detected, by a "true" output on line 230 representlng the state of the ~lip-~lop 119 in the control subsystem. It will be recalled that the latter ~lip-flop 119 gets set "true" during the counting cycle ~ollowing detectlon o~ a drop.
The "64" output llne from the deooder 228 is dlrected as one input to an AND gate 232 which has a ~secc,nd input, over llne 233, ~rom the ~ output of the start-up ~lip-~lop 114. Hence, during normal operation, when the sy~tem i~ out of the start-up phase, a count o~ 64 DRZ
pulses recelved, without any drops belng detected, will cause the gate 232 to go "true", and thereby trlgger an 30 alarm state through the OR gates 225 and 180.
When the sy~tem i~ still operating in the start-up phase, lt may take more counting cycles to generate the ~irst drop, since the system starts out with a very narrow ~ 058469pulse wldth. Therefore~ when the system ls in the start-up phase, the gate 232 ls dlsabled, and the "96" output line from the decoder 228 ls used to indlcate that 96 countlng cycles have occurred wlthout the detection of a drop, ln order to trigger the no-drop alarm state.
A "no actlon" alarm is also lncluded ln the alarm subsystem and get~ activated if there are no drops or out-put pulses from the system occurring for any period of ~ix minutes.
The "no actlon" alarm includes a fllp-flop 235 whlch resets a counter 236 ~typically a 27 counter) each time the fllp-flop is set "true". The counter 236 is "reset" through a pulse gate indlcated by a capacltor 237a and reslstor 237b. The pulse gate ls actually a dlffer-entlator which receives the Q output level of the flip-flop 235 and converts lt to a pulse capable of resettlng the counter 236. The flip-flop 235 is, in turn, set to its "true" state over the line 238 whenever the output fllp-flop 162 (FIG. 4a) g oe s "true". The output on line 238 20 is also coupled through a pulse gate conslsting of a capa-citor 239a and resistor 239b~ so that the pulse which sets the fllp-flop 235 only occurs when the output ~lip-flop 162 is going from its "false" state to its "true" state.
The flip-flop 235 is "reset" by an input over llne 241 from the drop detector 115 tFIG. 4b) each time a drop is detected Agaln, the output from the drop detector 115 is coupled to the "reset lnput of the flip-flop 235 through a pulse gate conslsting of a capacitor 242a and a resistor 242b.
If output pulses are lnitlally produced and then cease to be produced by the output flip-flop 162, there will be no pulses at the Q output of the fllp-flop 235 since there ls no change in the Q output of the flip-- ~051~469 ~lop and only a change in output will be passed by the p~lse gate. Similarly, if no drops occur, no pulses will o¢cur at the output of the flip-flop 235, slnce a drop is required to "reset" the flip-flop ~35 be~ore the flip-flop can be "set" again, and a pulse output will only be produced at the Q output of the fllp=~lop in going from the "reset" state to the "set" state Hence, if the flip-flop 235 keeps getting set rrom the output ~lip-~lop 162, without any drops being de-tected, the flip-flop 235 wlll already have been ln the "set state and no transition pulses wlll be generated at the Q output of the fllp-flop 235 and, accordingly, the counter 236 will not be "reset". Thus, it will be appar-ent that the presence of both drops and output pulses are necessary to generate pulse output ~rom the flip-flop 235 to reset the counter 236. I~ neither drops nor out-put pulses occur ~or approximately slx minutes, the counter 236 will be counted up by an oscillator 245 over line 246.
When a decoder 247 produces an output over line 248 indi-20 cating that counter 23~ has counted up 64 clock periods from the osclllator 245, a six minute "no action" alarm will be generated by the output o~ the OR gate 180.
It will be apparent that 64 periods, at 5.6 seconds ~or each period, yields a time lnterval o~ approximately 81x minutes. The reason ~or selecting the 8iX minute time interval is that, at very low pumplng rates, it can actually take as long as a period slightly less than six minutes between a pair o~ drops, and it ls desired to avoid the alarm state for this condition o~ operation.
The "no action" alarm will also be trlggered i~
the operator inadvertently selects a zero drop rate. ~nder those conditions, no DRZ pulses will be produced, and ther~
~ore, the "no-~rop" alarm condition monitored by the OR

- .......... ....

~058469 gate 225 wlll be ine~fective. However, the "no-actlon"
alarm will be triggered a~ter six mlnutes.
The vl~ual pulse width indication subsystem ls next descrlbed. Tne vlsual pulse width indlcation sub-system ls used only in connectlon wlth those output control devlces whlch depend on gravlty lnduced hydrostatic pre3sure levels, such as controllers rather than pumps.
A red light driver circult 251 and a green llght drlYer circult 252 are controlled by thelr own rllp-~lops 253 and 254, re~pectlvely. The J and K inputs to these - flip-flops 253, 254 are controlled by four AND gate3. An ~
AN~ gate 255 controls the J input o~ the ~lip-~lop 253, the ~;
K input o~ that ~lip-~lop being controlled by an AND gate 256. The ~ lnput o~ the ~lip-~lop 254 ls controlled by an ~~
AND gate 258, the K lnput o~ that ~llp-~lop being controlled by an AMD gate 257.
All ~our AND gates 255, 256, 257 and 258 have as one lnput the DRZ signal, over llne 1~7. Hence, the visual pulse width lndicatlon subsystem is only "set" or "re~et"
at the beglnning of a countlng cycle initlated by a DRZ
pulse. The ~ubsystem thus lndlcates between DRZ pulses where the subsystem had been ~et on the last DRZ pulse.
When the system ~lrst starts out (power turned on) the red light fllp-~lop 253 ls "reset" while the green light ~llp-~lop 254 ls set "true" over llne 260. Hence, on start-up, the green llght wlll go on lmmediately. When the flrst DRZ pulse comes along after such lnitiallzatlon, the pulse width reqister 85 has been initially set t~ the Pzero"
state, 80 that the 0-275 output line from the decoder 86 will be "true". This produce~ a "tr~e" lnput over line 262 to AND gate 255 and is inverted bY an lnverter 264 to pro-duce a "true" lnput over llne 266 to the gate 257. Hence, the green llght flip-flop 254 is "reset" by the flrst DRZ

7o-~ . '`" ~ -- ~0 S~ 4 ~9 pulse and, as the red light ~urns on, the green light momen-tarlly turns o~.
On the second DRZ pulse, the pulse wldth register 85 will now have nine counts less (~tart-up phase) than it had before, so that the output line 640-1023 from the de-coder 86 will now go "true 11~ resulting in enabling of the A~D gate 258 and dlsabllng of the gate 257, whlch "sets"
the fllp-flop 254 and turns on the green llght. At the same time, the 0-766 output line from the decoder 86 go~s "false which disables the gate 255 and enables the gate 256, so that the DRZ pulse "resets" the ~llp-~lop 253 and turns of~
the red light.
The visual pulse wldth indicatlon subsystem re-mains in the state with the green light on and the red llght off until the pulse width i9 sufflciently wide 80 that the o-766 line out o~ ~he decoder 86 agaln goe 9 "true" and enables the gate 255 to "set" the red light flip-flop 253 and turn on the red light. Since the 640-1023 output line ~rom the decoder 86 ls still "true", the green llght fllp-20 ~lop 254 has not yet been "reset". I~nder these conditions,both the red light and the green light will be turned on.
I~ the count in the pulse width register 85 iB
~urther reduced below a count of 640, then the output line 640_1o23 f~rom the decoder 86 will go "false", gate 258 will be disabled, gate 257 will be enabled, and the green llght fllp-flop 254 will be "reset" to tum off the green light.
The red light ~lip-flop 253 will now remain set to its "true" state, with the red light on, all the way down to a "zero" count in the pulse width register 85, indlcating very 30 wide pulses.
Hence, the visual pulse width indicatlon system enables ready observance by medical personnel of the output pulse wldth range of the fluid flow control system so that, if excesslvely wide or excesslvely narrow pulses are belng produced, the adminlstration set can be ad~usted, a~ by ralsing or lowering the bottle, to bring the output pulse width lnto the optimum operatlng range for the controller.
The new and improved ~luid flow control ~ystem of the present invention ls extremely accurate, reliable and easy to use. The system providPs enhanced dlgital pre-clslon ln selecting and ma~ntaining drop flow rates throughout a w~de range, and the system i8 quick to inform medical personnel o~ any lndlcatlons whlch mlght pose a hazard to the patlent. System testing and calibratlon ls con~iderably simpli~led and is essentially accomplished merely by checklng the clock 40. Hence, the system of the present lnvention minimizes the time-consuming and error-prone aspects o~ human monitoring and flow rate ad~ustment, provides substantlal improvement in economy, adaptabllity of a ~ingle system to a variety of di~ferent mechanical output control devices, and enhanced reliability, stability and accuracy over prevlous automatic control systems.
It will be apparent from the foregolng that~ while partlcular forms o~ the lnvention have been illustrated and described, various modiflcatlons can be made without departing from the ~pirit and scope o~ the invention.

Claims (18)

The embodiments of the invention in which an exclusive pro-perty or privilege is claimed are defined as follows:

1. A method used in the parenteral administration of medical liquids via an output control device, said method comprising the steps of: monitoring a pulse train representing output pulses intended to be generated for driving the output control device; searching for a first pulse width in a prescribed sequence; and searching for a second pulse width in said prescribed sequence; said second pulse width being of different duration than said first pulse width to provide an alarm indication.

2. The method as claimed in Claim 1, wherein said second pulse width is narrower than said first pulse width.

3. The method as claimed in Claim 1, wherein said second pulse width is wider than said first pulse width.

4. The method as claimed in Claim 2 including reinstating the search for said first pulse width and said second pulse width in sequence if, after said first pulse width is found, and prior to said second pulse width occurring, a pulse width having a magnitude in a prescribed range of magnitudes wider than said second pulse width occurs.

5. The method as claimed in Claim 3, including reinstating the search for said first pulse width and said second pulse width in sequence if, after said first pulse width is found, and prior to said second pulse width occurring, a pulse width having a magnitude in a prescribed range of magnitudes narrower than said second pulse width occurs.

6. The method as claimed in Claim 1, wherein said searching steps comprise: searching for a first pulse width in a first range of magnitudes, in a sequence of pulses; and searching for a second pulse width, in a second prescribed range of magnitudes, only after search-ing for said first pulse width has been successfully completed.

7. The method as claimed in Claim 6, wherein said first range of magnitudes is larger than said second range of magnitudes.

8. The method as claimed in Claim6, wherein said first range of magnitudes is smaller than said second range of magnitudes.

9. The method as claimed in Claim 6, including reinstating the searching for said first pulse width and said second pulse width, even after searching for said first pulse width has been successfully accomplished, if a pulse width occurs with a magnitude in a third prescribed range of magnitudes.

10. The method as claimed in Claim 9, wherein said first range of magnitudes is smaller than said second range of magnitudes, and said third range of magnitudes is smaller than said second range of magnitudes but larger than said first range of magnitudes.

11. The method as claimed in Claim 9, wherein said second range of magnitudes consists of pulse widths in the negative pulse width region.

12. The method as claimed in Claim 6 including: searching for a third pulse width, in a third prescribed range of magnitudes, only after searching for said first pulse width and said second pulse width has been successfully accomplished; and reinstating the searching for said first pulse width, said second pulse width and said third pulse width, even after searching for said first pulse width and said second pulse width has been successfully accomplished, if a pulse width occurs with a magnitude in a fourth prescribed range of magnitudes before the search for said third pulse width has been successfully accomplished.

13. Apparatus for use in a system for parenteral administra-tion of liquids at desired flow rates through a feeding tube from a liquid source to a patient, said apparatus comprising: electro-mechanical output control means for manipulating the feeding tube to vary the flow of liquid in the feeding tube, electrical pulsing means for providing output pulses to operate said output control means digital memory means for automatically varying the pulse width of said output pulses operating said control means, to achieve the desired flow rate; and means responsive to a predetermined sequence of pulse widths of said output pulses to provide an alarm indication.

14. The apparatus as claimed in Claim 13, wherein: said digital memory means includes at least one counter; and said pulse width can be a negative pulse width produced by overflow of said counter as a result of incrementing of said counter under the con-ditions of an excessively high rate of flow of fluid.

15. The apparatus as claimed in Claim 13, wherein said predetermined sequence of pulse widths is a narrow pulse width of prescribed magnitude followed by a wide pulse width of prescribed magnitude.

16. The apparatus as claimed in Claim 13, wherein said predetermined sequence of pulse widths is a wide pulse width of prescribed magnitude followed by a narrow pulse width of prescribe magnitude.

17. The apparatus as claimed in Claim 15, wherein said predetermined sequence of pulse widths is a narrow pulse width of prescribed magnitude followed by a wide pulse width of prescribed magnitude, followed by a narrow pulse width of prescribed width.

18. The apparatus as claimed in Claim 15 including means for overriding said means responsive to a predetermined sequence of pulses during start-up of the system.