CN104009032B - Cell and macro placement on fin grid - Google Patents
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- CN104009032B CN104009032B CN201410064299.7A CN201410064299A CN104009032B CN 104009032 B CN104009032 B CN 104009032B CN 201410064299 A CN201410064299 A CN 201410064299A CN 104009032 B CN104009032 B CN 104009032B
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Abstract
A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.
Description
Cross reference to related applications
The power of No. 61/770,224 u.s. patent application temporarily submitted on 2 27th, 2013 below application claims
Benefit, its entitled " cell and macro placement on fin grid ", this patent application is combined with entire contents
In this as reference.
Technical field
The present invention relates to semiconductor applications, more particularly it relates to the unit on a kind of fin grid and grand arrangement.
Background technology
Requirement more and more higher with the scaled all the more of integrated circuit and to integrated circuit speed is it is desirable to crystal
Pipe has increasing driving current and less and less size.In order to meet these conflicting requirements, develop fin
Formula field-effect transistor (finfet).Finfet has bigger groove width than flat transistor.Include position by being formed
Groove in the part on the side wall of semiconductor fin and the part on the top surface of semiconductor fin to increase groove width.Due to
The driving current of transistor is directly proportional to groove width, so the driving current of finfet is higher than the driving electricity of planar transistor
Stream.
Finfet is also made less and less, and the fin of finfet is made more and more thinner.This in order to be formed
Less fin, employs special optical technology, such as, diffraction and interference.The technique that this results in fin is increasingly complex.
Content of the invention
In the presence of solving the problems, such as prior art, according to an aspect of the invention, it is provided a kind of tube core, bag
Include: at least one standard block, comprising: the first border and the second boundary with respect to described first border, wherein, described first
Border and described the second boundary are parallel to first direction；Multiple first fin formula field effect transistors (finfet), including parallel to
First semiconductor fin of described first direction；And at least one memory macro, comprising: the 3rd border and with respect to the described 3rd
4th border on border, wherein, described 3rd border and described 4th border are parallel to described first direction；With multiple second
Finfet, including the second semiconductor fin parallel to described first direction, wherein, all at least one standard block described
The spacing of all semiconductor fin in semiconductor fin and at least one memory macro described be equal to described first semiconductor fin and
The integral multiple of the minimum spacing of described second semiconductor fin.
In described tube core, between described first border and described the second boundary first distance and described 3rd border
Second distance and described 4th border between is equal to the integral multiple of described minimum spacing.
In described tube core, also include: at least one simulation is grand, comprising: the 5th border and with respect to described 5th border
The 6th border, wherein, described 5th border and described 6th border are parallel to described first direction；And the multiple 3rd
Finfet, including the 3rd semiconductor fin parallel to described first direction, wherein, during at least one simulation described is grand all half
The spacing of conductor fin is equal to the integral multiple of described minimum spacing.
In described tube core, also include:
At least one input/output (i/o) is grand, comprising: the 5th border and the 6th border with respect to described 5th border,
Wherein, described 5th border and described 6th border are parallel to described first direction；And multiple 3rd finfet, including parallel
In the 3rd semiconductor fin of described first direction, wherein, the spacing of all semiconductor fin during at least one io described is grand is impartial
Integral multiple in described minimum spacing.
In described tube core, the longitudinal direction of the essentially all of semiconductor fin of all finfet in described tube core is all parallel
The essentially all spacing of all semiconductor fin of all finfet in described first direction, and described tube core is equal to
The integral multiple of described minimum spacing.
In described tube core, all semiconductor fin of all finfet in described tube core longitudinally each parallel to described the
All spacing of all semiconductor fin of all finfet in one direction, and described tube core are equal to described minimum spacing
Integral multiple.
In described tube core, the longitudinal direction of the essentially all semiconductor fin of all finfet in described tube core is all not parallel
In second direction, described second direction is perpendicular to described first direction.
According to a further aspect in the invention, there is provided a kind of tube core, comprising: standard block；Grand, selected from substantially by depositing
The group that reservoir is grand, simulation is grand, input/output is grand and combinations thereof is constituted；And fin formula field effect transistor (finfet),
Positioned at described standard block and described grand in, wherein, for forming essentially all half of all finfet in described tube core
Conductor fin is each parallel to first direction, and the spacing of described all semiconductor fin is equal to the minimum spacing in described spacing
Integral multiple, wherein, described minimum spacing is minimum spacing in described all spacing of described all semiconductor fin.
In described tube core, the described memory macro of described grand inclusion, and described memory macro includes static random storage
Device (sram) unit.
In described tube core, described memory macro includes the first border and the second boundary parallel to described first direction,
And the distance between described first border and described the second boundary are equal to the integral multiple of described minimum spacing.
In described tube core, described grand include described simulation grand, and described simulation grand inclusion operational amplifier grand.
In described tube core, described simulation is grand to include first border parallel with described first direction and the second boundary, and
And the distance between described first border and described the second boundary are equal to the integral multiple of described minimum spacing.
In described tube core, described io is grand for described grand inclusion, and described io grand inclusion static discharge (esd) is grand.
In described tube core, substantially do not have in described tube core semiconductor fin longitudinally perpendicular in described first direction.
According to another aspect of the invention, there is provided a kind of method, comprising: standard block is arranged in tube core layout,
Execute the step arranging described standard block using computer, wherein, the first border of described standard block and the second boundary divide
It is not aligned with the first gridline and the second gridline, and grid is distributed in entirely in described tube core layout；And by grand arrangement
In described tube core layout, described the 3rd grand border is relative with the 3rd gridline and the 4th gridline respectively with the 4th border
Standard, and described first gridline, described second gridline, described 3rd gridline and described 4th gridline belong to and have one
Cause the gridline of the grid of spacing, and described grand selected from by memory macro, the grand, input/output of simulation be grand and their group
Close constituted group.
In the process, after arranging described standard block and described grand step, described standard block and described
All fins of all fin formula field effect transistors (finfet) in grand are all aligned with gridline.
In the process, when the design of described tube core layout completes, all finfet's in described tube core layout
All fins are all aligned with gridline.
In the process, described grand inclusion memory macro.
In the process, described grand inclusion simulation is grand.
In the process, described grand inclusion input/output (io) is grand.
Brief description
In order to embodiment and its advantage are more fully understood, now combine the description that accompanying drawing carried out as reference, wherein:
Fig. 1 shows tube core layout and layout according to the exemplary embodiment circuit in tube core layout；
Fig. 2 shows semiconductor element according to exemplary embodiment and manufactures the circuit in this tube core；And
Fig. 3 schematically shows the computer for arranging tube core layout and the layout storage for storing tube core layout
Medium.
Specific embodiment
Below, manufacture and the use of various embodiments of the present invention are discussed in detail.It should be appreciated, however, that the invention provides being permitted
The applicable concept how can realize in various specific environments.The specific embodiment being discussed illustrate only manufacture and makes
With the concrete mode of the present invention, rather than limit the scope of the present invention.
Provide a kind of semiconductor element and integrated circuit formed therein and shape according to multiple exemplary embodiments
The method becoming this semiconductor element.Show the interstage forming this tube core.Discuss the modification of embodiment.In multiple views
In illustrative embodiment, similar reference number is used to represent similar element.
Fig. 1 shows the deposition step in IC design.According to some embodiments, using computer 10(Fig. 3) come
Execute this deposition step, what computer ran is the software of integrated design circuit.This software includes circuit layout tool, this instrument
There is arrangement and wiring function.Layout tool is configured to arrange standard block and grand, and they are through pre-designed function electricity
Road.In whole explanation, term " standard block " and " grand " refer to that layout finishes through pre-designed unit.Work as art
Language " standard block " is generally used for being related to little unit, and term " grand " be generally used for being related to big more not multi-functional
During unit, also it is used interchangeably term " standard block " and " grand ".Standard block and the grand circuit being stored in database form
In storehouse.In addition, standard block and grand (and corresponding data base) are stored in such as hard disk drive 12(Fig. 3) tangible deposit
In storage media.Computer 10 is connected with hard disk drive 12 electrical connection and signal, and can retrieve from hard disk drive 12
Standard block and grand to execute arrangement.
Fig. 1 shows the tube core layout 20 designing by circuit design insturment.Tube core layout 20 be tube core layout and
Run in computer 10.Tube core layout 20 can be a part for wafer layout (not shown), and this wafer layout includes multiple phases
Same tube core layout 20.As shown in Figure 2, manufacture the design circuit in wafer/tube core layout 20 in tube core/wafer 40.Weight
New reference Fig. 1, layout 20 includes a plurality of line 24 extending in the x direction.Line 24 is distributed in whole tube core layout 20 and has
Same intervals p1.In whole explanation, interval (spacing) p1 is referred to as spacing (pitch) p1.In certain embodiments, layout
20 also include a plurality of line 26 extending in y-direction, and y direction is perpendicular to x direction.Line 26 can also be distributed in whole layout 20
And there is consistent spacing p2.Spacing p1 can be equal to, be more than or less than spacing p2.In an alternative embodiment, tube core layout 20
Do not include line 26.Line 24 and 26 is hereinafter referred to as gridline.Line 24 and 26(Fig. 1) it is visual on the screen of computer 10
's.
Such as standard block 100, memory macro 200, simulation grand 300 and input/output (io) grand 400 integrated circuit with
Layout 20 is configured and is aligned with gridline 24.For example, standard block 100 can include phase inverter, nor door, nand door,
Xor door etc..Memory macro 200 can include SRAM (sram) is grand, dynamic RAM (dram) is grand etc.
Deng.Sram is grand or grand sram unit or the dram unit including forming array of dram, and can include for supporting memorizer
The support circuit of array processing.Support that circuit can include for example, row decoder, sense amplifier, power control circuit and electricity
Translational shifting circuit.Simulate grand 300 and can include phaselocked loop, operational amplifier, power amplifier etc..Io grand 400 can include
High speed serializer/simultaneously changes device (serial parallel and serializer), general io block, static discharge (esd) circuit etc..Circuit
100th, 200,300 and 400 can be at the position of needs that are pre-designed and being copied to layout 20, however circuit 100,200,
Some in 300 and 400 can also be step by step original place layout in tube core layout 20 rather than pre-designed and arrange
's.Fig. 1 shows the exemplary deposition step of one of memory cell 120.In certain embodiments, standard block 100, deposit
Reservoir grand 200 and simulation grand 300 are included in core circuit region 500, and io grand 400 can be only fitted to the io region of layout 20
In.
In whole description, when standard block or grand be referred to as with gridline 24 to punctual, corresponding standard block or grand
Border also align with gridline 24.For example, standard block 100, memory macro 200, the side of simulation grand 300 and io grand 400
Boundary 102,202,302 and 402 is aligned with gridline 24 respectively.Standard block 100, memory macro 200, simulation grand 300 and io
Transistor in grand 400 can be fin formula field effect transistor (finfet), this transistor include semiconductor fin and be located at partly lead
Gate electrode above body fin.For example, standard block 100 includes transistor 100, and this transistor includes fin 112 and gate electrode 114,
Memory macro 200 includes transistor 210, and this transistor includes fin 212 and gate electrode 214, and io grand 300 includes transistor 310, should
Transistor includes fin 312 and gate electrode 314, and io grand 400 includes transistor 410, and this transistor includes fin 412 and gate electrode
414.According to some embodiments, when standard block or grand be referred to as aligning with gridline 24 when, standard block or grand in
The fin of finfet can also be aligned with gridline 24.For example, the center line of fin 112,212,312 and 412 and corresponding gridline
24 align, however, the border of fin 112,212,312 and 412 can also be aligned with gridline 24 in an alternative embodiment.Fin
112nd, 212,312 direction that can have the lengthwise parallel with x direction with 412.
In a preferred embodiment, relative border 102 can be the first border or the second boundary respectively；Relative side
Boundary 202 can be the 3rd border or the 4th border respectively；Retive boundary 302 can be the 5th border and the 6th border respectively.This
Outward, relative border 402 can also be the 5th border and the 6th border respectively.
Memory macro 200 also includes multiple memory cells 120, and these memory cells can be for example sram unit
Or dram unit.Fig. 1 shows and a memory cell 120 is arranged in memory macro 200.In an alternate embodiment of the invention,
Pre-structured whole memory grand 200 and being simultaneously arranged in grand for whole memory 200 in tube core layout 20.Memory cell
120 border 122 is also aligned with gridline 24.
As can be seen that because fin 112,212,312 and 412 is aligned with the gridline 24 with equidistant from distance p1, so
The spacing of fin 112,212,312 and 412 is equal to n*p1, and wherein, n is equal to or the integer more than 0.Spacing p1 is also all fins
112nd, 212,312 and 412 minimum spacing.Alternatively specify, the spacing of all fins 112,212,312 and 412 is equal to grid
The integral multiple of spacing p1 of line 24.In order to determine the spacing of the fin not being aligned in y-direction, can be by extending fin (such as, fin
112) drawing extension line thus obtaining extension line, and align institute because extension line is parallel each other and with gridline 24
Can determine the spacing of extension line.For example, shown fin 112 and some fins 412 are not aligned in y-direction.However, they
Extension line (being also gridline 24) there is the spacing equal to n*p1.
In certain embodiments, all fins of all finfet in whole tube core layout 20 are respectively provided with parallel to x direction
Longitudinal direction, and there is no fin, or there is no that fin has the longitudinal direction extending in the y-direction.In addition, whole tube core cloth
There is no fin in office 20, or there is no that fin is not aligned with gridline 24.In an alternative embodiment, one or more standard lists
Unit 100, memory macro 200, some fins simulated in grand 300 and io grand 400 are not aligned with gridline 24, and remaining standard
Unit 100, memory macro 200, the fin of simulation grand 300 and io grand 400 and gridline 24 align.Gate electrode 114,214,314
With 414 perpendicular to fin 112,212,312 and 412, and there is the longitudinal direction parallel to y direction.
Due to standard block 100, memory macro 200, simulation grand 300 and io grand 400 border 102,202,302 and 402
Align with gridline 24 respectively, thus standard block 100, memory macro 200, simulation grand 300 and io grand 400 width w1,
The distance between w2, w3 and w4(retive boundary) be respectively spacing p1 integral multiple.
Standard block 100, memory macro 200, simulation grand 300 and io grand 400 respectively further comprise border 103,203,303 and
403, these borders are parallel to y direction.According to some embodiments, border 103,203,303 and 403 is not forced and gridline 24 phase
Be aligned.Therefore, border 103,203,303 and 403 can be aligned with the gridline 26 in arbitrary graphic pattern or not align.Can
In the embodiment of choosing, border 103,203,303 and 403 is not forced to align with gridline 26.Standard block 100, memory macro
200th, the gate electrode 114,214,314 and 414 in simulation grand 300 and io grand 400 can also be aligned with gridline 26, however,
In an alternative embodiment, they are not aligned with gridline 26.
Can be by the tangible media 12 in figure 3 of the circuit design storage in Fig. 1.The electricity of layout 20 can be used
Road is designed and to be manufactured integrated circuit.Fig. 2 shows physics semiconductor element 40, on a semiconductor wafer using in tube core layout 20
Circuit design manufacturing this physics semiconductor element.Therefore, each part shown in Fig. 2 all reflects the design in Fig. 1.
It should be understood that it is impossible to see gridline 24 and 26 again in tube core 40.However, in fig. 2, still illustrate for reference purposes
Gridline.However, fin 112,212,312 and 412 is distinguishing.In addition, for example, it can be found that standard by limiting feature
The border of at least some of unit 100, memory macro 200, simulation grand 300 and io grand 400.For example, standard block can wrap
Include dummy poly (or the pseudo- gate electrode being formed by the other materials beyond polysilicon) line, this line or electrically floating or be bound to vdd
Or vss.The center line of pseudo- silicon line can be aligned with the border of standard block 100.Further, since standard block 100, memory macro
200th, simulation grand 300 and io grand 400 can repeat in tube core 40, thus standard block 100, memory macro 200, simulate grand
300 and io grand 400 border can also be determined by comparing repeat patterns.
Although gridline 24 and 26(Fig. 1) it is not present in tube core 40, the extension line of fin 112,212,312 and 412
Can be identical, and the spacing of extension line can be to determine, equal to many times of spacing p1.In these embodiments, may be used
Minimum spacing p1 is determined with the minimum spacing by finding fin 112,212,312 and 412.According to some embodiments, fin 112,
212nd, one of 312 and 412 extension line can be selected as line of reference, and can be by measuring extension line and the ginseng of other fins
To determine the spacing of every other fin according to the distance between line.
In embodiment of the disclosure, by by standard block, memory macro, simulation is grand and io is grand fin and tube core or crystalline substance
The gridline of circle aligns to form very narrow fin, and its reason is, the formation of fin can use some diffractive technologies, and
The all fins being aligned with identical gridline thus can be formed simultaneously and they share identical processing step.However, such as
Really some fins are not aligned with the identical gridline of some other fin, and/or some fins have perpendicular with other fins
Longitudinal direction is if it has to being respectively formed these fins and increased manufacturing cost.
According to some embodiments, a kind of tube core includes at least one standard block, this standard block include the first border and
The second boundary relative with the first border.First border and the second boundary are parallel to first direction.At least one standard block is another
More than first finfet of outer inclusion, it includes the first semiconductor fin parallel to first direction.Tube core comprises additionally at least one
Memory macro, it has the 3rd border and fourth border relative with the 3rd border.3rd border and the 4th border are parallel to
One direction.At least one memory macro includes more than second finfet, and it includes the second semiconductor fin parallel to first direction.
All semiconductor fin at least one standard block and at least one memory macro be respectively provided with equal to the first semiconductor fin and
The spacing of the integral multiple of the minimum spacing of the second semiconductor fin.
According to other embodiment, a kind of tube core includes standard block and selected from substantially grand, defeated by memory macro, simulation
Enter/group that constituted of output macro and combinations thereof in grand.This tube core comprise additionally in positioned at each standard block and grand in
Finfet.It is essentially available for forming all semiconductor fin of all finfet in tube core each parallel to first direction.All
The spacing of semiconductor fin is equal to the integral multiple of the minimum spacing in spacing.Minimum spacing is all spacing of all semiconductor fin
In minimum spacing.
According to other other embodiment, a kind of method includes standard block is arranged in tube core layout, wherein, uses
The step that computer executes this arrangement standard block.First border of standard block and the second boundary respectively with the first gridline and
Second gridline aligns.Grid is distributed in whole tube core layout.The method comprises additionally in and is arranged in grand in tube core layout,
Wherein, the 3rd grand border and the 4th border are aligned with the 3rd gridline and the 4th gridline respectively.First gridline, second
Gridline, the 3rd gridline and the 4th gridline belong to the gridline of the grid with consistent spacing.This grand selected from by storing
The group that device is grand, simulation is grand, input/output is grand and combinations thereof is constituted.
Although the invention has been described in detail and its advantage, it is to be understood that can be will without departing substantially from appended right
In the case of seeking the spirit and scope of the present invention of restriction, make various different changes, replace and change.And, the model of the application
Enclose and be not limited in technique described in this specification, machine, manufacture, material component, device, the particular implementation of method and steps
Example.As it will be recognized by one of ordinary skill in the art that passing through the present invention, existing or Future Development for execution with according to this
Invent the essentially identical function of the described corresponding embodiment that adopted or obtain the technique of essentially identical result, machine, manufacture, material
Material component, device, method or step can be used according to the present invention.Therefore, claims should be included such
In the range of technique, machine, manufacture, material component, device, method or step.Additionally, every claim is constituted individually in fact
Apply example, and the combination of multiple claim and embodiment is within the scope of the invention.
Claims (20)
1. a kind of tube core, comprising:
At least one standard block, comprising:
First border and the second boundary with respect to described first border, wherein, described first border and described the second boundary are put down
Row is in first direction；
Multiple first fin formula field effect transistors (finfet), including the first semiconductor fin parallel to described first direction；With
And
At least one memory macro, wherein, at least one standard block described and at least one memory macro described are inhomogeneities
The unit of type, comprising:
3rd border and the 4th border with respect to described 3rd border, wherein, described 3rd border and described 4th border are put down
Row is in described first direction；With
Multiple second fin formula field effect transistors, including the second semiconductor fin parallel to described first direction, wherein, described extremely
The spacing of all semiconductor fin in all semiconductor fin and at least one memory macro described in a few standard block is equal
Integral multiple equal to described first semiconductor fin and the minimum spacing of described second semiconductor fin.
2. tube core according to claim 1, wherein, the first distance between described first border and described the second boundary with
And the second distance between described 3rd border and described 4th border is equal to the integral multiple of described minimum spacing.
3. tube core according to claim 1, also includes:
At least one simulation is grand, comprising:
5th border and the 6th border with respect to described 5th border, wherein, described 5th border and described 6th border are put down
Row is in described first direction；And
Multiple 3rd fin formula field effect transistors, including the 3rd semiconductor fin parallel to described first direction, wherein, described extremely
The spacing of all semiconductor fin during a few simulation is grand is equal to the integral multiple of described minimum spacing.
4. tube core according to claim 1, also includes:
At least one input/output (i/o) is grand, comprising:
5th border and the 6th border with respect to described 5th border, wherein, described 5th border and described 6th border are put down
Row is in described first direction；And
Multiple 3rd fin formula field effect transistors, including the 3rd semiconductor fin parallel to described first direction, wherein, described extremely
The spacing of all semiconductor fin during a few input/output is grand is equal to the integral multiple of described minimum spacing.
5. tube core according to claim 1, wherein, all of half of all fin formula field effect transistors in described tube core
Conductor fin longitudinally each parallel to all fin formula field effect transistors in described first direction, and described tube core all half
All spacing of conductor fin are equal to the integral multiple of described minimum spacing.
6. tube core according to claim 5, wherein, all of all fin formula field effect transistors in described tube core partly lead
The longitudinal of body fin partly leads each parallel to all of all fin formula field effect transistors in described first direction, and described tube core
All spacing of body fin are equal to the integral multiple of described minimum spacing.
7. tube core according to claim 1, wherein, all of all fin formula field effect transistors in described tube core partly lead
The longitudinal direction of body fin is all not parallel to second direction, and described second direction is perpendicular to described first direction.
8. a kind of tube core, comprising:
Standard block；
Grand, selected from by the group that memory macro, the grand, input/output of simulation be grand and combinations thereof is constituted；And
Fin formula field effect transistor (finfet), positioned at described standard block and described grand in, wherein, for forming described tube core
In all fin formula field effect transistors all semiconductor fin each parallel to first direction, and described all semiconductor fin
Spacing is equal to the integral multiple of the minimum spacing in described spacing, and wherein, described minimum spacing is described all semiconductor fin
Minimum spacing in described all spacing,
Wherein, described standard block and described memory macro are different types of units.
9. tube core according to claim 8, wherein, the described memory macro of described grand inclusion, and described memory macro bag
Include SRAM (sram) unit.
10. tube core according to claim 9, wherein, described memory macro includes first parallel to described first direction
Border and the second boundary, and the distance between described first border and described the second boundary are equal to the integer of described minimum spacing
Times.
11. tube cores according to claim 8, wherein, described grand include described simulation grand, and described simulation grand include fortune
Calculate amplifier grand.
12. tube cores according to claim 11, wherein, described simulation is grand to include first side parallel with described first direction
Boundary and the second boundary, and the distance between described first border and described the second boundary are equal to the integer of described minimum spacing
Times.
13. tube cores according to claim 8, wherein, the described input/output of described grand inclusion is grand, and described input/defeated
Go out grand inclusion static discharge (esd) grand.
14. tube cores according to claim 8, wherein, do not have in described tube core semiconductor fin longitudinally perpendicular in described
One direction.
A kind of 15. methods for manufacturing tube core, comprising:
Standard block is arranged in tube core layout, executes, using computer, the step arranging described standard block, wherein, described
First border of standard block and the second boundary are aligned with the first gridline and the second gridline respectively, and grid be distributed in whole
In individual described tube core layout；And
Be arranged in grand in described tube core layout, described the 3rd grand border and the 4th border respectively with the 3rd gridline and the 4th
Gridline aligns, and described first gridline, described second gridline, described 3rd gridline and described 4th gridline
Belong to the gridline of the grid with consistent spacing, and described grand selected from grand by memory macro, the grand, input/output of simulation
The group being constituted with combinations thereof, described standard block and described grand be different types of unit.
16. methods for manufacturing tube core according to claim 15, wherein, are arranging described standard block and described grand
Step after, described standard block and described grand in all fin formula field effect transistors (finfet) all fins all and grid
Ruling is aligned.
17. methods for manufacturing tube core according to claim 15, wherein, when the design of described tube core layout completes
When, all fins of all fin formula field effect transistors in described tube core layout are all aligned with gridline.
18. methods for manufacturing tube core according to claim 15, wherein, described grand inclusion memory macro.
19. methods for manufacturing tube core according to claim 15, wherein, described grand inclusion simulation is grand.
20. methods for manufacturing tube core according to claim 15, wherein, described grand inclusion input/output (io) is grand.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361770224P | 2013-02-27 | 2013-02-27 | |
| US61/770,224 | 2013-02-27 | ||
| US13/874,027 US9047433B2 (en) | 2013-02-27 | 2013-04-30 | Cell and macro placement on fin grid |
| US13/874,027 | 2013-04-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104009032A CN104009032A (en) | 2014-08-27 |
| CN104009032B true CN104009032B (en) | 2017-01-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410064299.7A Active CN104009032B (en) | 2013-02-27 | 2014-02-25 | Cell and macro placement on fin grid |
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| Country | Link |
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| US11675949B2 (en) | 2019-02-21 | 2023-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Space optimization between SRAM cells and standard cells |
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