CN104022775A - FIFO protocol based digital interface circuit for SerDes technology - Google Patents

Abstract

The invention belongs to the technical field of SerDes serial communication, in particular to a digital interface circuit based on FIFO protocol in SerDes technology. The invention is composed of two major parts, the digital circuit of the sending end and the digital circuit of the receiving end. The present invention introduces classic synchronous and asynchronous FIFOs and serial-parallel and parallel-serial conversion circuits in digital system design into the SerDes digital-analog interface, and encapsulates the digital-analog interface into a simple interface supporting FIFO read-write protocol, which is simple, feasible, and convenient to call. The ingenious use of FIFO effectively solves signal integrity problems such as cross-clock domain data transmission between chips and large transmission delay of feedback control signal channels. The extended bit width enhances the adaptability of the circuit design scheme.

Description

A Digital Interface Circuit Based on FIFO Protocol in SerDes Technology

technical field

The invention belongs to the technical field of SerDes serial communication, and in particular relates to a digital interface circuit based on FIFO protocol in SerDes technology.

Background technique

With the development of electronic communication technology, the industry puts forward higher and higher requirements for the transmission rate and channel bandwidth of the data interface. The SerDes serial interface with faster speed and lower resource overhead of channel bit width has gradually become the mainstream solution.

SerDes interface technology is the abbreviation of the combination of Serializer and Deserializer in English, which means that the circuit is composed of a pair of serializer and deserializer. It is a widely used time division multiplexing (Time Division Multiplex, TDM) and point-to-point (Point-to-Point, P2P) serial communication technology. SerDes technology converts multiple parallel signals into high-speed serial differential signals at the sending end, passes through transmission media (optical cables, copper wires, or low-resistance dielectrics, etc.), and finally combines high-speed serial signals into original low-speed parallel signals at the receiving end. Complete the data transfer process. This time-division multiplexing technology makes full use of the channel capacity of the transmission medium, reduces the number of transmission channels and device pins, thereby reducing channel resource overhead and facilitating system integration. In addition, the transmission using differential signals also has the advantages of strong anti-interference and low bit error rate.

The serializer and deserializer of the SerDes interface circuit are generally custom-designed by analog circuits, and the on-chip digital system is usually completed automatically by EDA tools. The interface between them is prone to signal integrity problems such as timing, crosstalk, and bit width mismatch, which brings great challenges to the design process.

Contents of the invention

The purpose of the present invention is to provide a digital interface circuit based on the FIFO protocol in SerDes technology to effectively solve the problem of signal integrity such as cross-clock domain data transmission between chips, large transmission delay of feedback control signal channels, and mismatch of bus and SerDes bit widths. question.

The digital interface circuit based on the FIFO protocol in the SerDes technology proposed by the present invention has an overall structure as shown in Figure 1, and it is composed of two parts: the digital circuit at the sending end and the digital circuit at the receiving end. At the sending end, the data is written into a synchronous first-in-first-out buffer queue through the FIFO protocol, and the parallel-to-serial conversion circuit of the latter stage reads the bus data from the buffer queue and splits them into several pieces of serial data and sends them to the SerDes serializer , the data is sent to the deserializer through the differential transmission channel after bit serialization, and the low-speed control signals such as write clock, write enable, and full write in advance pass through the transmission channel through the buffer. At the receiving end, the data output by the deserializer is first written into an asynchronous first-in-first-out buffer queue, and the serial-to-parallel conversion circuit of the latter stage reads the serial data and merges them into complete parallel bus data, and finally writes them into the synchronous First-in-first-out buffer queue for receiving end users to read.

In the present invention, the synchronous FIFO at the sending end and the synchronous FIFO at the receiving end have the same structure, synchronously means that the frequency and phase of the write clock and the read clock are consistent, and the FIFO read and write protocol is used for data communication, that is: the data w_data is in the write enable w_en is registered by the write clock w_clk during the high-level active period. When the data is full, the w_full feedback signal is pulled high; the read data r_data is taken out by the read clock r_clk during the high-level active period of the read enable r_en. When the data is read , the r_empty feedback signal is pulled high. Synchronization means that the frequency and phase of the write clock and the read clock are consistent. There are many classic implementations of synchronous FIFOs.

In the present invention, the asynchronous FIFO at the receiving end means that the frequency and phase of the write clock and the read clock have no correlation. clock. In addition, the write-full signal w_full_before of the write terminal is designed to be generated several clock cycles in advance to offset the delay of the signal in the buffer transmission single channel.

The SerDes interface circuit is generally composed of serializers and deserializers custom-designed by analog circuits. The interface between it and the on-chip digital system is prone to signal integrity problems such as timing, crosstalk, and bit width mismatch. Design poses a big challenge.

The present invention introduces classic synchronous and asynchronous FIFOs and serial-to-parallel and parallel-to-serial conversion circuits in digital system design into the SerDes digital-analog interface, and encapsulates the digital-analog interface into a simple interface that supports FIFO read and write protocols, which is simple, feasible, and easy to call . The ingenious use of FIFO effectively solves the problem of signal integrity such as cross-clock domain data transmission between chips and large transmission delay of feedback control signal channel. The extended bit width enhances the adaptability of the circuit design scheme.

Description of drawings

Figure 1 The overall structure of the SerDes digital interface circuit.

Figure 2 The state flow chart of the parallel-to-serial conversion circuit FSM.

Figure 3 The state flow diagram of the serial-to-parallel conversion circuit FSM.

Detailed ways

At the sending end, the bus data is written into a synchronous first-in-first-out buffer queue through the FIFO protocol. The FIFO protocol means: the data w_data is registered by the write clock w_clk when the write enable w_en is active at high level. When the data is full , the w_full feedback signal is pulled high; the read data r_data is taken out by the read clock r_clk during the high-level active period of the read enable r_en, and when the data is read, the r_empty feedback signal is pulled high.

The parallel-to-serial conversion circuit of the latter stage reads the bus data from the buffer queue and divides it into several pieces of serial data and sends them to the SerDes serializer in clock cycles. Serial device, write clock, write enable, write full in advance and other low-speed control signals through the buffer (buffer) through the transmission channel.

At the receiving end, the data output by the deserializer is first written into an asynchronous first-in-first-out buffer queue (FIFO). The write clock w_clk of the asynchronous FIFO comes from the clock of the sending end that has been buffered and transmitted by a single channel, and the read clock r_clk comes from the receiving end. terminal working clock. The write-full signal w_full_before of the writing end of the asynchronous FIFO is designed to be generated several clock cycles in advance and fed back to the sending end to offset the delay of the signal in the buffer transmission single channel. Then, the serial-to-parallel conversion circuit of the latter stage reads the serial data in the asynchronous FIFO and merges them into complete parallel bus data, and finally writes them into a synchronous first-in-first-out buffer queue for the receiving end user to read.

In the present invention, the parallel-to-serial conversion circuit reads the bus data from the buffer queue and splits it into several sections of serial data and sends it to the SerDes serial device. Since there are many cases of data read and write operations, the core uses a FSM (Finite state machine) control, the state flow chart is shown in Figure 2. The following describes the operation of the hardware structure in each state.

(1) The IDLE state is the state that the state machine enters when the hardware is reset, and it mainly realizes the reset of the state. When the synchronous FIFO of the previous stage is not empty and the asynchronous FIFO of the latter stage is not full, it jumps to the WR_FIRST state, otherwise it keeps the IDLE state.

(2) Read the first 8 bits of the 32-bit data line in the WR_FIRST state, and write it in when the next level of asynchronous FIFO is not full, otherwise enter the HD_FIRST state, if the write is successful, jump to the WR_SECOND state, here In the state, the data reading is completed.

(3) In the HD_FIRST state, do not do any operation, wait for the asynchronous FIFO of the next stage to be not full, if it is not full, enter the WR_SECOND state, otherwise, maintain the HD_FIRST state.

(4) Read 23~16 bits on the 32-bit data line in the WR_SECOND state, and write in when the asynchronous FIFO of the next stage is not full, otherwise enter the HD_SECOND state, and jump to the WR_THIRD state if the writing is successful.

(5) In the HD_SECOND state, do not do any operation, wait for the asynchronous FIFO of the next stage to be not full, if it is not full, enter the WR_THIRD state, otherwise, maintain the HD_SECOND state.

(6) Read 15~8 bits on the 32-bit data line in the WR_THIRD state, and write in when the asynchronous FIFO of the next stage is not full, otherwise enter the HD_THIRD state, and if the write is successful, jump to the WR_FORTH state.

(7) In the HD_THIRD state, do not do any operation, wait for the asynchronous FIFO of the next stage to be not full, if it is not full, enter the WR_FORTH state, otherwise, maintain the HD_THIRD state.

(8) Read the last 8 bits of the 32-bit data line in the WR_FORTH state, and write in the condition that the asynchronous FIFO of the subsequent stage is not full and the synchronous FIFO of the previous stage is not empty, otherwise enter the HD_FORTH state, if written If successful, jump to WR_FIRST state.

(9) In the HD_FORTH state, do not do any operation, wait for the asynchronous FIFO of the next stage to be not full and the synchronous FIFO of the previous stage is not empty, if satisfied, enter the WR_FIRST state, otherwise, maintain the HD_FORTH state.

In the present invention, the serial-to-parallel conversion circuit reads the asynchronous FIFO data and merges them into complete parallel bus data and finally writes them into a synchronous first-in-first-out buffer queue. Since there are many cases of data read and write operations, the core uses A FSM (finite state machine) control, the state flow chart shown in Figure 3. The following describes the operation of the hardware structure in each state.

(1) The IDLE state is the state that the state machine enters when the hardware is reset, and it mainly realizes the reset of the state. When the asynchronous FIFO of the previous stage is not empty and the synchronous FIFO of the latter stage is not full, it jumps to the RD_FIRST state, otherwise it maintains the IDLE state.

(2) Input the 8-bit data on the data line in the RD_FIRST state, and read the data when the previous level of asynchronous FIFO is not empty, otherwise enter the HD_FIRST state, if the reading is successful, jump to the RD_SECOND state.

(3) In the HD_FIRST state, do not do any operation, wait for the previous asynchronous FIFO to be non-empty, if not, enter the RD_SECOND state, otherwise, maintain the HD_FIRST state.

(4) Input the 8-bit data on the data line in the RD_SECOND state, and read the data when the previous level of asynchronous FIFO is not empty, otherwise enter the HD_SECOND state, if the reading is successful, jump to the RD_THIRD state.

(5) In the HD_SECOND state, do not do any operation, wait for the previous asynchronous FIFO to be non-empty, if not, enter the RD_THIRD state, otherwise, maintain the HD_SECOND state.

(6) Input the 8-bit data on the data line in the RD_THIRD state, and read the data when the asynchronous FIFO of the previous stage is not empty and the synchronous FIFO of the latter stage is not full, otherwise enter the HD_THIRD state, if the condition is met, jump Turn to RD_FORTH state.

(7) In the HD_THIRD state, do not do any operation, wait for the asynchronous FIFO of the previous stage to be non-empty and the synchronous FIFO of the subsequent stage is not full, if the conditions are met, enter the RD_FORTH state, otherwise, maintain the HD_THIRD state.

(8) Input 8-bit data on the data line in the RD_FORTH state, and read the data when the previous level of asynchronous FIFO is not empty, otherwise enter the HD_FORTH state, if the reading is successful, jump to the RD_FIRST state, in this state , to complete the data writing.

(9) In the HD_FORTH state, do not do any operation, wait for the previous asynchronous FIFO to be non-empty, if not, enter the RD_FIRST state, otherwise, maintain the HD_FORTH state.

SerDes digital interface circuit of the present invention, its working process is as follows:

(1) At the sending end, data is written into a synchronous first-in-first-out buffer queue through the FIFO protocol.

(2) The parallel-to-serial conversion circuit of the latter stage reads the bus data from the buffer queue and splits it into several pieces of serial data and sends them to the SerDes serializer.

(3) After the data is bit-serialized, it is sent to the deserializer through a differential transmission channel, and low-speed control signals such as write clock, write enable, and full write in advance pass through the transmission channel through the buffer.

(4) At the receiving end, the data output by the deserializer is first written into an asynchronous first-in-first-out buffer queue.

(5) The serial-to-parallel conversion circuit of the latter stage reads the serial data from the asynchronous FIFO and merges them into complete parallel bus data.

(6) The merged bus data is finally written into the synchronous first-in-first-out buffer queue at the receiving end for the receiving end user to read.

Claims (5)

1. A digital interface circuit based on the FIFO protocol in SerDes technology, which is characterized in that it consists of two parts: a digital circuit at the sending end and a digital circuit at the receiving end; at the sending end, data is written into a synchronous first-in-first-out through the FIFO protocol Buffer queue, the parallel-to-serial conversion circuit of the latter stage reads the bus data from the buffer queue and splits it into several pieces of serial data and sends it to the SerDes serializer. After the data is bit-serialized, it is sent to the deserializer through the differential transmission channel. At the receiving end, the data output by the deserializer is first written into an asynchronous first-in-first-out buffer queue, and the second-level The serial-to-parallel conversion circuit reads the serial data and merges them into complete parallel bus data, and finally writes them into a synchronous first-in-first-out buffer queue for the receiving end user to read. 2. The digital interface circuit according to claim 1, characterized in that: the structure of the synchronous FIFO at the sending end and the synchronous FIFO at the receiving end are consistent, synchronous means that the frequency and phase of the write clock and the read clock are consistent, and the FIFO read and write protocol is adopted for data communication. 3. The digital interface circuit according to claim 2, characterized in that: the receiving end asynchronous FIFO, the write clock w_clk comes from the sending end clock output through buffered transmission single channel, and the reading clock r_clk comes from the working clock of the receiving end ; The write-full signal w_full_before of the write terminal is generated several clock cycles in advance to offset the delay of the signal in the buffer transmission single channel. 4. The digital interface circuit according to claim 3, characterized in that: the parallel-serial conversion circuit reads the bus data from the buffer queue and splits it into several sections of serial data and sends it to the SerDes serializer, its core is a finite state machine. 5. digital interface circuit according to claim 4, it is characterized in that: after described serial-to-parallel conversion circuit reads asynchronous FIFO data, merges into complete parallel bus data and then writes into synchronous first-in-first-out buffer queue at last, At its core is a finite state machine.