CN104035228B - Liquid crystal display and method of manufacturing the same - Google Patents

Abstract

A liquid crystal display, comprising: a plurality of pixel electrodes and a plurality of common electrodes disposed on the first substrate and overlapping each other with a passivation layer interposed therebetween; and a connection portion disposed between the common voltage applying unit and the common electrode. The common electrode has a plurality of first cutouts, and the passivation layer has a plurality of second cutouts, the first cutouts and the second cutouts having substantially the same planar shape. The connection portion includes a lower connection portion formed of the same layer as the common electrode, and an upper connection portion disposed on the lower connection portion and including a low-resistance metal.

Description

Liquid crystal display and method of manufacturing the same

technical field

The present disclosure relates to a liquid crystal display and a method of manufacturing the same.

Background technique

A liquid crystal display, which is one of the most common types of flat panel displays currently in use, is a display device that rearranges liquid crystal molecules of a liquid crystal layer by applying a voltage to electrodes to control the amount of transmitted light.

Liquid crystal displays can be easily formed as thin films, but have poor side visibility compared to front visibility. Various types of liquid crystal alignment and driving methods have been developed to improve side visibility. One method for achieving wide viewing angles involves forming pixel electrodes and common electrodes on one substrate.

For a liquid crystal display, at least one of the two field generating electrodes (ie, the pixel electrode and the common electrode) has a plurality of cutouts and has a plurality of branch electrodes defined by the plurality of cutouts.

As such, in the case of forming two field generating electrodes on one display panel, in order to form each field generating electrode, a different photomask is required, which increases the manufacturing cost.

Furthermore, in the case where the common electrodes to which a predetermined voltage value is applied are connected to each other, the signal applied to the common electrodes may be delayed.

SUMMARY OF THE INVENTION

Exemplary embodiments provide a liquid crystal display and a method of manufacturing the same, which have low manufacturing costs and can prevent signal delay in a common electrode when two field generating electrodes are formed on one display panel.

Exemplary embodiments of the present disclosure provide a liquid crystal display including: a plurality of pixel electrodes and a plurality of common electrodes disposed on a first substrate and overlapping each other, with a passivation layer interposed between the pixel electrodes and the common electrodes; and The connection part is provided between the common voltage applying unit and the common electrode. The common electrode has a plurality of first slits, the passivation layer has a plurality of second slits, and the first slits and the second slits have substantially the same planar shape. The connection portion includes a lower connection portion formed of the same layer as the common electrode, and an upper connection portion provided on the lower connection portion and including a low-resistance metal.

The common voltage applying unit is disposed in a peripheral area around the display area, and the display area includes a plurality of pixel electrodes. The liquid crystal display may further include a common voltage line disposed on a portion of the common electrodes.

The common voltage line may be formed of the same layer as the upper connection portion.

The common voltage lines may extend parallel to the gate lines.

The common voltage line may be disposed between two adjacent data lines and extend parallel to the data lines.

The first substrate may include: an insulating substrate; a plurality of gate lines and a plurality of data lines disposed on the insulating substrate; a plurality of thin film transistors respectively connected to the plurality of gate lines and the plurality of data lines; and an organic layer disposed on the plurality of On each thin film transistor, a plurality of pixel electrodes and common electrodes are arranged on the organic layer.

The organic layer may be a color filter.

The liquid crystal display may further include a light blocking member disposed on the first substrate.

The liquid crystal display may further include: a second substrate facing the first substrate; and a compensation electrode disposed on an outer surface of the second substrate.

The common electrode on the first substrate may overlap the data line to form a first capacitor, and the compensation electrode on the second substrate may form a second capacitor together with the common electrode.

The compensation electrode may be configured to receive a voltage opposite in polarity to the data voltage applied to the data line to compensate for coupling between the data line and the common electrode.

Another exemplary embodiment of the present disclosure provides a method for manufacturing a liquid crystal display, including: forming a plurality of gate lines and a plurality of data lines on a first substrate; forming an organic layer on the plurality of gate lines and the plurality of data lines; forming a plurality of pixel electrodes on the organic layer; depositing a first layer including an insulating material on the plurality of pixel electrodes; depositing a second layer including a transparent conductor on the first layer; forming a photosensitive film pattern on the second layer; and utilizing The first photosensitive film pattern is used as an etching mask to etch the second layer and the first layer to simultaneously form a common electrode including a plurality of first cutouts and a passivation layer including a plurality of second cutouts.

The method of manufacturing a liquid crystal display may further include: forming a common voltage applying unit disposed in a peripheral area around a display area, the display area including a plurality of pixel electrodes; and forming a connection portion disposed between the common voltage applying unit and the common electrode .

The connection part may be formed together with the common electrode and the passivation layer.

The organic layer may include color filters.

The manufacturing method of the liquid crystal display may further include forming a light blocking member on the first substrate.

The manufacturing method of the liquid crystal display may further include forming a compensation electrode on an outer surface of the second substrate facing the first substrate.

Another exemplary embodiment of the present disclosure provides a method for manufacturing a liquid crystal display, including: forming a plurality of gate lines and a plurality of data lines on a first substrate; forming an organic layer on the plurality of gate lines and the plurality of data lines; forming a plurality of pixel electrodes on the organic layer; depositing a first layer including an insulating material on the plurality of pixel electrodes; depositing a second layer including a transparent conductor on the first layer; depositing a low-resistance metal on the second layer the third layer; forming a photosensitive film pattern on the third layer, which has a thickness that varies according to the position; by etching the third layer, the second layer and the first layer by using the second photosensitive film pattern as an etching mask, the forming a first insulating layer and forming a common electrode from the second layer; forming a third photosensitive film pattern by removing a part of the second photosensitive film pattern; and etching the third layer by using the third photosensitive film pattern as an etching mask, at A common voltage line is formed on a part of the common electrodes.

The manufacturing method of the liquid crystal display may further include crystallizing the second layer by annealing the first substrate before or after forming the third photosensitive film pattern.

The method of manufacturing a liquid crystal display may further include: forming a common voltage applying unit in a peripheral area around a display area including a plurality of pixel electrodes; and forming a connection portion between the common voltage applying unit and the common electrode, wherein the connection portion It may be formed simultaneously with the common electrode and the first insulating layer.

The forming of the connection part may include: forming the lower connection part from the same layer as the common electrode when forming the common electrode; and forming the upper connection part from the same layer as the common voltage line when forming the common voltage line.

According to an exemplary embodiment of the present disclosure, it is possible to prevent an increase in manufacturing cost and prevent a signal delay of a common electrode while two field generating electrodes are formed on one display panel.

Description of drawings

FIG. 1 is a layout diagram illustrating a liquid crystal display according to an exemplary embodiment of the present disclosure.

FIG. 2 is a cross-sectional view of the liquid crystal display taken along line II-II of FIG. 1 .

FIG. 3 is a cross-sectional view of the liquid crystal display taken along line III-III of FIG. 1 .

FIG. 4 is a cross-sectional view of the liquid crystal display taken along line IV-IV of FIG. 1 .

5A to 5C are cross-sectional views illustrating a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line V-V of FIG. 1 .

FIG. 6 is a layout diagram illustrating a part of a liquid crystal display according to an exemplary embodiment of the present disclosure.

FIG. 7 is a layout diagram illustrating a part of a liquid crystal display according to another exemplary embodiment of the present disclosure.

FIG. 8 is a cross-sectional view of the liquid crystal display taken along line VIII-VIII of FIG. 7 .

FIG. 9 is a layout diagram illustrating a liquid crystal display according to another exemplary embodiment of the present disclosure.

FIG. 10 is a cross-sectional view of the liquid crystal display taken along line X-X of FIG. 9 .

11 is a cross-sectional view illustrating a portion of a liquid crystal display according to another exemplary embodiment of the present disclosure, which is a cross-sectional view of the liquid crystal display taken along line II-II of FIG. 1 .

FIG. 12 is a waveform diagram of some signals applied to the liquid crystal display of FIG. 11 .

13 is a layout diagram illustrating a part of a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure.

FIG. 14 is a cross-sectional view of the liquid crystal display taken along line XIV-XIV of FIG. 13 .

FIG. 15 is a cross-sectional view of the liquid crystal display taken along line XV-XV of FIG. 13 .

FIG. 16 is a cross-sectional view of the liquid crystal display taken along line XVI-XVI of FIG. 13 .

17 , 20 and 23 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line II-II of FIG. 1 .

18 , 21 and 24 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line III-III of FIG. 1 .

19 , 22 and 25 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line IV-IV of FIG. 1 .

26 , 31 , 36 , 41 , 46 and 51 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along the line XIV-XIV of FIG. 13 . Sectional view.

FIGS. 27 , 32 , 37 , 42 , 47 and 52 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, taken along the line XV-XV of FIG. 13 . Sectional view.

28 , 33 , 38 , 43 , 48 and 53 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along the line XVI-XVI of FIG. 13 . Sectional view.

29 , 34 , 39 , 44 , 49 and 54 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line X-X of FIG. 9 .

30 , 35 , 40 , 45 , 50 and 55 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line VIII-VIII of FIG. 7 . Sectional view.

Detailed ways

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which exemplary embodiments of the disclosure are shown. As those skilled in the art would realize, the described embodiments may be embodied in various different forms, all without departing from the spirit or scope of the present disclosure.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present.

A liquid crystal display according to an exemplary embodiment of the present disclosure will be described with reference to the accompanying drawings.

First, a liquid crystal display according to an exemplary embodiment of the present disclosure will be described with reference to FIGS. 1 to 24 . FIG. 1 is a layout diagram illustrating a liquid crystal display according to an exemplary embodiment of the present disclosure. 2 is a cross-sectional view of the liquid crystal display taken along line II-II of FIG. 1 , FIG. 3 is a cross-sectional view of the liquid crystal display taken along line III-III of FIG. 1 , and FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 1 A cross-sectional view of a liquid crystal display.

1 to 4 , a liquid crystal display according to an exemplary embodiment of the present disclosure includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two panels 100 and 200 .

First, the lower panel 100 will be described.

Gate conductors including gate lines 121 are formed on the first insulating substrate 110 including transparent glass or plastic.

The gate line 121 includes a gate electrode 124 and a wide gate pad portion 129 for connection with another layer or external driver circuit. The gate line 121 may include an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, such as molybdenum (Mo) or Molybdenum-based metals of molybdenum alloys, chromium (Cr), tantalum (Ta) and titanium (Ti). However, the gate line 121 may have a multi-layer structure including at least two conductive layers having different physical properties.

A gate insulating layer 140 including silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 121 , 124 and 129 . The gate insulating layer 140 may have a multi-layered structure including at least two insulating layers having different physical properties.

A semiconductor 154 including amorphous silicon or polysilicon is formed on the gate insulating layer 140 . The semiconductor 154 may include an oxide semiconductor.

Ohmic contacts 163 and 165 are formed on the semiconductor 154 . The ohmic contacts 163 and 165 may include silicide or a material such as n+ hydrogenated amorphous silicon in which an n-type impurity such as phosphorus is doped at a high concentration. Ohmic contacts 163 and 165 may be provided on semiconductor 154 to be paired. If the semiconductor 154 is an oxide semiconductor, the ohmic contacts 163 and 165 may be omitted.

Data conductors including data lines 171 , source electrodes 173 and drain electrodes 175 are disposed on the ohmic contacts 163 and 165 and the gate insulating layer 140 .

The data line 171 includes a data pad portion 179 for connection with another layer or an external driving circuit. The data lines 171 transmit data signals and extend mainly in the vertical direction to cross the gate lines 121 .

In this case, the data line 171 may have a first curved portion in a curved shape to maximize the transmittance of the liquid crystal display, and the curved portion may have a letter V shape when viewed from above, the apex of which is in the middle area of the pixel area. A second curved portion forming a predetermined angle with the first curved portion may be further included in a middle region of the pixel region.

The first bent portion of the data line 171 may form an angle of about 7° with respect to the vertical reference line perpendicular to the extending direction of the gate line 121 . The second curved portion disposed in the middle region of the pixel region may further form an angle of about 7° to about 15° with respect to the first curved portion.

The source electrode 173 is a part of the data line 171 and is disposed on the same line as the data line 171 . The drain electrode 175 extends parallel to the source electrode 173 . Therefore, the drain electrode 175 is parallel to a part of the data line 171 .

The drain electrode 175 includes a first rod-shaped end portion and a second wide end portion facing the source electrode 173 provided on the gate electrode 124 .

The first semiconductor 159 and the first contact assistant 169 are disposed under the data pad portion 179 . The first semiconductor 159 and the first contact assistant 169 may be omitted.

The gate electrode 124 , the source electrode 173 , and the drain electrode 175 form a thin film transistor (TFT) together with the semiconductor 154 , and a channel is formed in the semiconductor 154 between the source electrode 173 and the drain electrode 175 .

The liquid crystal display according to the exemplary embodiment of the present disclosure includes the source electrode 173 disposed on the data line 171 while the drain electrode 175 extends parallel to the data line 171, which can increase the width of the thin film transistor without increasing the area of the data conductor, thereby increasing the Aperture ratio of large liquid crystal displays.

However, in the case of the liquid crystal display according to another exemplary embodiment of the present disclosure, the source electrode 173 and the drain electrode 175 may have different shapes.

The data line 171 and the drain electrode 175 may include a refractory metal such as molybdenum, chromium, tantalum, and titanium or alloys thereof, and may have a refractory metal layer (not shown) and a low-resistance conductive layer (not shown). Multilayer structure. Examples of the multilayer structure include: a double layer including a lower layer of chromium or molybdenum (alloy) and an upper layer of aluminum (alloy); and a triple layer including a lower layer of molybdenum (alloy), an intermediate layer of aluminum (alloy), and an upper layer of molybdenum (alloy). However, the data lines 171 and the drain electrodes 175 may include various other metals or conductors than those listed.

The first passivation layer 180x is disposed on the data conductors 171 , 173 , 175 and 179 , the gate insulating layer 140 , and the exposed portion of the semiconductor 154 . The first passivation layer 180x may include an organic insulating material or an inorganic insulating material.

The organic layer 80 is disposed on the first passivation layer 180x. The organic layer 80 has a thickness greater than that of the first passivation layer 180x and may have a flat upper surface.

The first thickness H1 of the organic layer 80 disposed in the display area in which the plurality of pixels are disposed and the gate pads are formed may be greater than the second thickness H2 of the organic layer 80 disposed in the peripheral area section 129 and data pad section 179.

Alternatively, the organic layer 80 may be disposed in the display area in which the plurality of pixels are disposed, but may not be disposed in the peripheral area in which the gate pad portion and the data pad portion are formed.

In the liquid crystal display according to another exemplary embodiment of the present disclosure, the organic layer 80 may be omitted.

The organic layer 80 is removed from regions corresponding to the drain electrode 175 , the gate pad portion 129 and the data pad portion 179 .

In the first passivation layer 180x and the gate insulating layer 140 in the region where the organic layer 80 is removed and corresponding to the gate pad portion 129, a first contact hole 186 exposing the gate pad portion 129 is formed.

In the first passivation layer 180x disposed in the region where the organic layer 80 is removed and corresponding to the data pad portion 179, a second contact hole 187 exposing the data pad portion 179 is formed.

In the first passivation layer 180x provided in the region where the organic layer 80 is removed and corresponds to the drain electrode 175, a third contact hole 185 is formed.

The pixel electrode 191 is formed on the organic layer 80 . The pixel electrode 191 includes curved edges substantially parallel to the first curved portion and the second curved portion of the data line 171 .

The pixel electrode 191 may include a transparent conductive layer such as ITO or IZO.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the third contact hole 185 to receive a voltage from the drain electrode 175 .

The first contact assistant 96 is formed on the gate pad portion 129 exposed through the first contact hole 186 , and the second contact assistant 97 is formed on the data pad portion 179 exposed through the second contact hole 187 .

The pixel electrode 191, the first contact assistant 96 and the second contact assistant 97 may be simultaneously formed on the same layer.

The second passivation layer 180y is formed on the pixel electrode 191, and the common electrode 270 is formed on the second passivation layer 180y. The common electrode 270 may include a transparent conductive layer such as ITO or IZO.

The second passivation layer 180y and the common electrode 270 have substantially the same planar shape.

The second passivation layer 180y and the common electrode 270 are disposed in the display area in which the plurality of pixels are disposed, but not in the peripheral area in which the gate pad part 129 and the data pad part 179 are formed.

The common electrode 270 has a plurality of first notches 271 , and the second passivation layer 180y has a plurality of second notches 181 . The first cutout 271 of the common electrode 270 and the second cutout 181 of the passivation layer 180y have the same planar shape. More specifically, the edge of the first cutout 271 overlaps the edge of the second cutout 181 .

Although not shown, an alignment layer is coated on portions of the pixel electrode 191 and the common electrode 270 exposed through the second cutout 181, and the alignment layer may be a vertical alignment layer rubbed in a predetermined direction. However, according to the liquid crystal display of another exemplary embodiment of the present disclosure, the alignment layer may include a photoreactive material to be photoaligned.

Then, the upper panel 200 will be described.

The light blocking member 220 is formed on the second insulating substrate 210 made of transparent glass or plastic. The light blocking member 220 is also called a black matrix and blocks light leakage.

Also, a plurality of color filters 230 are formed on the second substrate 210 .

The protective layer 250 is formed on the color filter 230 and the light blocking member 220 . The protective layer 250 may include an organic insulator, provide a flat surface, and may prevent the color filter 230 from being exposed. The protective layer 250 may be omitted.

An alignment layer may be disposed on the protective layer 250 .

The liquid crystal layer 3 includes a liquid crystal material having positive dielectric anisotropy. The liquid crystal molecules of the liquid crystal layer 3 are aligned such that the direction of the long axis thereof is parallel to the surfaces of the panels 100 and 200 , which has a 90° twisted helical structure from the rubbing direction of the alignment layer to the upper panel 200 .

The pixel electrode 191 receives a data voltage from the drain electrode 175, and the common electrode 270 receives a common voltage having a predetermined magnitude from a common voltage applying unit disposed outside the display area.

The pixel electrode 191 and the common electrode 270 as field generating electrodes generate an electric field, and the liquid crystal molecules disposed on the two electrodes 191 and 270 rotate in a direction parallel to the electric field direction. Thus, the polarization of light passing through the liquid crystal layer changes according to the rotation direction of the liquid crystal molecules.

In the liquid crystal display according to an exemplary embodiment of the present disclosure, the second passivation layer 180y disposed on the pixel electrode 191 and the common electrode 270 disposed on the second passivation layer 180y have substantially the same planar shape. In more detail, the common electrode 270 has a plurality of first slits 271, the second passivation layer 180y has a plurality of second slits 181, and the first slits 271 and the second slits 181 have substantially the same planar shape. More specifically, the edge of the first cutout 271 overlaps the edge of the second cutout 181 .

Therefore, the second passivation layer 180y and the common electrode 270 may be formed together by using one photomask.

Therefore, the manufacturing cost of the liquid crystal display can be prevented from increasing.

For the liquid crystal display according to the exemplary embodiment shown in FIGS. 1 to 4 , the organic layer 80 is disposed on the first passivation layer 180 x of the lower panel 100 , and the color filter 230 and the light blocking member 220 are disposed on the upper panel 200 . However, for the liquid crystal display according to another exemplary embodiment of the present disclosure, the color filter 230 , instead of the organic layer 80 , may be disposed on the lower panel 100 instead of the upper panel 200 . In this case, the light blocking member 220 may also be provided on the lower panel 100 instead of the upper panel 200 .

This will be described with reference to FIGS. 5A to 5C. 5A to 5C are cross-sectional views illustrating a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line V-V of FIG. 1 .

Referring to FIG. 5A , the light blocking member 220 is disposed on the first passivation layer 180x of the lower panel 100 . The light blocking members 220 are disposed in regions corresponding to the gate lines 121 and the data lines 171 . The color filter 230 is disposed on the first passivation layer 180x partially overlapping the light blocking member 220 . The capping layer 180 is disposed on the light blocking member 220 and the color filter 230 . The cap layer 180 prevents the pigments of the light blocking member 220 and the color filter 230 from penetrating into the liquid crystal layer 3 .

The pixel electrode 191 is disposed on the cap layer 180 , and the second passivation layer 180y and the common electrode 270 are disposed on the pixel electrode 191 . The common electrode 270 and the second passivation layer 180y have the first cutout 271 and the second cutout 181, and the first cutout 271 and the second cutout 181 have substantially the same planar shape. More specifically, the edge of the first cutout 271 overlaps the edge of the second cutout 181 .

There is no light blocking member 220 or color filter 230 provided on the upper panel 200 .

Referring to FIG. 5B , the color filter 230 is disposed on the first passivation layer 180x of the lower panel 100 . The color filter 230 is disposed in a region corresponding to the pixel electrode 191 . The light blocking member 220 is disposed on the color filter 230 and partially overlaps the first passivation layer 180x. The light blocking members 220 are disposed in regions corresponding to the gate lines 121 and the data lines 171 . The capping layer 180 is disposed on the color filter 230 and the light blocking member 220 . The cap layer 180 prevents the pigments of the light blocking member 220 and the color filter 230 from penetrating into the liquid crystal layer 3 .

The pixel electrode 191 is disposed on the cap layer 180 , and the second passivation layer 180y and the common electrode 270 are disposed on the pixel electrode 191 . The common electrode 270 and the second passivation layer 180y have the first cutout 271 and the second cutout 181, and the first cutout 271 and the second cutout 181 have substantially the same plan shape. More specifically, the edge of the first cutout 271 overlaps the edge of the second cutout 181 .

There is no light blocking member 220 or color filter 230 provided on the upper panel 200 .

Referring to FIG. 5C , the liquid crystal display according to the exemplary embodiment is similar to the liquid crystal display according to the exemplary embodiment shown in FIG. 5B .

The light blocking member 220 is disposed on the first passivation layer 180x of the lower panel 100 . The light blocking members 220 are disposed in regions corresponding to the gate lines 121 and the data lines 171 . The color filter 230 is disposed on the light blocking member 220 and partially overlaps the first passivation layer 180x.

The pixel electrode 191 is disposed on the color filter 230 , and the second passivation layer 180y and the common electrode 270 are disposed on the pixel electrode 191 . The common electrode 270 and the second passivation layer 180y have the first cutout 271 and the second cutout 181, and the first cutout 271 and the second cutout 181 have substantially the same plan shape. More specifically, the edge of the first cutout 271 overlaps the edge of the second cutout 181 .

There is no light blocking member 220 or color filter 230 provided on the upper panel 200 .

In the liquid crystal display according to the exemplary embodiment, the cover layer 180 provided on the light blocking member 220 and the color filter 230 is not provided, unlike the liquid crystal display according to FIG. 5B .

The planar shape of the common electrode 270 according to an exemplary embodiment of the present disclosure will be described with reference to FIG. 6 . FIG. 6 is a layout diagram illustrating a part of a liquid crystal display according to an exemplary embodiment of the present disclosure.

6 , a liquid crystal display according to an exemplary embodiment of the present disclosure includes a display area DA in which a plurality of pixels are formed and a peripheral area PA surrounding the display area DA, such as the liquid crystal display described with reference to FIGS. 1 to 4 .

The common electrode 270 is formed in the display area DA and has a plurality of first cutouts 271 disposed in each pixel area. A plurality of first cutouts 271 are formed at positions corresponding to the pixel electrodes 191 provided in each pixel region.

In the peripheral area PA, the common voltage applying unit 50 that applies the common voltage to the common electrode 270 is provided, and the connection portion 27 is provided between the common voltage applying unit 50 and the common electrode 270 . The common electrode 270 and the connection part 27 may be simultaneously formed on the same layer.

The common electrode 270 according to an exemplary embodiment of the present disclosure will be described in more detail with reference to FIGS. 7 and 8 . 7 is a layout view illustrating a portion of a liquid crystal display according to another exemplary embodiment of the present disclosure, and FIG. 8 is a cross-sectional view of the liquid crystal display taken along line VIII-VIII of FIG. 7 .

7 and 8 , a liquid crystal display according to an exemplary embodiment of the present disclosure includes a display area DA in which a plurality of pixels are formed and a peripheral area PA surrounding the display area DA, such as the liquid crystal display described with reference to FIGS. 1 to 4 .

The common electrode 270 is formed in the display area DA and has a plurality of first cutouts 271 disposed in each pixel area. A plurality of first cutouts 271 are formed at positions corresponding to the pixel electrodes 191 provided in each pixel region.

The common voltage applying unit 50 is disposed in the peripheral area PA and applies a common voltage to the common electrode 270 , and the connection portion 27 is disposed between the common voltage applying unit 50 and the common electrode 270 . The connection part 27 includes a lower connection part 27p formed of the same layer as the common electrode 270 and an upper connection part 27q provided on the lower connection part 27p.

The lower connection portion 27p of the connection portion 27 includes a transparent conductor, and similarly to the common electrode 270, the upper connection portion 27q of the connection portion 27 includes a low-resistance metal.

By forming the connecting portion 27 connecting the common voltage applying unit 50 to the common electrode 270 by the double layer including the lower connecting portion 27p and the upper connecting portion 27q, the common voltage applied from the common voltage applying unit 50 can be transmitted to the common electrode 270 without There is no signal delay.

The second passivation layer 180y, the common electrode 270 and the connection part 27 may be formed by using one photomask.

A liquid crystal display according to another exemplary embodiment of the present disclosure will be described with reference to FIGS. 9 and 10 . FIG. 9 is a layout view illustrating a portion of a liquid crystal display according to another exemplary embodiment of the present disclosure, and FIG. 10 is a cross-sectional view of the liquid crystal display taken along line X-X of FIG. 9 .

Referring to FIGS. 9 and 10 , the liquid crystal display according to the exemplary embodiment is similar to the liquid crystal display according to the exemplary embodiment shown in FIGS. 1 to 4 .

A liquid crystal display according to another exemplary embodiment of the present disclosure includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two panels 100 and 200 .

First, the lower panel 100 will be described.

The gate line 121 including the gate electrode 124 is provided on the first insulating substrate 110 , and the gate insulating layer 140 is formed on the gate line 121 .

The semiconductor layer 154 is formed on the gate insulating layer 140 . Ohmic contacts (not shown) are formed on the semiconductor 154 . If the semiconductor 154 is an oxide semiconductor, the ohmic contacts 163 and 165 may be omitted.

The data line 171 including the source electrode 173 and the drain electrode 175 is disposed on the ohmic contact and the gate insulating layer 140 .

The data line 171 may have a first curved portion in a curved shape to maximize the transmittance of the liquid crystal display, and the curved portion may have a letter V shape with a vertex in a middle area of the pixel area. A second curved portion forming a predetermined angle with the first curved portion may be further included in a middle region of the pixel region.

The first passivation layer 180x is disposed on the data conductors 171 , 173 and 175 , the gate insulating layer 140 , and the exposed portion of the semiconductor 154 . The first passivation layer 180x may include an organic insulating material or an inorganic insulating material.

The organic layer 80 is disposed on the first passivation layer 180x. The organic layer 80 has a thickness greater than that of the first passivation layer 180x and may have a flat upper surface.

As described with reference to FIGS. 5A to 5C , the organic layer 80 may be the color filter 230 .

The organic layer 80 and the first passivation layer 180x have third contact holes 185 formed therethrough.

The pixel electrode 191 is formed on the organic layer 80 . The pixel electrode 191 includes curved edges substantially parallel to the first curved portion and the second curved portion of the data line 171 .

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the first contact hole 185 to receive a voltage from the drain electrode 175 .

The second passivation layer 180y is formed on the pixel electrode 191, and the common electrode 270 is formed on the second passivation layer 180y.

The second passivation layer 180y and the common electrode 270 have substantially the same planar shape.

The common electrode 270 has a plurality of first cutouts 271, and the second passivation layer 180y has a plurality of second cutouts (not shown). The first cutout 271 and the second cutout have the same planar shape. More specifically, the edge of the first cutout 271 overlaps the edge of the second cutout.

The common voltage line 28 is provided on the common electrode 270 . The common voltage line 28 may include a low resistance metal to prevent signal delay of the common electrode 270 .

In the liquid crystal display according to the exemplary embodiment, the common voltage lines 28 extend parallel to the gate lines 121 , but in the liquid crystal display according to another exemplary embodiment of the present disclosure, the common voltage lines 28 may extend parallel to the data lines 171 . In this case, two pixel electrodes 191 may be disposed between two adjacent data lines 171 , and the common voltage line 28 may be disposed between two adjacent data lines 171 and between two pixel electrodes 191 , to prevent light leakage between the two pixel electrodes 191 .

In the liquid crystal display according to the exemplary embodiment, similar to the liquid crystal display according to the exemplary embodiment shown in FIGS. 7 and 8 , the connection part 27 between the common voltage 270 and the common voltage applying unit 50 may include the lower connection part 27p and The upper connection portion 27q provided on the lower connection portion 27p.

The common voltage line 28 may be formed of the same layer as the upper connection portion 27q of the connection portion 27 .

That is, the common electrode 270 and the lower connection part 27p of the connection part 27 may be formed of the same layer, and the common voltage line 28 and the upper connection part 27q of the connection part 27 may be formed of the same layer.

Although not shown, an alignment layer is provided on a portion of the pixel electrode 191 exposed through the first cutout 271 and the second cutout 181 .

The upper panel 200 will be described.

A light blocking member (not shown in FIG. 10 ) and a plurality of color filters 230 are formed on the second insulating substrate 210 . The protective layer 250 is formed on the color filter 230 and the light blocking member. An alignment layer may be disposed on the protective layer 250 .

As described above, if the organic layer 80 is a color filter, the color filter 230 of the upper panel 200 may be omitted. In addition, the light blocking member of the upper panel 200 may also be formed on the lower panel 100 .

The liquid crystal layer 3 includes a liquid crystal material having positive dielectric anisotropy. The liquid crystal molecules of the liquid crystal layer 3 are aligned such that the direction of their long axis is parallel to the surfaces of the panels 100 and 200 , which has a 90° twisted helical structure from the rubbing direction of the alignment layer to the upper panel 200 .

The pixel electrode 191 receives a data voltage from the drain electrode 175, and the common electrode 270 receives a common voltage having a predetermined magnitude from a common voltage applying unit disposed outside the display area.

The pixel electrode 191 and the common electrode 270 are field generating electrodes that generate an electric field, so the liquid crystal molecules disposed on the two electrodes 191 and 270 rotate in a direction parallel to the electric field direction. Thus, the polarization of light passing through the liquid crystal layer changes according to the rotation direction of the liquid crystal molecules.

In the liquid crystal display according to an exemplary embodiment of the present disclosure, the second passivation layer 180y and the common electrode 270 have substantially the same planar shape. In more detail, the common electrode 270 has a plurality of first slits 271, the second passivation layer 180y has a plurality of second slits, and the first slits 271 and the second slits have substantially the same planar shape. More specifically, the edge of the first cutout 271 overlaps the edge of the second cutout 181 .

Further, the lower connection portion 27p of the connection portion 27 is formed of the same layer as the common electrode 270 , and the common voltage line 28 is formed of the same layer as the upper connection portion 27q of the connection portion 27 . In addition, the second passivation layer 180y, the common electrode 270, the connection portion 27, and the common voltage line 28 may be simultaneously formed by using one photomask.

Therefore, the manufacturing cost of the liquid crystal display can be prevented from increasing, and the signal delay of the common electrode 270 can be prevented.

Many features of the liquid crystal displays according to the exemplary embodiments described with reference to FIGS. 1 to 4 , 5A to 5C, 6, 7 and 8 may be applied to the liquid crystal displays according to the exemplary embodiments.

A liquid crystal display according to another exemplary embodiment of the present disclosure will be described with reference to FIGS. 11 and 12 . 11 is a cross-sectional view illustrating a portion of a liquid crystal display according to another exemplary embodiment of the present disclosure, and FIG. 12 is a waveform diagram of some signals applied to the liquid crystal display of FIG. 11 .

Referring to FIG. 11 , the liquid crystal display according to the exemplary embodiment further includes a compensation electrode 280 disposed on the outer surface of the upper panel 200 .

The common electrode 270 disposed on the lower panel 200 overlaps the data line 171 to form the first capacitor C1, and the common electrode 270 together with the compensation electrode 280 forms the second capacitor C2.

A voltage having an opposite polarity to the data voltage applied to the data line 171 is applied to the compensation electrode 280 to compensate for coupling between the data line 171 and the common electrode 270 .

This will be described in more detail with reference to FIG. 12 .

Referring to FIG. 12, the data line 171 and the common electrode 270 overlap each other to form a first capacitor C1. Therefore, the common voltage Vcom of the common electrode 270 to which the predetermined voltage is applied may change the first value W1 by being coupled with the data voltage D applied to the data line 171 . In this case, a compensation voltage Ccps having an opposite polarity to the data voltage D applied to the data line 171 is applied from the compensation electrode 280 .

The compensation electrode 280 and the common electrode 270 overlap each other to form the second capacitor C2. Therefore, the common voltage Vcom of the common electrode 270 can be changed by the second value W2 by being coupled with the compensation electrode 280 . That is, by applying a voltage opposite in polarity to the data voltage D to the compensation electrode 280, the first value change W1 of the common voltage Vcom due to the data voltage D is compensated by coupling with the compensation voltage Ccps, thereby uniformly maintaining the common voltage Vcom value of .

Many features of the liquid crystal displays according to the exemplary embodiments described with reference to FIGS. 1 to 4, 5A to 5C, 6, 7, 8, 9 and 10 may be applied to the liquid crystal displays according to the exemplary embodiments.

In addition to FIGS. 1 to 4 , a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure will be described with reference to FIGS. 13 to 22 . 13 is a layout view illustrating a part of a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure, FIG. 14 is a cross-sectional view of the liquid crystal display taken along line XIV-XIV of FIG. 13 , and FIG. 15 is a view along XV of FIG. 13 - A cross-sectional view of the liquid crystal display taken along the line XV, and FIG. 16 is a cross-sectional view of the liquid crystal display taken along the line XVI-XVI of FIG. 13 . 17 , 20 and 23 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line II-II of FIG. 1 . 18 , 21 and 24 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line III-III of FIG. 1 . 19 , 22 and 25 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line IV-IV of FIG. 1 .

First, referring to FIGS. 13 to 16 , the gate line 121 including the gate electrode 124 and the gate pad portion 129 is formed on the first insulating substrate 110 , and the gate insulating layer 140 is formed on the gate line 121 . A semiconductor 154 , ohmic contacts 163 and 165 , and a data conductor including a data line 171 , a source electrode 173 , a data pad portion 179 and a drain electrode 175 are formed on the gate insulating layer 140 . The first passivation layer 180 x and the organic layer 80 are formed on the data line 171 and the drain electrode 175 . A first contact hole 186, a second contact hole 187 and a third contact hole 185 are formed through the first passivation layer 180x and the organic layer 80 to expose the gate pad portion 129, the data pad portion 179 and the drain electrode, respectively. In addition, the first contact assistant 96 is formed on the gate pad portion 129 exposed through the first contact hole 186, the second contact assistant 97 is formed on the data pad portion 179 exposed through the second contact hole 187, and the pixel electrode 191 It is formed to be connected to the drain electrode 175 through the first contact hole 185 . In this case, the organic layer 80 may be a color filter and may be formed together with a light blocking member. The first thickness H1 of the organic layer 80 disposed in the display area including the plurality of pixels may be greater than the second thickness H2 of the organic layer 80 disposed in the peripheral area including the gate pad portion 129 and the data Pad portion 179 .

Thereafter, as shown in FIGS. 1 to 4 , the second passivation layer 180y and the common electrode 270 are formed on the pixel electrode 191 . This will be described with reference to FIGS. 17 to 25 .

First, as shown in FIGS. 17 to 19 , the first layer 10 including silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the pixel electrode 191 , the first contact assistant 96 and the second contact assistant 97 , A second layer 20 comprising a transparent conductor is deposited on the first layer 10 . The first photosensitive film 400 is deposited on the second layer 20 .

Then, as shown in FIGS. 20 to 22, the first photosensitive film 400 is exposed and developed using a photomask to form a first photosensitive film pattern 400a. In this case, the first photosensitive film pattern 400 a is not formed around the gate pad portion 129 and the data pad portion 179 .

Thereafter, referring to FIGS. 23 to 25 , the second layer 20 and the first layer 10 are sequentially etched by using the first photosensitive film pattern 400 a to form a common electrode including a plurality of first cutouts 271 and a plurality of second cutouts 181 270 and the second passivation layer 180y. In this case, since the first photosensitive film pattern 400a is not formed around the gate pad portion 129 and the data pad portion 179, the common electrode 270 and the second passivation layer 180y are not formed at the gate pad portion 129 and the data pad portion 179 around.

Thus, after the lower panel 100 is formed, the liquid crystal display is completed by forming the upper panel 200 and injecting the liquid crystal layer 3 between the two panels 100 and 200, as shown in FIGS. 1 to 4 .

A method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure will now be described with reference to FIGS. 26 to 55 . 26 , 31 , 36 , 41 , 46 and 51 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along the line XIV-XIV of FIG. 13 . Sectional view. FIGS. 27 , 32 , 37 , 42 , 47 and 52 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, taken along the line XV-XV of FIG. 13 . Sectional view. 28 , 33 , 38 , 43 , 48 and 53 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along the line XVI-XVI of FIG. 13 . Sectional view. 29 , 34 , 39 , 44 , 49 and 54 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line X-X of FIG. 9 . 30 , 35 , 40 , 45 , 50 and 55 are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, which are cross-sectional views of the liquid crystal display taken along line VIII-VIII of FIG. 7 . Sectional view.

First, referring to FIGS. 26 to 30 , the gate line 121 including the gate electrode 124 and the gate pad portion 129 is formed on the first insulating substrate 110 , and the gate insulating layer 140 is formed on the gate line 121 . A semiconductor 154 , ohmic contacts 163 and 165 , and a data conductor including a data line 171 , a source electrode 173 , a data pad portion 179 and a drain electrode 175 are formed on the gate insulating layer 140 . The first passivation layer 180 x and the organic layer 80 are formed on the data line 171 and the drain electrode 175 . A first contact hole 186, a second contact hole 187 and a third contact hole 185 are formed through the first passivation layer 180x and the organic layer 80 to expose the gate pad portion 129, the data pad portion 179 and the drain electrode, respectively. In addition, the first contact assistant 96 is formed on the gate pad portion 129 exposed through the first contact hole 186, the second contact assistant 97 is formed on the data pad portion 179 exposed through the second contact hole 187, and the pixel electrode 191 It is formed to be connected to the drain electrode 175 through the third contact hole 185 . In this case, the organic layer 80 may be a color filter and may be formed together with a light blocking member. The first thickness H1 of the organic layer 80 disposed in the display area including the plurality of pixels may be greater than the second thickness H2 of the organic layer 80 disposed in the peripheral area including the gate pad portion 129 or the data Pad portion 179 .

Then, the first layer 10 including silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the pixel electrode 191 , the first contact assistant 96 and the second contact assistant 97 , the second layer 20 including the transparent conductor Deposited on the first layer 10 , a third layer 30 comprising a low resistance metal is deposited on the second layer 20 . The second photosensitive film 500 is deposited on the third layer 30 .

As shown in FIGS. 31 to 35, the second photosensitive film 500 is exposed to light and developed by using a photomask including a translucent region, a light transmitting region and a light blocking region to form second photosensitive film patterns 500a and 500b. The second photosensitive film patterns 500a and 500b have thicknesses that vary according to positions. In this case, the second photosensitive film patterns 500 a and 500 b are not formed around the gate pad portion 129 and the data pad portion 179 .

Various methods can be used to vary the thickness of the photosensitive film according to the position. For example, a method of locating the translucent, light-transmitting, and light-blocking regions in a photomask includes providing a thin film, a lattice pattern, or a slit pattern with an intermediate transmittance and an intermediate thickness in the translucent region. For slit patterns, the distance between slits or slit width may be less than the resolution of the exposure device used in the lithography process. Another example includes a method utilizing a photosensitive film capable of reflow. That is, the reflowable photosensitive film is formed of an exposure mask having only a light transmitting region and a light blocking region, and the photosensitive film is reflowed into the region from which the photosensitive film was removed to form a thin portion. In this way, the manufacturing method is simplified by eliminating one lithography process.

Then, as shown in FIGS. 36 to 40 , the third layer 30 , the second layer 20 and the first layer 10 are simultaneously or sequentially etched using the second photosensitive film patterns 500 a and 500 b as etching masks to form a first insulating layer pattern 11. The second conductive layer pattern 21 and the third conductive layer pattern 31. In this case, since the second photosensitive film patterns 500 a and 500 b are not formed around the gate pad portion 129 and the data pad portion 179 , the first to third layers 10 to 3 around the gate pad portion 129 and the data pad portion 179 30 are removed.

As shown in FIGS. 41 to 45, the heights and thicknesses of the second photosensitive film patterns 500a and 500b are reduced by a method such as ashing, while the thin photosensitive film pattern 500a is removed to form a third photosensitive film pattern 500c.

46 to 50, after the third photosensitive film pattern 500c is formed, the first insulating substrate 110 is annealed. The ITO or IZO forming the second conductive layer pattern 21 is crystallized by annealing. In the method of manufacturing the liquid crystal display according to the illustrated exemplary embodiment, after the third photosensitive film pattern 500c is formed, the first insulating substrate 110 may be annealed. However, according to the method of manufacturing a liquid crystal display according to another exemplary embodiment of the present disclosure, after the first insulating layer pattern 11, the second conductive layer pattern 21 and the third conductive layer pattern 31 are formed and before the third photosensitive film pattern 500c is formed , the first insulating substrate 110 may be annealed to crystallize the ITO or IZO forming the second conductive layer pattern 21 .

Then, as shown in FIGS. 51 to 55, the third conductive layer pattern 31 is etched using the third photosensitive film pattern 500c as an etching mask to complete the second passivation layer 180y, the common electrode 270, the lower connection portion 27p of the connection portion 27 , the upper connecting portion 27q of the connecting portion 27 and the common electrode line 28 .

Thereafter, the third photosensitive film pattern 500c is removed to form the lower panel 100 .

Thus, after forming the lower panel 100 , the liquid crystal display is completed by forming the upper panel 200 and injecting the liquid crystal layer 3 between the two panels 100 and 200 , as shown in FIGS. 7 , 8 , 9 and 10 .

As described above, according to the method of manufacturing a liquid crystal display according to an exemplary embodiment of the present disclosure, the common electrode 270 and the second passivation layer 180y are formed simultaneously, and the common voltage line 28 and the connection portion 27 including the lower connection portion 27p and the upper connection portion 27q are simultaneously formed form. As a result, the manufacturing cost of the liquid crystal display can be reduced while preventing signal delay of the common voltage applied to the common electrode.

While this disclosure has been described in connection with what are presently considered to be actual exemplary embodiments, it is to be understood that this disclosure is not limited to the disclosed embodiments, but on the contrary, is intended to cover the spirit and scope of the claims included in the claims and their equivalents. Various modifications and equivalent arrangements within the range.

Claims (10)

1. A liquid crystal display comprising: a plurality of pixel electrodes and a plurality of common electrodes are disposed on the first substrate and overlap each other, and the passivation layer is interposed between the pixel electrodes and the common electrodes, a plurality of gate lines and a plurality of data lines, arranged on the first substrate, a second substrate, facing the first substrate, and a compensation electrode, disposed on the outer surface of the second substrate, wherein the common electrode has a plurality of first notches, the passivation layer has a plurality of second cuts, and the first cutout and the second cutout have substantially the same planar shape, wherein the edge of the first cut of the common electrode overlaps the edge of the second cut of the passivation layer, A voltage having an opposite polarity to the data voltage applied to the data line is applied to the compensation electrode to compensate for coupling between the data line and the common electrode. 2. The liquid crystal display of claim 1, further comprising: A common voltage applying unit disposed in a peripheral area around a display area including the plurality of pixel electrodes, and A connection portion is provided between the common voltage applying unit and the common electrode, wherein the connection portion is formed of the same layer as the common electrode. 3. The liquid crystal display of claim 2, wherein the connection part includes a lower connection part formed of the same layer as the common electrode, and An upper connection portion is provided on the lower connection portion and includes a low resistance metal. 4. The liquid crystal display of claim 3, further comprising: A common voltage line is provided on a part of the common electrodes, wherein the common voltage line is formed of the same layer as the upper connection portion. 5. The liquid crystal display of claim 4, wherein: The common voltage lines extend parallel to the gate lines. 6. The liquid crystal display of claim 4, wherein: The common voltage line is disposed between two adjacent data lines and extends parallel to the data lines. 7. The liquid crystal display of claim 1, wherein the first substrate comprises: insulating substrate; the plurality of gate lines and the plurality of data lines are disposed on the insulating substrate; a plurality of thin film transistors, respectively connected to the plurality of gate lines and the plurality of data lines; and An organic layer is disposed on the plurality of thin film transistors, and the plurality of pixel electrodes and common electrodes are disposed on the organic layer. 8. The liquid crystal display of claim 7, wherein: The organic layer is a color filter. 9. The liquid crystal display of claim 8, further comprising: A light blocking member is disposed on the first substrate. 10. The liquid crystal display of claim 1, wherein the common electrode on the first substrate overlaps the data line to form a first capacitor, and the compensation electrode on the second substrate and The common electrodes together form a second capacitor.

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