CN104038220A - 16-bit pipelined analog-digital converter - Google Patents

Abstract

The present invention provides a 16-bit pipelined analog-to-digital converter, comprising: a sequentially connected pre-sample and hold circuit, a first stage, a second stage, a third stage, a fourth stage multi-digit digital-to-analog converter and a fifth stage flash analog-to-digital converters, and digital digital-to-analog converters connected to the first, second, third, and fourth-stage multi-digit digital-to-analog converters and the fifth-stage flash analog-to-digital converters respectively correction circuit. The use of digital correction technology in the analog-to-digital converter enables the analog-to-digital converter to tolerate a certain offset of the comparator without affecting the performance of the analog-to-digital converter. In addition, the sub-DAC error and inter-stage gain error in the MDAC caused by capacitance mismatch are eliminated through foreground analog calibration. The solution of the invention can effectively shorten the calibration time.

Description

A 16-bit Pipelined Analog-to-Digital Converter

technical field

The invention relates to the technical field of mixed-signal integrated circuits, in particular to a 16-bit 125MSPSCMOS pipeline analog-to-digital converter.

Background technique

With the development of modern communication technology and digital signal processing technology, the entire communication system has higher requirements on the speed and precision of the interface circuit between analog signal and digital signal, so it is necessary to design a high-speed and high-precision analog-to-digital converter.

It is difficult to implement in the pipelined analog-to-digital converter whose precision is higher than 10 bits in the existing structure, because it is limited by the matching of the capacitance on the chip and the threshold offset of the comparator. Analog-to-digital converters require corresponding calibration techniques and correction techniques.

In the process of implementing the present invention, it is found that the following problems exist in the prior art: most digital calibration techniques require a long calibration time to implement.

Contents of the invention

The technical problem to be solved by the present invention is to provide a 16-bit 125MSPS CMOS pipeline analog-to-digital converter, which can effectively shorten the calibration time.

In order to solve the above technical problems, an embodiment of the present invention provides a 16-bit pipelined analog-to-digital converter, including:

The pre-sampling and holding circuit, the first stage, the second stage, the third stage, the fourth stage multi-digit digital-to-analog converter and the fifth-stage flash analog-to-digital converter connected in sequence, and the first stage and the first stage respectively , the digital correction circuit connected to the second stage, the third stage, the fourth stage multi-digit digital-to-analog converter and the fifth-stage flash analog-to-digital converter; wherein,

The sample-and-hold circuit samples the input signal, and outputs the input signal to the first-stage multi-digit digital-to-analog converter;

The first-stage multi-digit digital-to-analog converter samples the output of the sample-and-hold circuit, amplifies and outputs the quantized residual difference, and completes the encoding of the output value of the output controllable comparator at this stage;

The second-stage multi-digit digital-to-analog converter samples the output of the first-stage multi-digit digital-to-analog converter, amplifies and outputs the quantized residual difference, and completes the encoding of the output value of the current-stage output controllable comparator;

The third-stage multi-digit digital-to-analog converter samples the output of the second-stage multi-digit digital-to-analog converter, and at the same time completes the encoding of the output value of the output controllable comparator at this stage;

The fourth-stage multi-digit digital-to-analog converter samples the output of the third-stage multi-digit digital-to-analog converter, and at the same time completes the coding of the output value of the output controllable comparator at this stage;

The fifth-stage flash analog-to-digital converter samples the output of the fourth-stage multi-digit digital-to-analog converter, and at the same time completes the encoding of the output value of the output controllable comparator of this stage;

The timing of the third-stage multi-digit digital-to-analog converter and the fifth-stage flash analog-to-digital converter is the same as that of the first-stage multi-digit digital-to-analog converter;

The timing of the fourth-stage multi-digit DAC is the same as that of the second-stage multi-digit DAC.

Wherein, the pre-sampling and holding circuit includes: a first operational amplifier (Ash1), a first, a second, a third and a fourth bootstrap switch, a transmission gate and a capacitor;

The positive and negative input terminals of the first operational amplifier are short-circuited together by an NMOS transistor (M7), and an input voltage (Vin_com) is added to the first operational amplifier through an NMOS transistor (M5) and an NMOS transistor (M6). positive and negative input terminals of an operational amplifier;

The positive and negative output ends of the first operational amplifier are short-circuited together by an NMOS transistor (M8), which is used to reset the output of the first operational amplifier;

The first bootstrap switch (S1) and the second bootstrap switch (S2) output corresponding control signals to turn on an NMOS transistor (M1) and an NMOS transistor (M2) which function as switches, so that the nineteenth capacitor (C19) , The seventeenth capacitor (C17) is connected to the positive input signal, the twentieth capacitor (C20) and the eighteenth capacitor (C18) are connected to the negative input signal;

The transmission gate transmits the signal at the input terminal to the output terminal or disconnects it from the output terminal according to the high and low levels of the control signal;

The first bootstrap switch and the second bootstrap switch are reset, and the output signal is low level, so that the source and drain of an NMOS transistor (M1) and an NMOS transistor (M2) are disconnected;

The third bootstrap switch (S3) and the fourth bootstrap switch (S4) output effective control signals, so that an NMOS transistor (M3) and another NMOS transistor (M4) that function as switches are turned on, and the The lower plates of the seventeenth capacitor (C17), the nineteenth capacitor (C19), the eighteenth capacitor (C18), and the twentieth capacitor (C20) are respectively connected to the first operational amplifier The negative and positive output terminals are connected;

When the first operational amplifier is working normally, the sampled signal is held and output to the input end of the multi-digit digital-to-analog converter at the first stage of the pipeline.

Wherein, the first-stage multi-digit digital-to-analog converter of the pipeline includes: a second operational amplifier (A1), 10 transmission gates, 64 switch arrays, capacitors, and 32 output controllable comparators;

Wherein, the positive and negative input ends of the second operational amplifier (A1) are short-circuited together through an NMOS transistor (M62), and the second operational amplifier A1 is connected through an NMOS transistor (M60) and an NMOS transistor (M61). The input terminal of the input common mode reference level Vcom1 is added; the output terminal of the second operational amplifier (A1) is short-circuited together by an NMOS transistor (M77), which acts on the output of the second operational amplifier (A1) With the role of reset;

The 32 output controllable comparators realize the sampling of the input signal;

Under the control of the control signal, the transmission gate grounds one end of the capacitor connected to the transmission gate or connects to the input common-mode reference level;

The output of the switch array is determined by the output of the output controllable comparator.

Wherein, the first-stage multi-digit digital-to-analog converter of the pipeline also includes:

The encoding circuit is used for encoding the output of the output controllable comparator.

Wherein, the second-stage multi-digit digital-to-analog converter of the pipeline includes: a third operational amplifier (A2), 8 transmission gates, 32 switch arrays, capacitors, and 16 output controllable comparators;

The positive and negative input ends of the third operational amplifier (A2) are short-circuited together through an NMOS transistor (M86), and the input common-mode reference voltage (Vcom2) is added through an NMOS transistor (M84) and an NMOS transistor (M85) , the positive and negative output terminals are also shorted together through an NMOS transistor (M106);

The 16 output controllable comparators realize the sampling of the input signal;

Under the control of the control signal, the eight transmission gates ground one end of the capacitor connected to the transmission gates or connect to the input common mode reference level;

The output of the switch array is determined by the output of the output controllable comparator.

Wherein, the second-stage multi-digit digital-to-analog converter of the pipeline also includes:

16 positive calibration error storage circuits for storing errors caused by capacitance mismatch associated with the 16 output controllable comparators in the first stage multi-digit digital-to-analog converter;

Sixteen negative calibration error storage circuits are used to store errors caused by capacitance mismatches associated with the other 16 output controllable comparators in the first-stage multi-digit digital-to-analog converter.

Wherein, the third-stage multi-digit digital-to-analog converter of the pipeline includes: a third operational amplifier (A3), 18 switch arrays, capacitors, and 17 output controllable comparators;

The positive and negative input terminals of the third operational amplifier (A3) are short-circuited together by an NMOS transistor (M124), and the input common-mode reference voltage Vcom3 is added through an NMOS transistor (M122) and an NMOS transistor (M123). The negative output terminals are shorted together through an NMOS transistor (M128);

The 17 output controllable comparators realize the sampling of the input signal;

The output of the switch array is determined by the output of the output controllable comparator.

Wherein, the third-stage multi-digit digital-to-analog converter of the pipeline also includes:

nine positive calibration error storage circuits for storing errors caused by capacitance mismatches associated with the nine output controllable comparators in the second stage multi-digit digital-to-analog converter;

Eight negative calibration error storage circuits for storing errors caused by capacitance mismatches associated with the other eight output controllable comparators in the second stage of the multi-digit digital-to-analog converter.

Wherein, the third-stage multi-digit digital-to-analog converter of the pipeline further includes: an encoding circuit (E3), used for encoding the output of the output controllable comparator.

Wherein, the fourth-stage multi-digit digital-to-analog converter of the pipeline includes: a fourth operational amplifier (A4), 20 switch arrays, capacitors, and 16 output controllable comparators;

Wherein, the positive and negative input ends of the fourth operational amplifier (A4) are short-circuited together by an NMOS transistor (M144), and the input common-mode reference voltage Vcom4 is added through an NMOS transistor (M142) and an NMOS transistor (M143). , the positive and negative output terminals are shorted together through an NMOS transistor (M152);

The 16 output controllable comparators realize the sampling of the input signal;

The output of the switch array is determined by the output of the output controllable comparator.

Wherein, the fourth-stage multi-digit digital-to-analog converter of the pipeline further includes: an encoding circuit 4 for encoding the output of the output controllable comparator.

Wherein, the fifth-level flash analog-to-digital converter includes:

7 comparators for sampling the input signal.

Wherein, the fifth-level flash analog-to-digital converter further includes: an encoding circuit E5, configured to encode the output of the comparator.

Wherein, the positive calibration error storage circuit includes:

2 CMOS transmission gates, 4 inverters, a NAND gate, an OR gate, a current regulation circuit, 2 resistors, and 2 NMOS transistors; among them,

The two CMOS transmission gates are connected sequentially, the first inverter (I1) of the four inverters is connected to the first transmission gate of the two CMOS transmission gates, and the second inverter (I2) is connected to the first transmission gate of the two CMOS transmission gates. Two transmission gates are connected, the first inverter is connected with the second inverter; the first inverter is also connected with the NAND gate, the NAND gate is connected with the NOR gate, and the NAND gate is connected The OR gate is connected to the third inverter, the third inverter is connected to the fourth inverter, the third inverter is connected to the current regulation circuit through the first MOS tube, and the current regulation circuit is connected to the current regulation circuit through a The resistor is grounded, the fourth inverter is grounded through a MOS transistor and the resistor, and the MOS transistor connected to the fourth inverter and the MOS transistor connected to the third inverter are connected to each other.

The beneficial effects of above-mentioned technical scheme of the present invention are as follows:

In the above solution, using analog technology for calibration can not only improve the accuracy of the analog-to-digital converter, but also effectively shorten the calibration time. At the same time, the inter-stage gain of the first-stage MDAC of the pipeline is compressed by 4 times, the quantization range of the second-stage MDAC, the third-stage MDAC, the fourth-stage MDAC, and the flash ADC of the fifth-stage pipeline are doubled. Correction is performed to eliminate the influence of the threshold offset of the comparator in each stage of the pipeline MDAC.

Description of drawings

Fig. 1 is the functional structural block diagram of 16 125MSPS CMOS pipeline type analog-to-digital converters in the embodiment of the present invention;

Fig. 2 is the schematic diagram of the pre-sample and hold circuit in Fig. 1;

Fig. 3 is a schematic diagram of the first stage MDAC of the pipeline in Fig. 1;

Fig. 4 is the schematic diagram of the second-stage MDAC of the pipeline in Fig. 1;

Fig. 5 is a schematic diagram of the third stage MDAC of the pipeline in Fig. 1;

Fig. 6 is a schematic diagram of the fourth stage MDAC of the pipeline in Fig. 1;

FIG. 7 is a schematic diagram of the fifth-stage flash ADC of the pipeline in FIG. 1;

Fig. 8 is a schematic diagram of the digital correction circuit in Fig. 1;

FIG. 9 is a schematic diagram of the positive calibration error storage circuit in FIG. 4 .

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

At first, the technical term involved in the present invention is explained:

PMOS: P-channel metal oxide semiconductor FET, P-channel metal oxide semiconductor field effect transistor;

NMOS: N-channel metal oxide semiconductor FET, N-channel metal oxide semiconductor field effect transistor;

CMOS: complementary metal oxide semiconductor FET, complementary metal oxide semiconductor field effect transistor;

ADC: analog-digital converter, analog-to-digital converter;

DAC: digital-analog converter, digital-to-analog converter;

MDAC: Multi-bits digital-analog converter, multi-digit digital analog converter, specifically refers to each stage circuit of the pipelined analog-to-digital converter in the present invention.

Referring to Fig. 1, it is a functional structural block diagram of a 16-bit 125MSPS CMOS pipelined analog-to-digital converter in an embodiment of the present invention. As can be seen from the figure, the pipelined analog-to-digital converter includes sequentially connected front-end sample-and-hold circuits, pipeline first stage multi-digit digital-to-analog converter (MDAC), pipeline second-stage multi-digit digital-to-analog converter (MDAC), pipeline third-stage multi-digit digital-to-analog converter (MDAC), pipeline fourth-stage multi-digit Analog-to-analog converter (MDAC), pipeline fifth-stage flash ADC and digital correction circuit. in:

The sample-and-hold circuit samples the input signal, and outputs the input signal to the first-stage multi-digit digital-to-analog converter;

The first-stage multi-digit digital-to-analog converter samples the output of the sample-and-hold circuit, amplifies and outputs the quantized residual difference, and completes the encoding of the output value of the output controllable comparator at this stage;

The second-stage multi-digit digital-to-analog converter samples the output of the first-stage multi-digit digital-to-analog converter, amplifies and outputs the quantized residual difference, and completes the encoding of the output value of the current-stage output controllable comparator;

The third-stage multi-digit digital-to-analog converter samples the output of the second-stage multi-digit digital-to-analog converter, and at the same time completes the encoding of the output value of the output controllable comparator at this stage;

The fourth-stage multi-digit digital-to-analog converter samples the output of the third-stage multi-digit digital-to-analog converter, and at the same time completes the coding of the output value of the output controllable comparator at this stage;

The fifth-stage flash analog-to-digital converter samples the output of the fourth-stage multi-digit digital-to-analog converter, and at the same time completes the encoding of the output value of the output controllable comparator of this stage;

The timing of the third-stage multi-digit digital-to-analog converter and the fifth-stage flash analog-to-digital converter is the same as that of the first-stage multi-digit digital-to-analog converter;

The timing of the fourth-stage multi-digit DAC is the same as that of the second-stage multi-digit DAC.

Each part of the above-mentioned circuit will be described in detail below in conjunction with the specific drawings:

The pre-sample-and-hold circuit adopts a fully differential charge-reversal circuit structure. The fully-differential structure is conducive to suppressing the influence of power supply disturbances on circuit performance. The feedback coefficient of the charge-reversal type is close to 1, which affects the bandwidth of the operational amplifier in the sample-and-hold circuit. The requirements will be reduced, and the positive feedback realized by capacitor C17 and capacitor C18 is used to adjust the establishment accuracy of the sample-and-hold circuit, and the random signal generated by the pseudo-random number generator is added to the output terminal of the sample-and-hold circuit, so that when the input signal is relatively The entire analog-to-digital converter has good linearity, and the added random signal will be subtracted in the digital correction circuit.

Referring to FIG. 2 , it can be seen from the figure that when the clock signal is at a low level, the clock signals clk_n1 and clk_n2 are at a high level. The positive and negative input terminals of the operational amplifier Ash1 in the sample and hold circuit are short-circuited together by the NMOS transistor M7, and the voltage Vin_com is added to the positive and negative input terminals of the operational amplifier Ash1 in the sample and hold circuit through the NMOS transistor M5 and the NMOS transistor M6, The NMOS transistor M8 short-circuits the positive and negative output terminals of the operational amplifier Ash1 in the sample-and-hold circuit together, and plays the role of resetting the output of the operational amplifier Ash1 in the sample-and-hold circuit. At the same time, the bootstrap switch S1 and the bootstrap switch S2 output corresponding control signals to turn on the NMOS transistor M1 and the NMOS transistor M2, which function as switches, so that the capacitor C19, capacitor C17, capacitor C20 and capacitor C18 are connected to the positive input signal and the negative input signal respectively. Connected, that is, to complete the sampling of the input signal. Both ends of the capacitor C15 and the capacitor C16 are respectively connected to the fixed voltage Vref and the fixed voltage Vin_com through the NMOS transistor M5 , the NMOS transistor M6 , the NMOS transistor M9 and the transistor M10 . At this time, the control signals dith1_p, dith2_p, dith3_p, dith4_p, dith5_p, dith6_p are all low level, and the control signals dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n are all high level, so the CMOS transmission gate T1, CMOS Transmission gate T3, CMOS transmission gate T5, CMOS transmission gate T7, CMOS transmission gate T9, CMOS transmission gate T11, CMOS transmission gate T14, CMOS transmission gate T16, CMOS transmission gate T18, CMOS transmission gate T20 and CMOS transmission gate T22 work normally , CMOS transmission gate T2, CMOS transmission gate T4, CMOS transmission gate T6, CMOS transmission gate T8, CMOS transmission gate T10, CMOS transmission gate T12, CMOS transmission gate T13, CMOS transmission gate T15, CMOS transmission gate T17, CMOS transmission gate T19 The input terminal and the output terminal of the CMOS transmission gate T21 are disconnected. At this time, one end of the capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, and capacitor C7 is connected to a fixed level Vref, and the other end is also connected to a fixed level. Vref; One end of capacitor C8, capacitor C9, capacitor C10, capacitor C11, capacitor C12, and capacitor C13 is connected to a fixed level Vref_dith, the other end is connected to a level Vref, one end of capacitor C1 and capacitor C14 is grounded, and the other end is connected to a fixed voltage Level Vref. When the clock level is high level, the clock signals clk_n1 and clk_n2 are low level at this time. At this time, the bootstrap switch S1 and the bootstrap switch S2 are reset, and the output signal is low level, so that the source and drain of the NMOS transistor M1 and the NMOS transistor M2 are disconnected, and the bootstrap switch S3 and the bootstrap switch S4 output effective control The signal makes the NMOS transistor M3 and the NMOS transistor M4 which function as switches turn on, and connects the lower plates of the capacitors C17, C19, C18, and C20 to the negative and positive output terminals of the operational amplifier Ash1 in the sample-and-hold circuit respectively. At this time, the operational amplifier Ash1 in the sample-and-hold circuit works normally, and holds and outputs the sampled signal to the input end of the first-stage MDAC of the pipeline. According to the size of the input signal, when there is no need to add a random signal to the input port, the control signals dith1_p, dith2_p, dith3_p, dith4_p, dith5_p, dith6_p are still at low level, and the control signals dith1_n, dith2_n, dith3_n, dith4_n, dith5_n , dith6_n are still high. When a random signal needs to be added to the input port, since the control signals dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n are the opposite of the control signals dith1_p, dith2_p, dith3_p, dith4_p, dith5_p, dith6_p respectively. At this time, the high and low levels of the control signals dith1_p, dith2_p, dith3_p, dith4_p, dith5_p, and dith6_p change randomly, so the high and low levels of the corresponding control signals dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, and dith6_n also change randomly. The CMOS transmission gate controlled by the signal will also be turned on or off correspondingly to realize the charging of the capacitor C2 to the capacitor C12, thereby adding a randomly changing signal to the output signal of the sample and hold circuit. In the digital correction circuit, according to the high and low levels of the control signals dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n, the size of the random signal added in the sample and hold circuit is judged and subtracted from the output result of the conversion.

See Figure 3. The first-stage MDAC of the pipeline adopts a fully differential charge-reversal circuit structure. Under normal operating conditions, the output of the sample-and-hold circuit is quantized to five bits, and a six-digit digital code is output, and the quantized remaining The difference is magnified by 8 times, compared to the theoretical magnification of 32 times, the actual magnification is compressed by 1/4. The selection of compression 1/4 here is mainly based on the following considerations. First, due to the offset of the threshold of the comparator, the residual difference generated by this stage will be magnified by 32 times and then exceed the quantization range of the lower stage, which will introduce nonlinear errors. Therefore, the amplification factor should be compressed accordingly to eliminate this effect; secondly, considering the limitation of the output swing range of the operational amplifier in MDAC, choose to compress 1/4 instead of 1/2; thirdly, consider According to the accuracy requirements of the comparator, the larger the compression factor, the larger the quantization range of the lower-level MDAC will be reduced, so the accuracy of the lower-level comparator for quantization will be higher, so here we choose to compress 1/4, and It is not 1/8. In the case of three-bit quantization of the lower level, the accuracy requirement of the lower level for the comparator is the same as that of the current level to achieve five-digit precision; the corresponding transfer function expression of the current level:

$\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Vinp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vinn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 31</span>}\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span>& \mathrm{<span\; class="notranslate">\; Vinp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vinn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&le;</span>\frac{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 15</span>}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\\ \mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Vinp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vinn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span>& \frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}<span\; class="notranslate">\; <</span>\mathrm{<span\; class="notranslate">\; Vinp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vinn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&le;</span>\frac{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\\ \mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Vinp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vinn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 33</span>}\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span>& \mathrm{<span\; class="notranslate">\; Vinp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vinn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; <</span>\frac{\mathrm{<span\; class="notranslate">\; 16</span>}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\end{array}\right.$

Among them, Voutp1 is the positive output value of the current stage, Voutn1 is the negative output value of the current stage, Vinp1 is the positive input value of the current stage, Vinn1 is the negative input value of the current stage, and Vref is the reference voltage value, which is also the quantization range of the ADC. i ₁ is a corresponding integer, and its value range is -14≤i ₁ ≤16.

At this time, the output of all comparators is still 0, and the size of the inter-stage gain is judged by comparing the two output codes. When the inter-stage gain of the current stage is less than 8 times, the inter-stage gain can be increased through adjustment, and when the inter-stage gain of the current stage is greater than 8 times, the inter-stage gain of the current stage can be reduced through adjustment. What needs to be explained here is that the calibration of this stage is performed after the calibration of the subsequent stage is completed. After that, the sub-DAC is calibrated, and the output of the controllable comparator is controlled by the calibration control signal. See Figure 3 for a fixed input value. It can be seen from the figure that in normal operation, when the clock is high, the clock signal clk1_p , clk1_p1, clk1_p2 are high level, at this time the positive and negative input terminals of the operational amplifier A1 in MDAC are short-circuited together through the NMOS transistor M62, and the input terminal of the operational amplifier A1 is added through the NMOS transistor M60 and NMOS transistor M61 Common mode reference level Vcom1. The output terminals of the operational amplifier A1 in the MDAC are short-circuited together by the NMOS transistor M77, which resets the output of the operational amplifier A1 in the MDAC. At this time, the positive output and the negative output of the output controllable comparator Coc1 to the output controllable comparator Coc32 of this stage are all 1, and the inversion of the positive output and the inversion of the negative output are both 0, so the switch array Sr1 to In the switch array Sr64, the PMOS transistors connected to the reference voltage Vref and the NMOS transistors connected to the ground are in the off state, and only the NMOS transistors connected to the positive input signal and the negative input signal are turned on. In addition, at this time, the NMOS transistor M50, the NMOS transistor The M51, the NMOS transistor M54, the NMOS transistor M58 and the NMOS transistor M59 are turned on, so as to realize the sampling of the input signal by the capacitor C25 to the capacitor C93. At the same time, the output controllable comparator Coc1 to the output controllable comparator Coc32 also implement sampling of the input signal. In addition, the NMOS transistor M74 and the NMOS transistor M75 are turned on, and one end of the CMOS transmission gate T35 to the CMOS transmission gate T44 is connected to the input common mode reference level Vcom1. At this time, the control signals VCmdac1_gain1_p and VCmdac1_gain1_n will control the CMOS transmission gate T35, the CMOS transmission gate T44, NMOS transistor M74, and NMOS transistor M65 are turned on or off, thereby determining that one end of capacitor C94 and capacitor C103 is grounded or connected to the input common-mode reference level Vcom1 when the clock is high; the control signals VCmdac1_gain2_p and VCmdac1_gain2_n will control the CMOS The transmission gate T36, the CMOS transmission gate T43, the NMOS transistor M73 and the NMOS transistor M66 are turned on or off, thereby determining that one end of the capacitor C95 and the capacitor C102 is grounded or connected to the input common-mode reference level Vcom1 when the clock is at a high level; The signals VCmdac1_gain3_p and VCmdac1_gain3_n will control the CMOS transmission gate T37, the CMOS transmission gate T42, the NMOS transistor M72 and the NMOS transistor M67 to be turned on or off, thereby determining that one end of the capacitor C96 and the capacitor C101 is grounded or connected to the input common when the clock is at a high level. Modulus reference level Vcom1; control signals VCmdac1_gain4_p and VCmdac1_gain4_n will control the conduction or shutdown of CMOS transmission gate T38, CMOS transmission gate T41, NMOS transistor M71 and NMOS transistor M68, thereby determining the high voltage of capacitor C97 and capacitor C100 in the clock Normally, one end is grounded or connected to the input common-mode reference level Vcom1; the control signals VCmdac1_gain5_p and VCmdac1_gain5_n will control the on or off of the CMOS transmission gate T39, CMOS transmission gate T40, NMOS transistor M70 and NMOS transistor M69, thereby determining the capacitor C98 and the capacitor One end of C99 is grounded or connected to the input common mode reference level Vcom1 when the clock is at a high level. The encoding circuit E1 is in the reset state, and the output codes are all 0s. When the clock level is low, the clock signals clk1_p, clk1_p1, and clk1_p2 are low. At this time, the operational amplifier A1 in the MDAC works normally, the bootstrap switch S5 and the bootstrap switch S6 output effective control signals, and the NMOS transistor M63 and The NMOS transistor M64 is turned on, respectively connecting the lower plates of the capacitor C93 and the capacitor C25 to the negative and positive output terminals of the operational amplifier A1 in the MDAC. The sampling control signals Vsamp1 and Vsamn1, that is, the output terminals of the bootstrap switch S3 and the bootstrap switch S4 in the sample-and-hold circuit are at low level, so all the sampling switches are turned off. At this time, the outputs of the switch array Sr1 to the switch array Sr64 are determined by the output of the output controllable comparator Coc1 to the output controllable comparator Coc32 . The outputs of the output controllable comparator Coc1 to the output controllable comparator Coc32 are judged according to the comparison between the input signal and the threshold value. The comparator thresholds of the first-stage MDAC in the pipeline are 16/32 Vref, 15/32 Vref, 14/32 Vref, 13/32 Vref, 12/32 Vref, 11/32 Vref, 10/32 ·Vref, 9/32·Vref, 8/32·Vref, 7/32·Vref, 6/32·Vref, 5/32·Vref, 4/32·Vref, 3/32·Vref, 2/32·Vref , 1/32·Vref, 0/32·Vref, -1/32·Vref, -2/32·Vref, -3/32·Vref, -4/32·Vref, -5/32·Vref, -6 /32·Vref, -7/32·Vref, -8/32·Vref, -9/32·Vref, -10/32·Vref, -11/32·Vref, -12/32·Vref, -13/ 32·Vref, -14/32·Vref, -15/32·Vref. In addition, at this time, the PMOS transistor M55 , the PMOS transistor M56 and the PMOS transistor M57 are turned on. During normal operation, the control signal Vcorrect1 is always at a high level, the PMOS transistor M52 is turned off, the control signal Vnormal1 and clk1_p1 are inverted, and the NMOS transistor M53 is turned on. In this way, recharging of the capacitors C26 to C92 is realized. The total capacitance of the 35 capacitors from capacitor C25 to capacitor C59 is the same as the total capacitance of the 34 capacitors from C60 to capacitor C93, all of which are 64 unit capacitors C0_1, and the size of capacitor C25 and capacitor C93 are both 8 unit capacitors C0_1, the size of the capacitor C59 is 23 unit capacitors C0_1, the size of the capacitor C60 is 24 unit capacitors C0_1, and the size of the remaining capacitors are all unit capacitors C0_1. According to the principle of charge conservation, the first-stage MDAC of the pipeline realizes five-bit quantization of the input signal and amplifies the remaining difference by 8 times. The encoding circuit 1 encodes the output of the output controllable comparator. Since the output of the controllable comparator is a thermometer code, it needs to be converted into a binary code by the encoding circuit 1 . Firstly, use XOR logic to convert the thermometer code into a single code, and then use the OR gate to convert the single code into a binary code. The encoding result of the first-stage pipeline MDAC:

Vinp1-Vinn1=Vin1 D16 D15 D14 D13 D12 D11 Vin1>16/32Vref 1 0 0 0 0 0 16/32Vref>Vin1>15/32Vref 0 1 1 1 1 1 15/32Vref>Vin1>14/32Vref 0 1 1 1 1 0 14/32Vref>Vin1>13/32Vref 0 1 1 1 0 1 13/32Vref>Vin1>12/32Vref 0 1 1 1 0 0

12/32Vref>Vin1>11/32Vref 0 1 1 0 1 1 11/32Vref>Vin1>10/32Vref 0 1 1 0 1 0 10/32Vref>Vin1>9/32Vref 0 1 1 0 0 1 9/32Vref>Vin1>8/32Vref 0 1 1 0 0 0 8/32Vref>Vin1>7/32Vref 0 1 0 1 1 1 7/32Vref>Vin1>6/32Vref 0 1 0 1 1 0 6/32Vref>Vin1>5/32Vref 0 1 0 1 0 1 5/32Vref>Vin1>4/32Vref 0 1 0 1 0 0 4/32Vref>Vin1>3/32Vref 0 1 0 0 1 1 3/32Vref>Vin1>2/32Vref 0 1 0 0 1 0 2/32Vref>Vin1>1/32Vref 0 1 0 0 0 1 1/32Vref>Vin1>0/32Vref 0 1 0 0 0 0 0/32Vref>Vin1>-1/32Vref 0 0 1 1 1 1 -1/32Vref>Vin1>-2/32Vref 0 0 1 1 1 0 -2/32Vref>Vin1>-3/32Vref 0 0 1 1 0 1 -3/32Vref>Vin1>-4/32Vref 0 0 1 1 0 0 -4/32Vref>Vin1>-5/32Vref 0 0 1 0 1 1 -5/32Vref>Vin1>-6/32Vref 0 0 1 0 1 0 -6/32Vref>Vin1>-7/32Vref 0 0 1 0 0 1 -7/32Vref>Vin1>-8/32Vref 0 0 1 0 0 0 -8/32Vref>Vin1>-9/32Vref 0 0 0 1 1 1 -9/32Vref>Vin1>-10/32Vref 0 0 0 1 1 0 -10/32Vref>Vin1>-11/32Vref 0 0 0 1 0 1 -11/32Vref>Vin1>-12/32Vref 0 0 0 1 0 0 -12/32Vref>Vin1>-13/32Vref 0 0 0 0 1 1 -13/32Vref>Vin1>-14/32Vref 0 0 0 0 1 0 -14/32Vref>Vin1>-15/32Vref 0 0 0 0 0 1 -15/32Vref>Vin1 0 0 0 0 0 0

In the calibration mode, due to the mismatch of capacitance, this stage will introduce corresponding errors to affect the overall performance of the ADC, so corresponding calibration is required. During calibration, this stage is disconnected from the sample-and-hold circuit, and the sample-and-hold circuit does not To work, the input terminal of this stage introduces a fixed value, and at this time the control signal Vnormal1 is always low, the NMOS transistor M53 is turned off, the control signal Vcorrect1 is in phase with the clock signal clk1_p, and the PMOS transistor M52 is turned on. When calibrating the inter-stage gain, first connect the input to the reference level Vinp1-Vinn1=-33/64 Vref, then the outputs from the output controllable comparator Coc1 to the output controllable comparator Coc32 are all 0, and a corresponding Output coding, then connect the input to the reference level Vinp1-Vinn1=-31/64 Vref to get another corresponding output coding, if the inter-stage gain of this stage is 8 times, the difference between the output codes before and after Should be -1/4·Vref. When the difference between the front and rear codes deviates from this value, the value of the inter-stage gain increase and decrease control signal VCmdac1_gain1_n to the inter-stage gain increase and decrease control signal VCmdac1_gain5_n can be adjusted to realize the increase and decrease adjustment of the inter-stage gain. The inter-stage gain increase and decrease control signal VCmdac1_gain1_p It is the inverse of the interstage gain increase and decrease control signal VCmdac1_gain1_n. The increase and decrease control signal VCmdac1_gain_n of the inter-stage gain is at a high level, and the CMOS transmission gate T46 and the CMOS transmission gate T47 are turned on, so that the negative feedback capacitance is increased to realize the reduction of the inter-stage gain; the increase and decrease control signal VCmdac1_gain_n of the inter-stage gain is When the level is low, the CMOS transmission gate T45 and the CMOS transmission gate T48 are turned on, and the corresponding positive feedback is added to realize the increase of the inter-stage gain. The inter-stage gain control signals VCmdac1_gain1_n, VCmdac1_gain2_n, VCmdac1_gain3_n, VCmdac1_gain4_n, VCmdac1_gain5_n can be adjusted to realize the change amount of the inter-stage gain.级间增益的小控制信号VCmdac1_gain1_p、VCmdac1_gain2_p、VCmdac1_gain3_p、VCmdac1_gain4_p、VCmdac1_gain5_p分别为级间增益大小控制信号VCmdac1_gain1_n、VCmdac1_gain2_n、VCmdac1_gain3_n、VCmdac1_gain4_n、VCmdac1_gain5_n的反，级间增益大小控制信号VCmdac1_gain1_n为高电平时，不影响The size of the inter-stage gain, if the inter-stage gain control signal VCmdac1_gain1_n is at low level, the corresponding inter-stage gain becomes (C60+C61+...+C93)/(C93±C94). When the inter-stage gain control signal VCmdac1_gain2_n is at a high level, it does not affect the inter-stage gain. If the inter-stage gain control signal VCmdac1_gain2_n is at a low level, the corresponding inter-stage gain becomes (C60+C61+…+C93)/ (C93±C95). When the inter-stage gain control signal VCmdac1_gain3_n is at a high level, it does not affect the inter-stage gain. If the inter-stage gain control signal VCmdac1_gain3_n is at a low level, the corresponding inter-stage gain becomes (C60+C61+…+C93) /(C93±C96). When the inter-stage gain control signal VCmdac1_gain4_n is at a high level, it does not affect the inter-stage gain. If the inter-stage gain control signal VCmdac1_gain4_n is at a low level, the corresponding inter-stage gain becomes (C60+C61+…+C93)/ (C93±C97). When the inter-stage gain control signal VCmdac1_gain5_n is at a high level, it does not affect the inter-stage gain. If the inter-stage gain control signal VCmdac1_gain5_n is at a low level, the corresponding inter-stage gain becomes (C60+C61+…+C93)/ (C93±C98). Calibration of the inter-stage gain is realized by adjusting the inter-stage gain increase/decrease control signal VCmdac1_gain_n, and the inter-stage gain size control signals Cmdac1_gain1_n, VCmdac1_gain2_n, VCmdac1_gain3_n, VCmdac1_gain4_n, VCmdac1_gain5_n. When the circuit is working normally, the control signal is directly added to the circuit according to the calibrated value. When calibrating the sub-DAC, the input terminal is connected to the reference level Vinp1-Vinn1=-31/64 Vref, and one of the control signals VC1_1 to VC1_31 of the control output controllable comparator is high, so that the corresponding output controllable comparator The output is set to 1, and other output controllable comparators output actual values. According to the input value, the outputs of other output controllable comparators are all 0. By comparing whether the output code difference before and after the output controllable comparator is set to 1 is 1/4 Vref, the error caused by the mismatch of the capacitance connected to the switch controlled by the output controllable comparator that is set to 1 is judged. Size, and eliminate this error by regulating the corresponding calibration error storage circuit in the second stage MDAC of the pipeline. Finally, through such a method, the output of the sub-DAC is calibrated accordingly. In normal operation, if the output of the controllable comparator is 1, then the corresponding calibration error storage circuit in the second-stage MDAC of the pipeline will add the error generated during calibration to the output signal of the second-stage MDAC of the pipeline. If the output of the controllable comparator is 0, the corresponding calibration error storage circuit in the second-stage MDAC of the pipeline will not add the error generated during calibration to the output signal of the second-stage MDAC of the pipeline.

See Figure 4. The second-stage MDAC of the pipeline adopts a fully differential charge-reversal circuit structure. Under normal operating conditions, the output of the first-stage MDAC of the pipeline is quantized to three bits, and a five-digit digital code is output. The quantized residual difference The value is magnified by 8 times. The quantization range of the comparator in this stage is doubled, and the output range of the upper stage MDAC is from -1/8 Vref to 1/8 Vref, so the quantization range of the comparator is from -1/8 Vref to 1/8 · Vref, now extend this range from -1/4 · Vref to 1/4 · Vref. This is mainly used to eliminate the residual difference generated by the upper level due to the threshold offset of the comparator exceeding the theoretical range of this level, so that by expanding the comparison range of the comparator, the excess value can be quantified accordingly, and through appropriate coding And digital correction to eliminate the error caused by the deviation of the threshold value of the upper comparator. Doing so allows the circuit to tolerate a threshold offset of ±1/64·Vref from the upper-level comparator. This stage also designs the corresponding calibration error storage circuit, which is mainly used to generate the error caused by the capacitance mismatch connected to the output of each comparator in the upper stage, and calibrate this error through this stage. There are 32 comparators in the upper stage, and the comparator with the threshold value of 32/64 Vref does not perform corresponding calibration processing, so 31 calibration error storage circuits are required at this stage. In order to realize the symmetry of the circuit, 32 calibration error storage circuits are designed. Circuit, respectively connect 32 calibration error storage circuits to the positive and negative ends of the input terminal on average. In order to achieve the same function, the structure of the calibration error storage circuit connected to the positive and negative ends is different, which is different from the positive and negative terminals of the operational amplifier 2 in MDAC. The one associated with the input end is a positive calibration error storage circuit, and the opposite is a negative calibration error storage circuit. The transfer function of this stage can be simply expressed as

$\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 17</span>}\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Verr</span>}& \mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&le;</span>\frac{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 8</span>}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\\ \mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Verr</span>}& \frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}<span\; class="notranslate">\; <</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&le;</span>\frac{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\\ \mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 17</span>}\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Verr</span>}& \frac{\mathrm{<span\; class="notranslate">\; 8</span>}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}<span\; class="notranslate">\; <</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\end{array}\right.$

Among them, Voutp2 is the positive terminal output of the current stage, Voutn2 is the negative terminal output of the current stage, Voutp1 is the positive terminal input of the current stage, which is also the positive terminal output of the upper stage, and Voutn1 is the negative terminal input of the current stage, which is also the upper stage The negative terminal output of Verr is the error value caused by the capacitance mismatch associated with the output controllable comparator whose output is 1 in the upper stage, and this value can be positive or negative. i ₂ is a corresponding integer, and its range is -8≤i ₂ ≤8.

In the calibration mode, the current stage is disconnected from the upper-level MDAC. At this time, the upper-level MDAC does not work, and the input terminal of the current level is connected to a fixed value. First of all, the calibration of the inter-stage gain is still carried out. Due to the mismatch of the feedback capacitor, the inter-stage gain will deviate. The input terminal is first connected to a fixed value of -19/64 Vref. At this time, since the output of the comparator is 0, the ideal residual difference of this stage is -1/8 Vref; then the input terminal is first connected to a fixed value. The value is -17/64·Vref. At this time, the ideal residual difference of this stage is 1/8·Vref, so the difference between the two output codes before and after is -1/4·Vref. Since the values connected to other capacitors do not change in the previous two times, if the difference of the residual difference between the two previous and previous times deviates from -1/4·Vref, it is mainly caused by the gain deviation between the stages of this stage. According to the difference between the two output codes before and after, it is judged whether the inter-stage gain is greater than 8 times or less than 8 times, and the inter-stage gain adjustment signal is used to adjust the inter-stage gain value to make it equal to 8 times. Afterwards, the sub-DAC is calibrated, and the output of one of the output controllable comparators of the current stage is set to 1 by using the control signal. At this time, the ideal residual difference of the current stage is -1/8·Vref, By comparing the output coding of the remaining difference before and after the controllable comparator is set to 1, the error caused by the mismatch of the associated capacitance is judged, and the corresponding calibration error storage circuit is regulated in the lower stage, so that the comparator is set to 1 The difference of the residual difference before and after is 1/4·Vref. This stores the error caused by the mismatch of the capacitance associated with the set comparator in the downstream stage. In normal operation, when the output of this output controllable comparator is 0, the error caused by the mismatch of the capacitance associated with the output controllable comparator will not be introduced into the lower stage. On the contrary, when the output of the controllable comparator is 1, the error caused by the mismatch of the capacitance associated with the comparator will be introduced to the output of the lower stage, thereby eliminating the error value.

Referring to Figure 4, it can be seen from the figure that under normal working conditions, when the clock is at low level, the output of clock signal clk2_n, clock signal clk2_n1, and clock signal clk2_n2 is at high level, and the clock clk2_p is at low level. At this time, MDAC The positive and negative input terminals of the operational amplifier A2 are short-circuited together through the NMOS transistor M86, and the input common-mode reference voltage Vcom2 is added through the NMOS transistor M84 and the NMOS transistor M85, and the positive and negative output terminals are also short-circuited together through the NMOS transistor M106. It acts as a reset for the output of the operational amplifier A2 in MDAC. At this time, the positive output and the negative output of the output controllable comparator Coc33 to the output controllable comparator Coc49 of this stage are all 1, and the inversion of the positive output and the inversion of the negative output are both 0, so the switch array Sr65 in this stage to In the switch array Sr98, the PMOS transistors connected to the reference voltage Vref and the NMOS transistors connected to the ground are in the off state, and only the NMOS transistors connected to the positive input signal and the negative input signal are turned on. In addition, the NMOS transistor M78 and the NMOS transistor M80 , NMOS transistor M81 , NMOS transistor M87 , NMOS transistor M89 , NMOS transistor M92 and NMOS transistor M93 are turned on, so that the capacitors C159 to C196 can sample the input signal. At the same time, the output controllable comparator Coc33 to the output controllable comparator Coc49 also implement sampling of the input signal. At this time, the positive calibration error storage circuit Ep1 to the positive calibration error storage circuit Ep16 store the negative output of the output controllable comparator Coc1 to the output controllable comparator Coc16 in the first stage MDAC, and the negative calibration error storage circuit En1 to The negative calibration error storage circuit En15 stores the negative output from the output controllable comparator Coc17 to the output controllable comparator Coc31 in the first-stage MDAC, the output of the negative calibration error storage circuit En16 is always a fixed value, and the positive calibration error The outputs of the storage circuit Ep1 to the positive calibration error storage circuit Ep16 and the negative calibration error storage circuit En1 to the negative calibration error storage circuit En15 are set to corresponding constant values, and the capacitors C108 to C139 are charged. Capacitors C140 to C155 will be connected in series with capacitors C108 to C139 respectively, so as to adjust the value that the output of the error calibration circuit adds to the output terminal of the MDAC of the current stage. In addition, the NMOS transistor M104 and the NMOS transistor M105 are turned on, and one end of the CMOS transmission gate T55 to the CMOS transmission gate T62 is connected to the input common-mode reference level Vcom2. At this time, the control signals VCmdac2_gain1_p and VCmdac2_gain1_n will control the CMOS transmission gate T55, the CMOS transmission gate T62, NMOS transistor M96, and NMOS transistor M103 are turned on or off, thereby determining that one end of capacitor C197 and capacitor C204 is grounded or connected to the input common-mode reference level Vcom2 when the clock is high; the control signals VCmdac2_gain2_p and VCmdac2_gain2_n will control the CMOS The transmission gate T56, the CMOS transmission gate T62, the NMOS transistor M97 and the NMOS transistor M102 are turned on or off, thereby determining that one end of the capacitor C198 and the capacitor C203 is grounded or connected to the input common-mode reference level Vcom2 when the clock is at a high level; The signals VCmdac2_gain3_p and VCmdac2_gain3_n will control the CMOS transmission gate T57, the CMOS transmission gate T60, the NMOS transistor M98 and the NMOS transistor M101 to be turned on or off, thereby determining whether one end of the capacitor C199 and the capacitor C202 is grounded or connected to the input common when the clock is at a high level. Modulus reference level Vcom2; control signals VCmdac2_gain4_p and VCmdac2_gain4_n will control the conduction or closure of CMOS transmission gate T58, CMOS transmission gate T59, NMOS transistor M99 and NMOS transistor M100, thereby determining the high voltage of capacitor C200 and capacitor C201 in the clock Usually one end is grounded or connected to the input common-mode reference level Vcom2; when the clock is at high level, the output of clock signal clk2_n, clock signal clk2_n1, and clock signal clk2_n2 is at low level, and clk2_p is at high level. At this time, the operation in MDAC The amplifier A2 works normally, the bootstrap switch S7 and the bootstrap switch S8 output effective control signals, so that the lower plates of the capacitor C156 and the capacitor C196 are respectively connected to the positive and negative output terminals of the operational amplifier A2 in the MDAC. The output of the switch array Sr65 to the switch array Sr98 will be determined by the output of the output controllable comparator Coc33 to the output controllable comparator Coc49. The output controllable comparator obtains the corresponding output by comparing the input signal with the threshold. The thresholds of the comparators in the second stage of the pipeline MDAC are: 8/32 Vref, 7/32 Vref, 6/32 Vref , 5/32·Vref, 4/32·Vref, 3/32·Vref, 2/32·Vref, 1/32·Vref, 0/32·Vref, -1/32·Vref, -2/32·Vref , -3/32·Vref, -4/32·Vref, -5/32·Vref, -6/32·Vref, -7/32·Vref, -8/32·Vref. In addition, at this time, the PMOS transistor M79, the NMOS transistor M82, the PMOS transistor M83 and the PMOS transistor M88 are turned on. At this time, the control signal Vcorrect2 is always at a low level, so that the NMOS transistor M91 is turned off; the control signal VSamp2 is in phase with the clock signal clk2_n, and the PMOS transistor M90 is turned on. In this way, recharging of the capacitors C157 to C195 is realized. At the same time, the positive calibration error storage circuit Ep1 to the positive calibration error storage circuit Ep16 and the negative calibration error storage circuit En1 to the negative calibration error storage circuit En15 will output the controllable comparator Coc1 to the output controllable comparator Coc31 in the first stage MDAC of the pipeline. The fixed value determined by the negative output of the capacitor C108 to capacitor C139 is recharged, so that the error of the sub-DAC in the first stage MDAC of the pipeline can be added to the output signal of this stage. The total capacitance of the 20 capacitors from capacitor C156 to capacitor C175 is the same as the total capacitance of the 21 capacitors from C176 to capacitor C196, both of which are 64 unit capacitors C0_2, of which the size of capacitor C156 and capacitor C196 are both 8 unit capacitors The size of C0_2, capacitor C175 and capacitor C176 is 20 unit capacitors C0_2, the size of capacitor C177 is 16 unit capacitors C0_2, the size of capacitor C174 is 17 unit capacitors C0_2, and the remaining capacitors are all unit capacitors C0_2. The 48 capacitors from capacitor C108 to capacitor C155 are equally large, and they are all C0_2. According to the principle of charge conservation, the second-stage MDAC in the pipeline implements three-bit quantization of the input signal and amplifies the remaining difference by 8 times. The encoding circuit 2 encodes the output of the controllable comparator. Since the output of the controllable comparator is the thermometer code, it needs the encoding circuit 2 to convert it into a binary code. Firstly, use XOR logic to convert the thermometer code into single 1 code, and then use OR gate to convert single 1 code into binary code. The encoding result of the second-stage pipeline MDAC:

Vinp2-Vinn2=Vin2 D25 D24 D23 D22 D21 Vin2>8/32Vref 0 1 1 0 0 8/32Vref>Vin2>7/32Vref 0 1 0 1 1 7/32Vref>Vin2>6/32Vref 0 1 0 1 0 6/32Vref>Vin2>5/32Vref 0 1 0 0 1 5/32Vref>Vin2>4/32Vref 0 1 0 0 0 4/32Vref>Vin2>3/32Vref 0 0 1 1 1 3/32Vref>Vin2>2/32Vref 0 0 1 1 0 2/32Vref>Vin2>1/32Vref 0 0 1 0 1 1/32Vref>Vin2>0/32Vref 0 0 1 0 0 0/32Vref>Vin2>-1/32Vref 0 0 0 1 1 -1/32Vref>Vin2>-2/32Vref 0 0 0 1 0 -2/32Vref>Vin2>-3/32Vref 0 0 0 0 1 -3/32Vref>Vin2>-4/32Vref 0 0 0 0 0 -4/32Vref>Vin2>-5/32Vref 1 1 1 1 1 -5/32Vref>Vin2>-6/32Vref 1 1 1 1 0 -6/32Vref>Vin2>-7/32Vref 1 1 1 0 1 -7/32Vref>Vin2>-8/32Vref 1 1 1 0 0 -8/32Vref>Vin2 1 1 0 1 1

In the calibration mode, the current stage is disconnected from the upper-level MDAC. At this time, the upper-level MDAC does not work, and the input terminal of the current level is connected to a fixed value. At this time, the control signal Vcorrect2 is in phase with the clock signal clk2_p, so that the NMOS transistor M91 is turned on when the signal is always at a high level; the control signal Vnormal2 is always at a high level, so that the PMOS transistor M90 is always turned off. At first the calibration of the interstage gain is carried out, first the input is connected to the reference level Vinp2-Vinn2=-19/64 Vref, at this moment the outputs from the output Coc33 of the controllable comparator to the output Coc49 of the controllable comparator are all 0, A corresponding output code is obtained, and then the input is connected to the reference level Vinp1-Vinn1=-17/64·Vref to obtain another corresponding output code. When the inter-stage gain of this stage is 8 times, the difference between the output codes before and after should be -1/4·Vref. When the difference between the front and rear codes deviates from this value, the value of the inter-stage gain increase and decrease control signal VCmdac2_gain1_n to the inter-stage gain increase and decrease control signal VCmdac2_gain4_n can be adjusted to realize the increase and decrease adjustment of the inter-stage gain. The inter-stage gain increase and decrease control signal VCmdac2_gain1_p It is the inverse of the inter-stage gain increase/decrease control signal VCmdac2_gain1_n. The inter-stage gain increase/decrease control signal VCmdac2_gain_n is at a high level, so that the CMOS transmission gate T64 and the CMOS transmission gate T65 are turned on, so that the negative feedback capacitance is increased to realize the reduction of the inter-stage gain; the inter-stage gain increase/decrease control signal VCmdac2_gain_n is low Level, so that the CMOS transmission gate T63 and the CMOS transmission gate T66 are turned on, so that the positive feedback capacitance is increased, and the inter-stage gain is increased. The inter-stage gain control signals VCmdac2_gain1_n, VCmdac2_gain2_n, VCmdac2_gain3_n, VCmdac2_gain4_n can be adjusted to realize the change amount of the inter-stage gain. The inter-stage gain control signals VCmdac2_gain1_p, VCmdac2_gain2_p, VCmdac2_gain3_p, and VCmdac2_gain4_p are the inverses of the inter-stage gain control signals VCmdac2_gain1_n, VCmdac2_gain2_n, VCmdac2_gain3_n, and VCmdac2_gain4_n, respectively. When the inter-stage gain control signal VCmdac2_gain1_n is at a high level, it does not affect the inter-stage gain. If the inter-stage gain control signal VCmdac2_gain1_n is at a low level, the corresponding inter-stage gain becomes (C176+C177+…+C196) /(C196±C197). When the inter-stage gain control signal VCmdac2_gain2_n is at a high level, it does not affect the inter-stage gain. If the inter-stage gain control signal VCmdac2_gain2_n is at a low level, the corresponding inter-stage gain becomes (C176+C177+…+C196) /(C196±C198). When the inter-stage gain control signal VCmdac2_gain3_n is at a high level, it does not affect the inter-stage gain. If the inter-stage gain control signal VCmdac2_gain3_n is at a low level, the corresponding inter-stage gain becomes (C176+C177+…+C196) /(C196±C199). When the inter-stage gain control signal VCmdac2_gain4_n is at a high level, it does not affect the inter-stage gain. If the inter-stage gain control signal VCmdac2_gain4_n is at a low level, the corresponding inter-stage gain becomes (C176+C177+…+C196) /(C196±C200). Calibration of the inter-stage gain is realized by adjusting the inter-stage gain increase/decrease control signal VCmdac2_gain_n, and the inter-stage gain control signals Cmdac2_gain1_n, VCmdac2_gain2_n, VCmdac2_gain3_n, VCmdac2_gain4_n. When the circuit is working normally, the control signal is directly added to the circuit according to the calibrated value. When calibrating the sub-DAC, the input terminal is connected to the reference level Vinp1-Vinn1=-31/64 Vref, and one of the control signals VC2_1 to VC2_17 of the output controllable comparator is controlled to be high level, so that the corresponding output controllable comparison The output of the controllable comparator is set to 1, and the other output controllable comparators output the actual value. According to the input value, the output of the other output controllable comparators are all 0. By comparing whether the output code difference before and after the output controllable comparator is set to 1 is 1/4 Vref, the error caused by the mismatch of the capacitance connected to the switch controlled by the output controllable comparator that is set to 1 is judged. Size, and eliminate this error by regulating the corresponding calibration error storage circuit in the third stage MDAC of the pipeline. Finally, through such a method, the output of the sub-DAC is calibrated accordingly. In normal operation, if the output of the controllable comparator is 1, then the corresponding calibration error storage circuit in the third-stage MDAC of the pipeline will add the error generated during calibration to the output signal of the third-stage MDAC of the pipeline. If the output of the controllable comparator is 0, the corresponding calibration error storage circuit in the third-stage MDAC of the pipeline will not add the error generated during calibration to the output signal of the third-stage MDAC of the pipeline.

See Figure 5. The third-stage MDAC of the pipeline adopts a fully differential charge-reversal circuit structure. Under normal operating conditions, the output of the second-stage MDAC of the pipeline is quantized to three bits, and a five-digit digital code is output, and then the quantized The remaining difference is magnified by 8 times. Also doubles the quantization range of the comparators in this stage. Expand from the original -1/8·Vref to 1/8·Vref to the current -1/4·Vref to 1/4·Vref. This is mainly used to eliminate the error caused by the output result of the upper stage exceeding the quantization interval of the current stage due to the offset of the threshold value of the upper-stage comparator. After expanding the quantization range of this stage, the output of the upper stage can be properly coded, and finally the correct result can be obtained in the digital correction circuit. So doing so can make the circuit tolerant to the threshold offset of ±1/64·Vref in the upper comparator. In addition, a corresponding calibration error storage circuit is added in this stage to eliminate the error of the neutron DAC in the upper stage. The transfer function expression of this stage:

$\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 17</span>}\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Verr</span>}\mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&le;</span>\frac{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 8</span>}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\\ \mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Verr</span>}\mathrm{<span\; class="notranslate">\; 1</span>}& \frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}<span\; class="notranslate">\; <</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&le;</span>\frac{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\\ \mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 17</span>}\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Verr</span>}\mathrm{<span\; class="notranslate">\; 1</span>}& \frac{\mathrm{<span\; class="notranslate">\; 8</span>}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}<span\; class="notranslate">\; <</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 2</span>}\end{array}\right.$

Among them, Voutp3 is the positive terminal output of the current stage, Voutn3 is the negative terminal output of the current stage, Voutp2 is the positive terminal input of the current stage, which is also the positive terminal output of the upper stage, and Voutn2 is the negative terminal input of the current stage. The negative terminal output of the upper stage, Verr1 is the error value caused by the capacitance mismatch associated with the output controllable comparator whose output is 1 in the upper stage, and this value can be positive or negative. i3 is a corresponding integer, and its range is -8≤i ₃ ≤8.

Since the output of the remaining difference value of this stage only needs to meet the accuracy requirement of 7 bits, the mismatch of the capacitance can meet this accuracy, so there is no requirement for calibration at this stage.

Referring to Figure 5, it can be seen from the figure that when the circuit is working, when the clock is at high level, the clock signal clk3_p, clock signal clk3_p1, clock signal clk3_p2 and clock signal clk3_p3 are at high level, and the clock signal clk3_n and clock signal clk3_n3 are at low level . At this time, the positive and negative input terminals of the operational amplifier A3 in the MDAC are short-circuited together by the NMOS transistor M124, and the input common-mode reference voltage Vcom3 is added through the NMOS transistor M122 and the NMOS transistor M123, and the positive and negative output terminals are short-circuited by the NMOS transistor M128. Together, it plays a role in resetting the output of the operational amplifier A3 in MDAC. At this time, the positive output and the negative output of the comparator Com1 to the output controllable comparator Com17 of this stage are both 1, and the inversion of the positive output and the inversion of the negative output are both 0, so the switch array Sr99 to the switch array Sr118 in this stage The PMOS transistors connected to the reference voltage Vref and the NMOS transistors connected to the ground are in the off state, and only the NMOS transistors connected to the positive input signal and the negative input signal are turned on. In addition, the NMOS transistor M113, NMOS transistor M114, and NMOS transistor The transistor M116, the NMOS transistor M118, the NMOS transistor M199, and the NMOS transistor M125 are turned on, so as to implement the sampling of the input signal by the capacitor C239 to the capacitor C264. At the same time, the comparators Com1 to Com17 also implement sampling of the input signal. At this time, the positive calibration error storage circuit Ep17 to the positive calibration error storage circuit Ep25 store the negative outputs of the output controllable comparator Coc33 to the output controllable comparator Coc41 in the second-stage MDAC, and the negative calibration error storage circuit En17 to The negative calibration error storage circuit En24 stores the negative output from the output controllable comparator Coc42 to the output controllable comparator Coc49 in the second-stage MDAC. In order to match the positive and negative input terminals of the third-stage MDAC, PMOS transistors M107, NMOS transistor M108, PMOS transistor M109, NMOS transistor M110, PMOS transistor M111, and NMOS transistor M112. At the same time, the outputs of the positive calibration error storage circuit Ep17 to the positive calibration error storage circuit Ep25 and the negative calibration error storage circuit En17 to the negative calibration error storage circuit En24 are placed at corresponding constant values, and the PMOS transistor 107, the PMOS transistor M109 and the PMOS transistor M111 conduct Through, charge from the capacitor C209 to the capacitor C228. Capacitors C229 to C238 are connected in series with capacitors C209 to C228 respectively, so as to adjust the value that the output of the error calibration circuit adds to the output terminal of the MDAC of the current stage. At this time, the output of the encoding circuit E3 is all 0. When the clock is at a low level, the clock signals clk3_p, clk3_p1, clk3_p2 and clk3_p3 are at a low level, and the clock signals clk3_n and clk3_n3 are at a high level. At this time, the operational amplifier A3 in the MDAC works normally, and the bootstrap switch S9 and the bootstrap switch S10 outputs an effective control signal, so that the lower plates of the capacitor C239 and the capacitor C264 are respectively connected to the positive and negative output terminals of the operational amplifier A3 in the MDAC. The output of the switch array Sr99 to the switch array Sr118 will be determined by the output of the comparator Com1 to the comparator Com17. The comparator obtains the corresponding output by comparing the input signal with the threshold. The thresholds of the comparators in the third-stage MDAC of the pipeline are: 8/32 Vref, 7/32 Vref, 6/32 Vref, 5/ 32·Vref, 4/32·Vref, 3/32·Vref, 2/32·Vref, 1/32·Vref, 0/32·Vref, -1/32·Vref, -2/32·Vref, -3 /32·Vref, -4/32·Vref, -5/32·Vref, -6/32·Vref, -7/32·Vref, -8/32·Vref. In addition, at this time, the PMOS transistor M115 , the NMOS transistor M117 , the PMOS transistor M120 and the PMOS transistor M121 are turned on. In this way, recharging of the capacitors C240 to C263 is realized. At the same time, the positive calibration error storage circuit Ep17 to the positive calibration error storage circuit Ep25 and the negative calibration error storage circuit En17 to the negative calibration error storage circuit En24 will output the controllable comparator Coc33 to the output controllable comparator Coc49 in the second stage MDAC of the pipeline. The fixed value determined by the negative output of the capacitor realizes the recharging of the capacitor C112 to the capacitor C127, so that the error of the sub-DAC of the second stage MDAC of the pipeline can be added to the output signal of this stage. The total capacitance of the 13 capacitors from capacitor C239 to capacitor C251 is the same as the total capacitance of the 13 capacitors from C252 to capacitor C264, both of which are 32 unit capacitors C0_3, and the size of capacitor C239 and capacitor C264 are both 4 unit capacitors The size of C0_3, capacitor C250 and capacitor C253 is 6 unit capacitors C0_3, the size of capacitor C251 and capacitor C252 is 12 unit capacitors C0_3, and the size of the remaining capacitors are all unit capacitors C0_3. The 30 capacitors from capacitor C209 to capacitor C238 are equally large, and they are all C0_3. According to the principle of charge conservation, the third-stage MDAC in the pipeline realizes three-bit quantization of the input signal and amplifies the remaining difference by 8 times. The encoding circuit 3 encodes the output of the comparator. Since the output of the comparator is a thermometer code, the encoding circuit 3 is needed to convert it into a binary code. Firstly, use XOR logic to convert the thermometer code into single 1 code, and then use OR gate to convert single 1 code into binary code. The encoding result of the third-stage pipeline MDAC:

Vinp3-Vinn3=Vin3 D35 D34 D33 D32 D31 Vin3>8/32Vref 0 1 1 0 0 8/32Vref>Vin3>7/32Vref 0 1 0 1 1 7/32Vref>Vin3>6/32Vref 0 1 0 1 0 6/32Vref>Vin3>5/32Vref 0 1 0 0 1 5/32Vref>Vin3>4/32Vref 0 1 0 0 0 4/32Vref>Vin3>3/32Vref 0 0 1 1 1 3/32Vref>Vin3>2/32Vref 0 0 1 1 0 2/32Vref>Vin3>1/32Vref 0 0 1 0 1 1/32Vref>Vin3>0/32Vref 0 0 1 0 0 0/32Vref>Vin3>-1/32Vref 0 0 0 1 1 -1/32Vref>Vin3>-2/32Vref 0 0 0 1 0 -2/32Vref>Vin3>-3/32Vref 0 0 0 0 1 -3/32Vref>Vin3>-4/32Vref 0 0 0 0 0 -4/32Vref>Vin3>-5/32Vref 1 1 1 1 1 -5/32Vref>Vin3>-6/32Vref 1 1 1 1 0 -6/32Vref>Vin3>-7/32Vref 1 1 1 0 1 -7/32Vref>Vin3>-8/32Vref 1 1 1 0 0 -8/32Vref>Vin3 1 1 0 1 1

See Figure 6. The fourth-stage MDAC in the pipeline adopts a fully differential charge-reversal circuit structure. This stage performs three-bit quantization on the output of the upper-stage MDAC, outputs a five-digit digital code, and amplifies the quantized difference by 8 times. Similarly, the quantization range of the comparator at this stage is doubled. Expand from the original -1/8·Vref to 1/8·Vref to the current -1/4·Vref to 1/4·Vref. This is mainly used to eliminate the error caused by the output result of the upper stage exceeding the quantization interval of the current stage due to the offset of the threshold value of the upper-stage comparator. After expanding the quantization range of this stage, the output of the upper stage can be properly coded, and finally the correct result can be obtained in the digital correction circuit. So doing so can make the circuit tolerant to the threshold offset of ±1/64·Vref in the upper comparator. The expression of the transfer function of this stage:

$\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 17</span>}\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span>& \mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; \&le;</span>\frac{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 8</span>}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\\ \mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span>& \frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}<span\; class="notranslate">\; <</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; \&le;</span>\frac{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}\\ \mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 17</span>}\mathrm{<span\; class="notranslate">\; Vref</span>}}{\mathrm{<span\; class="notranslate">\; 64</span>}}<span\; class="notranslate">\; )</span>& \frac{\mathrm{<span\; class="notranslate">\; 8</span>}}{\mathrm{<span\; class="notranslate">\; 32</span>}}\mathrm{<span\; class="notranslate">\; Vref</span>}<span\; class="notranslate">\; <</span>\mathrm{<span\; class="notranslate">\; Voutp</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Voutn</span>}\mathrm{<span\; class="notranslate">\; 3</span>}\end{array}\right.$

Among them, Voutp4 is the positive terminal output of the current stage, Voutn4 is the negative terminal output of the current stage, Voutp3 is the positive terminal input of the current stage, which is also the positive terminal output of the upper stage, and Voutn3 is the negative terminal input of the current stage. The negative terminal output of the upper stage, i4 is the corresponding integer, and its range is -8≤i ₄ ≤8.

Referring to Figure 6, it can be seen from the figure that when the circuit is working, when the clock is at low level, the clock signal clk4_n, clock signal clk4_n1, clock signal clk4_n2 and clock signal clk4_n3 are at high level, and the clock signal clk4_p and clock signal clk4_p3 are at low level flat. At this time, the positive and negative input terminals of the operational amplifier A4 in the MDAC are short-circuited together by the NMOS transistor M144, and the input common-mode reference voltage Vcom4 is added through the NMOS transistor M142 and the NMOS transistor M143, and the positive and negative output terminals are short-circuited by the NMOS transistor M152. Together, it plays a role in resetting the output of the operational amplifier A4 in the MDAC. At this time, the positive output and the negative output of the comparator Com18 to the output controllable comparator Com34 of this stage are both 1, and the inversion of the positive output and the inversion of the negative output are both 0, so the switch array Sr119 to the switch array Sr138 in this stage The PMOS transistor connected to the reference voltage Vref and the NMOS transistor connected to the ground are in the off state, and only the NMOS transistor connected to the positive input signal and the negative input signal is turned on. In addition, the NMOS transistor M135, NMOS transistor M136, and NMOS transistor The transistor M138 , the NMOS transistor M140 , the NMOS transistor M145 , and the NMOS transistor M147 are turned on, so as to realize the sampling of the input signal by the capacitor C273 to the capacitor C298 . At this time, the output of the encoding circuit E4 is all 0. When the clock is at high level, the clock signal clk4_n, clock signal clk4_n1, clock signal clk4_n2 and clock signal clk4_n3 are at low level, and the clock signal clk4_p and clock signal clk4_p3 are at high level. At this time, the operational amplifier A4 in MDAC works normally, and the NMOS The transistor M148, the NMOS transistor M50, the PMOS transistor M149, and the PMOS transistor M151 are turned on, so that the lower plates of the capacitor C273 and the capacitor C298 are respectively connected to the positive and negative output terminals of the operational amplifier A4 in the MDAC. The output of the switch array Sr119 to the switch array Sr138 will be determined by the output of the comparator Com18 to the comparator Cmo34. The comparator obtains the corresponding output by comparing the input signal with the threshold. The thresholds of the comparators in the fourth-stage MDAC of the pipeline are: 8/32 Vref, 7/32 Vref, 6/32 Vref, 5/ 32·Vref, 4/32·Vref, 3/32·Vref, 2/32·Vref, 1/32·Vref, 0/32·Vref, -1/32·Vref, -2/32·Vref, -3 /32·Vref, -4/32·Vref, -5/32·Vref, -6/32·Vref, -7/32·Vref, -8/32·Vref. In addition, at this time, the PMOS transistor M137 , the NMOS transistor M139 , the PMOS transistor M141 and the PMOS transistor M146 are turned on. In this way, recharging of the capacitors C274 to C294 is realized. The total capacitance of the 13 capacitors from capacitor C273 to capacitor C285 is the same as the total capacitance of the 13 capacitors from C286 to capacitor C298, which are 32 unit capacitors C0_4, and the size of capacitor C273 and capacitor C285 are both 4 unit capacitors The size of C0_4, capacitor C284 and capacitor C287 is 6 unit capacitors C0_4, the size of capacitor C285 and capacitor C286 is 12 unit capacitors C0_4, and the size of the remaining capacitors are all unit capacitors C0_4. According to the principle of charge conservation, the fourth-stage MDAC in the pipeline realizes three-bit quantization of the input signal and amplifies the remaining difference by 8 times. The encoding circuit 4 encodes the output of the comparator. Since the output of the comparator is a thermometer code, it needs to be converted into a binary code by the encoding circuit 4 . Firstly, use XOR logic to convert the thermometer code into single 1 code, and then use OR gate to convert single 1 code into binary code. The encoding result of the fourth-stage pipeline MDAC:

Vinp4-Vinn4=Vin4 D45 D44 D43 D42 D41 Vin4>8/32Vref 0 1 1 0 0 8/32Vref>Vin4>7/32Vref 0 1 0 1 1 7/32Vref>Vin4>6/32Vref 0 1 0 1 0 6/32Vref>Vin4>5/32Vref 0 1 0 0 1 5/32Vref>Vin4>4/32Vref 0 1 0 0 0 4/32Vref>Vin4>3/32Vref 0 0 1 1 1 3/32Vref>Vin4>2/32Vref 0 0 1 1 0 2/32Vref>Vin4>1/32Vref 0 0 1 0 1 1/32Vref>Vin4>0/32Vref 0 0 1 0 0 0/32Vref>Vin4>-1/32Vref 0 0 0 1 1 -1/32Vref>Vin4>-2/32Vref 0 0 0 1 0 -2/32Vref>Vin4>-3/32Vref 0 0 0 0 1 -3/32Vref>Vin4>-4/32Vref 0 0 0 0 0 -4/32Vref>Vin4>-5/32Vref 1 1 1 1 1 -5/32Vref>Vin4>-6/32Vref 1 1 1 1 0 -6/32Vref>Vin4>-7/32Vref 1 1 1 0 1 -7/32Vref>Vin4>-8/32Vref 1 1 1 0 0 -8/32Vref>Vin4 1 1 0 1 1

See Figure 7, the fifth-stage flash ADC of the pipeline, quantizes the output of the fourth-stage MDAC of the pipeline by two digits, and outputs a four-digit digital code, and also changes the quantization range of the comparator from the original -1/8·Vref to 1 /8 Vref expands from -6/32 Vref to 6/32 Vref. This is mainly used to eliminate the error caused by the output result of the upper stage exceeding the quantization interval of the current stage due to the offset of the threshold value of the upper-stage comparator. After expanding the quantization range of this stage, the output of the upper stage can be properly coded, and finally the correct result can be obtained in the digital correction circuit. So doing so can make the circuit tolerant to the threshold offset of ±1/64·Vref in the upper comparator.

Referring to Figure 7, it can be seen from the figure that when the circuit is working, when the clock is at a high level, the comparator Com35 to the comparator Com41 sample the input signal, and at this time the positive output and the negative output of the comparator Com35 to the comparator Com41 are both 1. Both the inverse of positive output and the inverse of negative output are 0. The output of the encoding circuit E5 is all 0s. When the clock is at a low level, the comparator obtains a corresponding output according to comparing the input signal with the threshold. The thresholds of the comparator at this level are: 3/16 Vref, 2/16 Vref, 1/16 Vref, 0/16 Vref, -1/16 Vref, -2/16 Vref, -3/ 16 Vref. The encoding circuit 5 encodes the output of the comparator. Since the output of the comparator is a thermometer code, it needs the encoding circuit E5 to convert it into a binary code. Firstly, use XOR logic to convert the thermometer code into single 1 code, and then use OR gate to convert single 1 code into binary code. The encoding result of the fifth-stage pipeline flash ADC:

Vinp5–Vinn5=Vin5 D54 D53 D52 D51 Vin5>3/16Vref 0 1 0 1 3/16Vref>Vin5>2/16Vref 0 1 0 0 2/16Vref>Vin5>1/16Vref 0 0 1 1 1/16Vref>Vin5>0/16Vref 0 0 1 0 0/16Vref>Vin5>-1/16Vref 0 0 0 1 -1/16Vref>Vin5>-2/16Vref 0 0 0 0 -2/16Vref>Vin5>-3/16Vref 1 1 1 1 -3/16Vref>Vin5 1 1 1 0

See Figure 8, the digital correction circuit, because the magnification of the remaining difference of the first stage MDAC of the pipeline is compressed by 4 times, the second stage MDAC of the pipeline, the third stage MDAC of the pipeline, the fourth stage MDAC of the pipeline and the fifth stage of the pipeline flash The input quantization interval of the ADC is expanded accordingly. This is done in order to make the threshold offset in the comparator within the range of ±1/64·Vref without affecting the performance of the ADC. Then the encoding of each level will generate the corresponding output code according to the input value of each level. In addition, the random value added in the sample and hold circuit also needs to be subtracted from the output result. Therefore, it is necessary to perform corresponding logic addition and subtraction operations on the output code of each stage and the random value added in the sample-and-hold circuit to obtain the final correct 16-bit output binary code of the ADC.

Referring to Figure 8, it can be seen from the figure that the digital correction circuit directly outputs the output codes D52 and D51 of the fifth-stage flash ADC of the pipeline, and the output code D53 of the fifth-stage flash ADC of the pipeline will be the same as the output of the fourth-stage MDAC of the pipeline The code D41 is added, and the output code D42 of the fourth stage of the pipeline will be subtracted from the output code D54 of the flash ADC of the fifth stage of the pipeline. The principle of this is that when the threshold value of a comparator in the fourth-stage MDAC of the pipeline deviates from the theoretical value, and everything else is normal, if the threshold value is too large, when the input value is between the theoretical threshold value and the actual threshold value, the first stage of the pipeline The output signal of the four-stage MDAC will be higher than 1/8 Vref, and its output code is 1 smaller than the theoretical threshold value. The output codes D52 and D51 of the fifth-stage flash ADC of the pipeline are the same as the theoretical threshold, while the fifth-stage flash ADC of the pipeline The output code D53 of the ADC is 1, which needs to be added to the output code D41 of the fourth-stage MDAC in the pipeline, so that the final encoding result with a larger threshold is the same as the theoretical threshold encoding result. If the threshold is too small, when the input value is between the theoretical threshold and the actual threshold, the output signal of the fourth-stage MDAC in the pipeline will be lower than -1/8·Vref, and its output code is 1 larger than the theoretical threshold, and the fifth in the pipeline The output codes D52 and D51 of the first-stage flash ADC are the same as the theoretical threshold, while the output code D53 of the fifth-stage flash ADC of the pipeline is 1, which needs to be added to the output code D41 of the fourth-stage MDAC of the pipeline, and the fifth-stage flash ADC of the pipeline The output code D54 of the ADC is 1, which needs to be subtracted from the output code D42 of the fourth-stage MDAC of the pipeline. In fact, the output code D41 of the fourth-stage MDAC of the pipeline is subtracted by 1, so that the encoding result with a smaller final threshold and the theoretical threshold The result of encoding is the same. Similarly, the output code D31 of the third-stage MDAC of the pipeline needs to be added with the output code D44 of the fourth-stage MDAC of the pipeline, and the output code D32 of the third-stage MDAC of the pipeline needs to be subtracted from the output code D45 of the fourth-stage MDAC of the pipeline; The output code D21 of the first-stage MDAC needs to be added with the output code D34 of the third-stage MDAC of the pipeline, the output code D22 of the second-stage MDAC of the pipeline needs to be subtracted from the output code D35 of the third-stage MDAC of the pipeline, and the output code D11 of the first-stage MDAC of the pipeline The output code D24 of the second-stage MDAC of the pipeline needs to be added, and the output code D12 of the first-stage MDAC of the pipeline needs to be subtracted from the output code D25 of the second-stage MDAC of the pipeline. In addition, it is necessary to subtract the random signal control signals dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n added to the output signal of the sample and hold circuit, and finally obtain the 16-bit binary code of the actual input value. When the input is higher than the maximum positive input value, the input signal overflow quantization range indication signal OF is 1, and the other 16-bit outputs are all 1. When the input is lower than the minimum negative input value, the input signal overflow quantization range indication signal OF is the same is 1, and the other 16 are all 0 for output. When the input signal is in the normal quantization range, the input signal overflows the quantization range indicating signal OF is 0.

It can be seen from the above structure that during normal operation, when the clock signal is at low level, the sample-and-hold circuit samples the input signal; when the clock is at high level, the first-stage MDAC of the pipeline samples the output of the sample-and-hold circuit, and the pipeline The comparator in the first stage MDAC also samples this value at the same time. When the clock is low again, the output value generated by the output controllable comparator of the first-stage MDAC of the pipeline will control the output of the sub-DAC, and amplify the quantized residual difference by 8 times for output, and the second-stage MDAC of the pipeline will sample this output value , and at the same time realize the encoding of the output value of the output controllable comparator of the current stage. Similarly, when the clock of the second-stage MDAC of the pipeline is at a high level, the output value generated by the output controllable comparator will control the output of the sub-DAC, and amplify the quantized residual difference by 8 times for output, and the third-stage MDAC of the pipeline samples this output value , and at the same time complete the coding of the output value of the output controllable comparator of the current stage. The timing of the third-stage MDAC and the fifth-stage flash ADC of the pipeline is the same as that of the first-stage pipeline. The timing of the fourth-stage MDAC of the pipeline is the same as that of the second-stage MDAC of the pipeline.

Referring to FIG. 9, it can be seen from the figure that the positive calibration error storage circuit includes: CMOS transmission gate T70, CMOS transmission gate T71, inverter I1, inverter I2, inverter I3, inverter I4, and a NAND gate Nand1, NOR gate Sor1, current regulation circuit Ic1, resistor R1, resistor R2, NMOS transistor M155, NMOS transistor M156. When calibrating, first, the clock signal clk6_p is low level, clk6_n is high level, the output of the NAND gate Nand1 is always 1, when the positive and negative control signal Vcdac_updown_1 of the calibration error is high, the output of the NOR gate is 1, which means At this time, the NMOS transistor M156 is turned on, and the output terminal of the calibration error storage circuit is the voltage of the drain of the transistor M156. After that, the clock signal clk6_p is high level, the clock signal clk6_n is low level, and when the input signal Vin_cn is low, that is, the negative output of the corresponding comparator is 0. At this time, the output of the NAND gate Nand1 is 0, and the NOR gate The output of Sor1 is 0, at this time the NMOS transistor M155 is turned on, and the output terminal of the calibration error storage circuit is the voltage of the drain of the transistor M155. If the calibration error storage circuit is associated with the positive input of the operational amplifier in the corresponding MDAC, ie positive calibration error storage circuit, then an error value will be subtracted from the output signal of the corresponding MDAC. The magnitude of this error signal will be determined by the 1-fold reference current adjustment signal Vcdac_c1_1, the 2-fold reference current adjustment signal Vcdac_c1_2, the 4-fold reference current adjustment signal Vcdac_c1_3, and the 8-fold reference current adjustment signal Vcdac_c1_4. When the calibration error positive and negative control signal Vcdac_updown_1 is low, an error value will be added to the output signal of the corresponding MDAC. If the input signal Vin_cn is high, the output of the calibration error storage circuit does not change when the clock signal clk6_p changes from low level to high level, so the calibration error storage circuit does not affect the corresponding output signal of MDAC. In order to make the calibration error positive and negative control signal Vcdac_updown_1 high always indicates that an error value will be subtracted in the output signal of the corresponding MDAC. When the calibration error storage circuit is related to the negative input terminal of the operational amplifier in the corresponding MDAC, that is, the negative calibration error storage circuit, the gate signals of the NMOS transistor M155 and the NMOS transistor M156 in the calibration error storage circuit are interchanged.

In normal operation, the adjustment signal in the calibration error storage circuit, the calibration error positive and negative control signal Vcdac_updown_1, 1 times the reference current adjustment signal Vcdac_c1_1, 2 times the reference current adjustment signal Vcdac_c1_2, 4 times the reference current adjustment signal Vcdac_c1_3, 8 times the reference current The adjustment signal Vcdac_c1_4 will be loaded into the circuit according to the value during calibration. In this way, the calibration of errors caused by capacitance mismatch is realized.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (14)

1. A 16-bit pipeline analog-to-digital converter, characterized in that, comprising: The pre-sampling and holding circuit, the first stage, the second stage, the third stage, the fourth stage multi-digit digital-to-analog converter and the fifth-stage flash analog-to-digital converter connected in sequence, and the first stage and the first stage respectively , the digital correction circuit connected to the second stage, the third stage, the fourth stage multi-digit digital-to-analog converter and the fifth-stage flash analog-to-digital converter; wherein, The sample-and-hold circuit samples the input signal, and outputs the input signal to the first-stage multi-digit digital-to-analog converter; The first-stage multi-digit digital-to-analog converter samples the output of the sample-and-hold circuit, amplifies and outputs the quantized residual difference, and completes the encoding of the output value of the output controllable comparator at this stage; The second-stage multi-digit digital-to-analog converter samples the output of the first-stage multi-digit digital-to-analog converter, amplifies and outputs the quantized residual difference, and completes the encoding of the output value of the current-stage output controllable comparator; The third-stage multi-digit digital-to-analog converter samples the output of the second-stage multi-digit digital-to-analog converter, and at the same time completes the encoding of the output value of the output controllable comparator at this stage; The fourth-stage multi-digit digital-to-analog converter samples the output of the third-stage multi-digit digital-to-analog converter, and at the same time completes the coding of the output value of the output controllable comparator at this stage; The fifth-stage flash analog-to-digital converter samples the output of the fourth-stage multi-digit digital-to-analog converter, and at the same time completes the encoding of the output value of the output controllable comparator of this stage; The timing of the third-stage multi-digit digital-to-analog converter and the fifth-stage flash analog-to-digital converter is the same as that of the first-stage multi-digit digital-to-analog converter; The timing of the fourth-stage multi-digit DAC is the same as that of the second-stage multi-digit DAC. 2. The analog-to-digital converter according to claim 1, wherein the pre-sampling and holding circuit comprises: a first operational amplifier (Ash1), first, second, third and fourth bootstrap switches, Transmission gates and capacitors; The positive and negative input terminals of the first operational amplifier are short-circuited together by an NMOS transistor (M7), and an input voltage (Vin_com) is added to the first operational amplifier through an NMOS transistor (M5) and an NMOS transistor (M6). positive and negative input terminals of an operational amplifier; The positive and negative output ends of the first operational amplifier are short-circuited together by an NMOS transistor (M8), which is used to reset the output of the first operational amplifier; The first bootstrap switch (S1) and the second bootstrap switch (S2) output corresponding control signals to turn on an NMOS transistor (M1) and an NMOS transistor (M2) which function as switches, so that the nineteenth capacitor (C19) , The seventeenth capacitor (C17) is connected to the positive input signal, the twentieth capacitor (C20) and the eighteenth capacitor (C18) are connected to the negative input signal; The transmission gate transmits the signal at the input terminal to the output terminal or disconnects it from the output terminal according to the high and low levels of the control signal; The first bootstrap switch and the second bootstrap switch are reset, and the output signal is low level, so that the source and drain of an NMOS transistor (M1) and an NMOS transistor (M2) are disconnected; The third bootstrap switch (S3) and the fourth bootstrap switch (S4) output effective control signals, so that an NMOS transistor (M3) and another NMOS transistor (M4) that function as switches are turned on, and the The lower plates of the seventeenth capacitor (C17), the nineteenth capacitor (C19), the eighteenth capacitor (C18), and the twentieth capacitor (C20) are respectively connected to the first operational amplifier The negative and positive output terminals are connected; When the first operational amplifier is working normally, the sampled signal is held and output to the input end of the multi-digit digital-to-analog converter at the first stage of the pipeline. 3. The analog-to-digital converter according to claim 1, characterized in that, the first-stage multi-digit digital-to-analog converter of the pipeline comprises: a second operational amplifier (A1), 10 transmission gates, and 64 switch arrays , capacitors and 32 output controllable comparators; Wherein, the positive and negative input ends of the second operational amplifier (A1) are short-circuited together through an NMOS transistor (M62), and the second operational amplifier A1 is connected through an NMOS transistor (M60) and an NMOS transistor (M61). The input terminal of the input common mode reference level Vcom1 is added; the output terminal of the second operational amplifier (A1) is short-circuited together by an NMOS transistor (M77), which acts on the output of the second operational amplifier (A1) With the role of reset; The 32 output controllable comparators realize the sampling of the input signal; Under the control of the control signal, the transmission gate grounds one end of the capacitor connected to the transmission gate or connects to the input common-mode reference level; The output of the switch array is determined by the output of the output controllable comparator. 4. The analog-to-digital converter according to claim 3, wherein the first-stage multi-digit digital-to-analog converter of the pipeline further comprises: The encoding circuit is used for encoding the output of the output controllable comparator. 5. The analog-to-digital converter according to claim 1, characterized in that, the second-stage multi-digit digital-to-analog converter of the pipeline comprises: a third operational amplifier (A2), 8 transmission gates, and 32 switch arrays , capacitors and 16 output controllable comparators; The positive and negative input ends of the third operational amplifier (A2) are short-circuited together through an NMOS transistor (M86), and the input common-mode reference voltage (Vcom2) is added through an NMOS transistor (M84) and an NMOS transistor (M85) , the positive and negative output terminals are also shorted together through an NMOS transistor (M106); The 16 output controllable comparators realize the sampling of the input signal; Under the control of the control signal, the eight transmission gates ground one end of the capacitor connected to the transmission gates or connect to the input common mode reference level; The output of the switch array is determined by the output of the output controllable comparator. 6. The analog-to-digital converter according to claim 5, wherein the second-stage multi-digit digital-to-analog converter of the pipeline further comprises: 16 positive calibration error storage circuits for storing errors caused by capacitance mismatch associated with the 16 output controllable comparators in the first stage multi-digit digital-to-analog converter; Sixteen negative calibration error storage circuits are used to store errors caused by capacitance mismatches associated with the other 16 output controllable comparators in the first-stage multi-digit digital-to-analog converter. 7. The analog-to-digital converter according to claim 1, wherein the third-stage multi-digit digital-to-analog converter of the pipeline includes: a third operational amplifier (A3), 18 switch arrays, capacitors, and 17 output controllable comparator; The positive and negative input terminals of the third operational amplifier (A3) are short-circuited together by an NMOS transistor (M124), and the input common-mode reference voltage Vcom3 is added through an NMOS transistor (M122) and an NMOS transistor (M123). The negative output terminals are shorted together through an NMOS transistor (M128); The 17 output controllable comparators realize the sampling of the input signal; The output of the switch array is determined by the output of the output controllable comparator. 8. The analog-to-digital converter according to claim 7, wherein the third-stage multi-digit digital-to-analog converter of the pipeline further comprises: nine positive calibration error storage circuits for storing errors caused by capacitance mismatches associated with the nine output controllable comparators in the second stage multi-digit digital-to-analog converter; Eight negative calibration error storage circuits for storing errors caused by capacitance mismatches associated with the other eight output controllable comparators in the second stage of the multi-digit digital-to-analog converter. 9. The analog-to-digital converter according to claim 8, characterized in that, the third-stage multi-digit digital-to-analog converter of the pipeline further comprises: an encoding circuit (E3), used to output the controllable comparator The output is encoded. 10. The analog-to-digital converter according to claim 1, characterized in that, the fourth-stage multi-digit digital-to-analog converter of the pipeline comprises: a fourth operational amplifier (A4), 20 switch arrays, capacitors, and 16 output controllable comparator; Wherein, the positive and negative input ends of the fourth operational amplifier (A4) are short-circuited together by an NMOS transistor (M144), and the input common-mode reference voltage Vcom4 is added through an NMOS transistor (M142) and an NMOS transistor (M143). , the positive and negative output terminals are shorted together through an NMOS transistor (M152); The 16 output controllable comparators realize the sampling of the input signal; The output of the switch array is determined by the output of the output controllable comparator. 11. The analog-to-digital converter according to claim 10, wherein the fourth-stage multi-digit digital-to-analog converter of the pipeline further comprises: an encoding circuit 4, which is used to encode the output of the output controllable comparator . 12. The analog-to-digital converter according to claim 1, wherein the fifth-stage flash analog-to-digital converter comprises: 7 comparators for sampling the input signal. 13. The analog-to-digital converter according to claim 12, wherein the fifth-stage flash analog-to-digital converter further comprises: an encoding circuit E5, configured to encode the output of the comparator. 14. The analog-to-digital converter according to claim 6 or 8, wherein the positive calibration error storage circuit comprises: 2 CMOS transmission gates, 4 inverters, a NAND gate, an OR gate, a current regulation circuit, 2 resistors, and 2 NMOS transistors; among them, The two CMOS transmission gates are connected sequentially, the first inverter (I1) of the four inverters is connected to the first transmission gate of the two CMOS transmission gates, and the second inverter (I2) is connected to the first transmission gate of the two CMOS transmission gates. Two transmission gates are connected, the first inverter is connected with the second inverter; the first inverter is also connected with the NAND gate, the NAND gate is connected with the NOR gate, and the NAND gate is connected The OR gate is connected to the third inverter, the third inverter is connected to the fourth inverter, the third inverter is connected to the current regulation circuit through the first MOS tube, and the current regulation circuit is connected to the current regulation circuit through a The resistor is grounded, the fourth inverter is grounded through a MOS transistor and the resistor, and the MOS transistor connected to the fourth inverter and the MOS transistor connected to the third inverter are connected to each other.