CN104104379B - A kind of logic level signal transmission method and device - Google Patents

Abstract

The present invention provides a logic level signal transmission method and device. The method includes: generating a superimposed logic level signal after superimposing the transmitted first logic level signal and the second logic level signal, and transmitting the superimposed logic level signal After that, it is separated into a third logic level signal and a fourth logic level signal, and the third logic level signal or the fourth logic level signal is received in response; the first logic level signal and the second logic level signal respectively The three logic level signal is the same as the fourth logic level signal, and the transmission of the second logic level signal is performed after the transmission of the first logic level signal is completed. In the present invention, two logic level signals are superimposed and then transmitted, and then separated into two logic level signals, so that two logic signals can be transmitted with one signal line, and the number of split hosts and display screens of the vehicle entertainment navigation system can be reduced. The number of pins between the connectors reduces the difficulty of structural design and improves the reliability of signal connections.

Description

A logic level signal transmission method and device

technical field

The present invention relates to the technical field of signal transmission, in particular to a logic level signal transmission method and device.

Background technique

In the current car entertainment navigation system, there are more and more split machines in which the main unit and the panel are separated, and the two are electrically connected by cables; generally, the main unit contains MCU and related circuits, and the panel contains MPU and related circuits. However, there are many signals connected to each other between the main unit and the panel of the split machine, including audio and video, control, communication and other signals, so that the pin PIN of the connector used must be enough, which makes it difficult to select the connector. The structural design also becomes complicated, which in turn reduces the reliability of the signal connection of the split machine.

Among the connection signals of the split machine, there are many signals that do not need to be transmitted at the same time. For example, the panel of the car entertainment navigation system is designed with a reset button. Reset the MCU and MPU as a whole to restore them to the normal state; at the same time, the MCU on the host also has a signal line to reset the MPU on the panel separately. The two reset signals are not transmitted at the same time, but in the existing technical solution, to realize the above two reset functions, two signal lines must be used to transmit the two reset signals.

Contents of the invention

The invention provides a logic level signal transmission method and device, which solves the technical problem of using one signal line to complete two logic level signal transmissions.

In order to achieve the above object, the technical scheme adopted in the present invention is:

One aspect of the present invention provides a logic level signal transmission method, which is characterized in that it includes:

superimposing the sent first logic level signal and the second logic level signal to generate a superimposed logic level signal, and separating the superimposed logic level signal into a third logic level signal and a fourth logic level signal after transmission signal, a third logic level signal or a fourth logic level signal is received in response;

The first logic level signal and the second logic level signal are respectively the same as the third logic level signal and the fourth logic level signal, and the transmission of the second logic level signal is performed after the transmission of the first logic level signal is completed.

Further, before the above logic level signal transmission step, it also includes:

configuring the sent first logic level signal and the second logic level signal to be a normal logic level;

Setting parameters so that the received third logic level signal and the fourth logic level signal are normal logic levels;

A valid logic level signal configured for response;

Controlling the first logic level signal or the second logic level signal to change from a normal logic level signal to an effective logic level signal.

After the above logic level signal transmission steps, also include:

Set the recovery time of the transmitted first or second logic level signal from an active logic level signal to a normal logic level signal and the response of the received third logic level signal or fourth logic level signal Interval time, the recovery time is less than or equal to the response interval time.

Another aspect of the present invention provides a logic level signal transmission device, including a first set of signal input and output interfaces, a logic level signal superposition circuit, a logic level signal separation circuit, and a second set of signal input and output interfaces;

The first group of signal input and output interfaces includes a first logic level signal output interface and a second logic level signal output interface, respectively connected to the first logic level signal input terminal and the second logic level signal of the logic level signal superposition circuit The input terminal is used to send the first logic level signal and the second logic level signal to the logic level signal superposition circuit;

A logic level signal superposition circuit, configured to superimpose the first logic level signal and the second logic level signal to generate a superimposed logic level signal, and transmit the superimposed logic level signal to the logic through the superimposed signal output terminal The superposition signal input terminal of the level signal separation circuit;

A logic level signal separation circuit, configured to separate the superimposed logic level signal into a third logic level signal and a fourth logic level signal, through the third logic level signal output terminal and the fourth logic level signal respectively output output;

The second group of signal input and output interfaces includes a third logic level signal input interface and a fourth logic level signal input interface, respectively connected to the third logic level signal output end and the fourth logic level signal of the logic level signal separation circuit The output terminal is used for receiving the third logic level signal or the fourth logic level signal in response.

Further, it also includes a first microcontroller and a second microcontroller;

The first microcontroller is used to configure the first group of signal input and output interfaces as the first logic level signal output interface and the second logic level signal output interface; The flat signal and the second logic level signal are normal logic levels, and then the first logic level signal or the second logic level signal is controlled to change from a normal logic level signal to an effective logic level signal;

The second microcontroller is configured to configure the second group of signal input and output interfaces as the third logic level signal input interface and the fourth logic level signal input interface; and configure an effective logic level for the response Signal.

Further, it also includes a first microcontroller and a second microcontroller;

The first micro-controller is used to set the recovery time for the sent first logic level signal or the second logic level signal to recover from an effective logic level signal to a normal logic level signal;

The second microcontroller is used to set the response interval time of the received valid logic level signal, the third logic level signal or the fourth logic level signal is an effective logic level signal;

The recovery time is set to be less than or equal to the response interval time.

Further, another structure of the logic level signal transmission device is:

The first group of signal input and output interfaces are connected to a switch, and the first logic sent by the switch is controlled

The level signal or the second logic level signal changes from a normal logic level signal to an effective logic level signal.

Further, the first logic level signal input terminal of the logic level signal superposition circuit is connected to the power supply through the first resistor, and grounded through the second resistor;

The second logic level signal input terminal of the logic level signal superposition circuit is connected to one end of the third resistor through the fourth resistor, and the other end of the third resistor is connected to the power supply;

The connecting end of the first resistor and the second resistor and the connecting end of the third resistor and the fourth resistor are connected as the superposition signal output terminal of the logic level signal superposition circuit.

Further, the superposition signal input end of the logic level signal separation circuit is connected to the superposition signal output end, and the logic level signal separation circuit has a first triode, a second triode, and a third triode ;

The superposition signal input end is connected to the emitter of the first triode, a fifth resistor is connected in series between the base of the first triode and the power supply, and a sixth resistor is connected in series between the base of the first triode and the ground. A resistor, a seventh resistor is connected in series between the collector of the first triode and the power supply, and the collector of the first triode is connected to the third logic level signal input interface;

The input terminal of the superposition signal is connected to the base of the third triode through the eighth resistor, the first capacitor is connected in parallel with the two ends of the eighth resistor, and the base of the third triode is grounded through the ninth resistor; the third The emitter of the triode is grounded; the collector of the third triode is connected to the base of the second triode, and the base of the second triode is connected to the superposition signal input terminal through the tenth resistor, and the second triode The base of the tube is grounded through the second capacitor; the emitter of the second triode is grounded; the collector of the second triode is connected to the power supply through the eleventh resistor, and the collector of the second triode is connected to the fourth logic Level signal input interface.

The present invention generates a superimposed logic level signal by superimposing two logic level signals, and then separates the superimposed logic level signal into two logic level signals after transmission, so as to realize the transmission of two logic signals with one signal line, The number of pins of the connector between the main unit of the car entertainment navigation system and the display screen is reduced, the difficulty of structural design is reduced, and the reliability of signal connection is improved.

Description of drawings

Fig. 1 is a schematic flow chart of the logic level signal transmission method of the present invention;

Fig. 2 is a schematic structural diagram of a logic level signal transmission device of the present invention;

3 is a schematic diagram of the circuit structure of the logic level signal transmission device of the present invention;

FIG. 4 is a schematic structural diagram of another embodiment of the logic level signal transmission device of the present invention.

detailed description

The implementation of the present invention will be described in detail below in conjunction with the accompanying drawings. The accompanying drawings are only for reference and description, and do not constitute a limitation to the protection scope of the present invention.

Example 1:

As shown in FIG. 1 , this embodiment provides a logic level signal transmission method, including: generating a superimposed logic level signal after superimposing the transmitted first logic level signal and a second logic level signal, and The superimposed logic level signal is separated into a third logic level signal and a fourth logic level signal after transmission, and the third logic level signal or the fourth logic level signal is received in response;

The first logic level signal and the second logic level signal are respectively the same as the third logic level signal and the fourth logic level signal, and the transmission of the second logic level signal is performed after the transmission of the first logic level signal is completed.

In an embodiment of the present invention, before the above logic level signal transmission step, it also includes:

The first logic level signal and the second logic level signal configured to be sent are normal logic levels; in this embodiment, by configuring the first group of signal input and output interfaces and the second group of signal input and output interfaces as floating ) state to achieve;

Parameters are set so that the received third logic level signal and the fourth logic level signal are normal logic levels; in this embodiment, the normal state of the received two logic level signals is high level;

Configure an effective logic level signal for response; in this embodiment, respond only when the logic level changes from high level to low level, and the effective logic level is low level;

Controlling the first logic level signal or the second logic level signal to change from a normal logic level signal to an effective logic level signal. In this embodiment, it is realized by pulling down the first group of signal input and output interfaces or the second group of signal input and output interfaces.

In an embodiment of the present invention, after the above logic level signal transmission step, further includes:

The first microprocessor sets the recovery time t2 for the first logic level signal or the second logic level signal sent by the effective logic level signal to the normal logic level signal, and the second microprocessor sets the third logic level signal received The response interval time t1 of the level signal or the fourth logic level signal, the recovery time t2 is less than or equal to the response interval time t1. In this embodiment, the input of the third logic level signal or the fourth logic level signal is ignored within the response interval time t1 after the input of the third logic level signal or the fourth logic level signal; It will return to the normal state within the recovery time t2 after outputting the low level.

The logic level signal transmission method provided in this embodiment can be applied to a car entertainment navigation system in the form of a split machine, and is specifically used for signal transmission between the host and the panel of the split machine, such as the MCU on the host and the panel on the panel. The transmission of the reset signal to reset the MPU as a whole and the reset signal to reset the MPU on the panel alone can be transmitted successively through one signal line in this embodiment, instead of at the same time.

In this embodiment, the superimposed logic level signal is generated by superimposing the first logic level signal and the second logic level signal, and then the superimposed logic level signal is separated into a third logic level signal and a fourth logic level signal after transmission. Flat signal, realize the transmission of two logic signals with one signal line, reduce the number of PIN pins of the connector between the split machine host and the display screen of the car entertainment navigation system, reduce the difficulty of structural design, and improve the reliability of signal connection .

Example 2:

As shown in FIG. 2, this embodiment provides a logic level signal transmission device, including a first set of signal input and output interfaces, a logic level signal superposition circuit, a logic level signal separation circuit, and a second set of signal input and output interfaces;

The first group of signal input and output interfaces includes a first logic level signal output interface I/O11 and a second logic level signal output interface I/O12, respectively connected to the first logic level signal input terminal and the logic level signal superposition circuit of the logic level signal The second logic level signal input terminal is used to send the first logic level signal and the second logic level signal to the logic level signal superposition circuit;

A logic level signal superposition circuit, configured to superimpose the first logic level signal and the second logic level signal to generate a superimposed logic level signal, and transmit the superimposed logic level signal to the logic through the superimposed signal output terminal The superposition signal input terminal of the level signal separation circuit;

A logic level signal separation circuit, configured to separate the superimposed logic level signal into a third logic level signal and a fourth logic level signal, through the third logic level signal output terminal and the fourth logic level signal respectively output output;

The second group of signal input and output interfaces includes a third logic level signal input interface I/O21 and a fourth logic level signal input interface I/O22, which are respectively connected to the third logic level signal output terminal and the logic level signal separation circuit of the logic level signal separation circuit. The fourth logic level signal output end is used for receiving the third logic level signal or the fourth logic level signal in response.

As shown in Figure 2, in an embodiment of the present invention, a first microcontroller and a second microcontroller are also included;

The first microcontroller is used to configure the first group of signal input and output interfaces as the first logic level signal output interface I/O11 and the second logic level signal output interface I/O12; and is used to configure first The first logic level signal A1 and the second logic level signal B1 sent are normal logic level, and then control the first logic level signal A1 or the second logic level signal B1 from normal logic level signal to effective logic Level signal;

The second microcontroller is configured to configure the second group of signal input and output interfaces as the third logic level signal input interface I/O21 and the fourth logic level signal input interface I/O22; and configured for Active logic level signal for the response.

In this embodiment, a first microcontroller and a second microcontroller are also included;

The first microcontroller is used to set the recovery time for the sent first logic level signal A1 or the second logic level signal A2 to recover from an effective logic level signal to a normal logic level signal;

The second microcontroller is used to set the response interval time of the received effective logic level signal, the third logic level signal A2 or the fourth logic level signal B2 is an effective logic level signal;

The recovery time is set to be less than or equal to the response interval time.

In this embodiment, as shown in FIG. 2, the first microcontroller, the first group of signal input and output interfaces I/O11, I/O12, and logic level signal superposition circuit belong to the sending end; the logic level The signal separation circuit, the second group of signal input and output interfaces I/O21, I/O22, and the second microcontroller belong to the receiving end.

As shown in FIG. 3, in an embodiment of the present invention, the first logic level signal input terminal of the logic level signal superposition circuit is connected to the power supply through the first resistor R11, and grounded through the second resistor R12;

The second logic level signal input terminal of the logic level signal superposition circuit is connected to one end of the third resistor R13 through the fourth resistor R14, and the other end of the third resistor R13 is connected to the power supply;

The connecting end of the first resistor R11 and the second resistor R12 and the connecting end of the third resistor R13 and the fourth resistor R14 are connected as the superposition signal output terminal of the logic level signal superposition circuit.

As shown in Figure 3, in an embodiment of the present invention, the superposition signal input terminal of the logic level signal separation circuit is connected to the superposition signal output terminal, and the logic level signal separation circuit has a first triode Q21 , the second triode Q22, the third triode Q23;

The superposition signal input terminal is connected to the emitter of the first triode Q21, the fifth resistor R21 is connected in series between the base of the first triode Q21 and the power supply, and the base of the first triode Q21 and the ground A sixth resistor R22 is connected in series, a seventh resistor R23 is connected in series between the collector of the first transistor Q21 and the power supply, and the collector of the first transistor Q21 is connected to the third logic level signal input interface I/O21 ; The collector of the first triode Q21 is used as the third logic level signal output terminal.

The eighth resistor R24 at the input end of the superposition signal is connected to the base of the third transistor Q23, the two ends of the eighth resistor R24 are connected in parallel with the first capacitor C21, and the base of the third transistor Q23 is connected to the base of the third transistor Q23 through the ninth resistor R25 is grounded; the emitter of the third transistor Q23 is grounded; the collector of the third transistor Q23 is connected to the base of the second transistor Q22, and the base of the second transistor Q22 is connected to the The superimposed signal input terminal, the base of the second triode Q22 is grounded through the second capacitor C22; the emitter of the second triode Q22 is grounded; the collector of the second triode Q22 is connected to the power supply through the eleventh resistor R27 , the collector of the second transistor Q22 is connected to the fourth logic level signal input interface I/O22; the collector of the second transistor Q22 is used as the fourth logic level signal output terminal.

In Fig. 3, the triode selects the conduction threshold voltage to be greater than or equal to 0.7V.

The working process of the logic level signal transmission device provided in this embodiment is:

By configuring the first microcontroller, the normal state of the first group of signal input and output interfaces I/O11 and I/O12 is a floating (Floating) state; by configuring the second microcontroller, the second group of signal input and output interfaces I/O The state of O21 and I/O22 is input. In this embodiment, the power supply of the logic level signal superimposition circuit is 3.3V, so the output voltage of the superimposed signal output terminal (ie, node 1 in FIG. 2 ) is 3.3V, because the emitter voltage of the first triode Q21 That is, it is equal to the voltage of node 1, and the base voltage is 3.3V obtained after being divided by resistors R21 and R22, which is 1.05V, so the first triode Q21 is cut off, and the third logic level A2 is a high level of 3.3V; The base voltage of the triode Q23 is obtained by dividing the voltage of the node 1 through the resistors R24 and R25, which is 1.115V, so the third triode Q23 is turned on, so that the base of the second triode Q22 is grounded And when it is off, the fourth logic level B2 is a high level of 3.3V. This is the initial state of a logic level signaling device.

The working process of the logic level signal transmission device is described in the following cases:

Scenario 1:

The first microcontroller changes the first logic level signal output interface I/O11 from floating to low level 0, and the second logic level signal output interface I/O12 is in any state, then the superimposed signal output terminal (node 1) The voltage of the first triode Q21 is 0V, the emitter voltage of the first triode Q21 is equal to the voltage of node 1, and the base voltage is 3.3V obtained by dividing the voltage by the resistors R21 and R22, which is 1.05V, so that the first triode Q21 is turned on, the third logic level A2 changes from the original high level 3.3V to low level 0V, the base voltage of the second transistor Q22 is 0V, so it is cut off, and the fourth logic level B2 remains high flat;

The second microcontroller judges that the input of the third logic level A2 is a valid input, and the input of the fourth logic level B2 is an invalid input; the second microcontroller no longer responds to the third logic level in the response interval time t1 (5ms). input of level A2;

The first microcontroller restores the state of the first logic level signal output interface I/O11 from the low level 0V to the suspended state within the recovery time t2 (5 ms). In this embodiment, the response interval time t1 is equal to the recovery time t2.

Scenario 2:

The first logic level signal output interface I/O11 remains in a floating state, and the first microcontroller changes the second logic level signal output interface I/O12 from floating to low level 0, and the superimposed signal output terminal (node 1) The voltage of 3.3V is obtained after dividing by resistors R13 and R14, which is 1.115V. The emitter voltage of the first triode Q21 is equal to the voltage of node 1, and the base voltage is obtained by dividing by resistors R21 and R22, which is 1.05 V, so the first triode Q21 is cut off, and the third logic level A2 remains high; the base voltage of the third triode Q23 is obtained by dividing the voltage of node 1 by resistors R24 and R25, which is 0.377 V, so the third transistor Q23 is cut off, and the base voltage of the second transistor Q22 is 1.115V, so that the second transistor Q22 is turned on, and the fourth logic level B2 is changed from the original high level 3.3 V becomes low level 0V;

The second microcontroller judges that the input of the fourth logic level B2 is a valid input, and the input of the third logic level A2 is an invalid input; the second microcontroller no longer responds to the fourth logic level in the response interval time t1 (5ms). input of level B2;

The first microcontroller restores the state of the second logic level signal output interface I/O12 from the low level 0V to the suspended state within the recovery time t2 (5 ms). In this embodiment, the response interval time t1 is equal to the recovery time t2.

Example 3:

In this embodiment, as shown in FIG. 4, the difference between this embodiment and Embodiment 2 is that another structure of the logic level signal transmission device is provided:

The first group of signal input and output interfaces are connected to a switch S11, and the first logic level signal or the second logic level signal sent through the switch S11 is controlled to change from a normal logic level signal to an effective logic level signal.

The logic level signal transmission device provided in this embodiment can be applied to a car entertainment navigation system in the form of a split machine, specifically for signal transmission between the host and the panel of the split machine, such as the MCU on the host and the panel The transmission of the mechanical reset signal for the overall reset of the MPU and the software reset signal for the MPU reset on the panel is transmitted successively by using one signal line in this embodiment, and does not need to be transmitted at the same time.

As shown in FIG. 4 , in this embodiment, the switch S11 is a mechanical switch, and when pressed, the end connected to the resistor R11 and R12 is grounded, thereby generating a low-level reset signal.

In Fig. 4, the triode selects the conduction threshold voltage to be greater than or equal to 0.7V.

The reset signal can be set as low level or high level active according to the actual needs of the system. In this embodiment, the reset signal is set to be active at low level.

In this embodiment, the first logic level signal is the mechanical reset signal A1, the second logic level signal is the software reset signal B1, the third logic level signal is the mechanical reset signal A2, and the fourth logic level signal is the software reset signal A2. Reset signal B2.

The working process of the logic level signal transmission device of this embodiment is:

1) The initial state of the circuit: when both the mechanical reset signal A1 and the software reset signal B1 are invalid (that is, the high level is 3.3V), the voltage of node 1 is 3.3V, since the emitter voltage of the first triode Q21 is equal to the node 1 voltage, the base voltage is 3.3V obtained by dividing the voltage by resistors R21 and R22, which is 1.05V, so the first triode Q21 is cut off, and the mechanical reset signal A2 is at high level; the base of the third triode Q23 The pole voltage is obtained by dividing the voltage of node 1 by resistors R24 and R25, which is 1.115V, so the third transistor Q23 is turned on, so that the base of the second transistor Q22 is grounded and cut off, and the software reset signal B2 is high level.

2) When the mechanical reset signal A1 is valid: the mechanical reset signal A1 changes from a high level of 3.3V to a low level of 0V, then the voltage of node 1 is 0V, and the emitter voltage of the first triode Q21 is equal to the voltage of node 1. The base voltage is 3.3V obtained by dividing the voltage by resistors R21 and R22, which is 1.05V, so the first triode Q21 is turned on, and the reset signal A2 changes from the original high level 3.3V to low level 0V; The base voltage of the transistor Q22 is 0V, so it is cut off, and the software reset signal B2 remains at a high level.

3) When the software reset signal B1 is valid: the software reset signal B1 changes from a high level of 3.3V to a low level of 0V, then the voltage of node 1 is 3.3V obtained by dividing the voltage by resistors R13 and R14, which is 1.115V, the first The emitter voltage of the triode Q21 is equal to the voltage of node 1, and the base voltage is obtained after being divided by the resistors R21 and R22, which is 1.05V, so the first triode Q21 is cut off, and the mechanical reset signal A2 is at a high level; The base voltage of the triode Q23 is obtained by dividing the voltage of the node 1 through the resistors R24 and R25, which is 0.377V, so Q23 is cut off, and the base voltage of Q22 is 1.115V, so it is turned on, and the software resets the signal B2 is low level.

The above disclosures are only preferred embodiments of the present invention, and cannot be used to limit the protection scope of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention still fall within the scope of the present invention.

Claims (7)

1. A logic level signal transmission method, characterized in that, comprising: superimposing the sent first logic level signal and the second logic level signal to generate a superimposed logic level signal, and separating the superimposed logic level signal into a third logic level signal and a fourth logic level signal after transmission signal, a third logic level signal or a fourth logic level signal is received in response; The first logic level signal and the second logic level signal are respectively the same as the third logic level signal and the fourth logic level signal, and the transmission of the second logic level signal is performed after the transmission of the first logic level signal is completed: Before the above steps, also include: configuring the sent first logic level signal and the second logic level signal to be a normal logic level; Setting parameters so that the received third logic level signal and the fourth logic level signal are normal logic levels; A valid logic level signal configured for response; Controlling the first logic level signal or the second logic level signal to change from a normal logic level signal to an effective logic level signal. 2. The logic level signal transmission method according to claim 1, characterized in that: After the above steps, also include: Set the recovery time of the transmitted first or second logic level signal from an active logic level signal to a normal logic level signal and the response of the received third logic level signal or fourth logic level signal Interval time, the recovery time is less than or equal to the response interval time. 3. A logic level signal transmission device, characterized in that: comprising a first group of signal input and output interfaces, a logic level signal superposition circuit, a logic level signal separation circuit, and a second group of signal input and output interfaces; The first group of signal input and output interfaces includes a first logic level signal output interface and a second logic level signal output interface, respectively connected to the first logic level signal input terminal and the second logic level signal of the logic level signal superposition circuit The input terminal is used to send the first logic level signal and the second logic level signal to the logic level signal superposition circuit; A logic level signal superposition circuit, configured to superimpose the first logic level signal and the second logic level signal to generate a superimposed logic level signal, and transmit the superimposed logic level signal to the logic through the superimposed signal output terminal The superposition signal input terminal of the level signal separation circuit; A logic level signal separation circuit, configured to separate the superimposed logic level signal into a third logic level signal and a fourth logic level signal, through the third logic level signal output terminal and the fourth logic level signal respectively output output; The second group of signal input and output interfaces includes a third logic level signal input interface and a fourth logic level signal input interface, respectively connected to the third logic level signal output end and the fourth logic level signal of the logic level signal separation circuit An output responsive to receiving a third logic level signal or a fourth logic level signal: Also including a first microcontroller and a second microcontroller; The first microcontroller is used to configure the first group of signal input and output interfaces as the first logic level signal output interface and the second logic level signal output interface; The flat signal and the second logic level signal are normal logic levels, and then the first logic level signal or the second logic level signal is controlled to change from a normal logic level signal to an effective logic level signal; The second microcontroller is configured to configure the second group of signal input and output interfaces as the third logic level signal input interface and the fourth logic level signal input interface; and configure an effective logic level for the response Signal. 4. The logic level signal transmission device according to claim 3, characterized in that: The first micro-controller is used to set the recovery time for the sent first logic level signal or the second logic level signal to recover from an effective logic level signal to a normal logic level signal; The second microcontroller is used to set the response interval time of the received valid logic level signal, the third logic level signal or the fourth logic level signal is an effective logic level signal; The recovery time is set to be less than or equal to the response interval time. 5. The logic level signal transmission device according to claim 3, characterized in that: The first group of signal input and output interfaces is connected to a switch, and the first logic level signal or the second logic level signal sent through the switch is controlled to change from a normal logic level signal to an effective logic level signal. 6. The logic level signal transmission device according to any one of the preceding claims 3-5, characterized in that: The first logic level signal input terminal of the logic level signal superposition circuit is connected to the power supply through the first resistor (R11), and grounded through the second resistor (R12); The second logic level signal input end of the logic level signal superposition circuit is connected to one end of the third resistor (R13) through the fourth resistor (R14), and the other end of the third resistor (R13) is connected to the power supply; The connecting end of the first resistor (R11) and the second resistor (R12) and the connecting end of the third resistor (R13) and the fourth resistor (R14) are connected as the superposition signal output terminal of the logic level signal superposition circuit. 7. The logic level signal transmission device according to any one of claims 3-5, characterized in that: The superposition signal input end of the logic level signal separation circuit is connected to the superposition signal output end, and the logic level signal separation circuit has a first triode (Q21), a second triode (Q22), a third Transistor (Q23); The superposition signal input end is connected to the emitter of the first triode (Q21), and a fifth resistor (R21) is connected in series between the base of the first triode (Q21) and the power supply, and the first triode (Q21) A sixth resistor (R22) is connected in series between the base of ) and ground, a seventh resistor (R23) is connected in series between the collector of the first transistor (Q21) and the power supply, and the first transistor (Q21) The collector is connected to the third logic level signal input interface; The superposition signal input end is connected to the base of the third triode (Q23) through the eighth resistor (R24), the first capacitor (C21) is connected in parallel to the two ends of the eighth resistor (R24), and the third triode The base of the tube (Q23) is grounded through the ninth resistor (R25); the emitter of the third transistor (Q23) is grounded; the collector of the third transistor (Q23) is connected to the second transistor (Q22) Base, the base of the second triode (Q22) is connected to the superposition signal input terminal through the tenth resistor (R26), and the base of the second triode (Q22) is grounded through the second capacitor (C22); The emitter of the second transistor (Q22) is grounded; the collector of the second transistor (Q22) is connected to the power supply through the eleventh resistor (R27), and the collector of the second transistor (Q22) is connected to the fourth Logic level signal input interface.