CN104113337B - A kind of production line analog-digital converter - Google Patents

Abstract

The present invention provides a pipeline analog-to-digital converter, which includes: a first pipeline stage, a seven-stage second pipeline stage, and a third pipeline stage connected step by stage; and the first pipeline stage, the first pipeline stage, The digital correction circuit connected respectively to the second pipeline stage of the seven stages and the third pipeline stage of the first stage; and the first pipeline stage of the first stage, the second pipeline stage of the seven stages, and the third pipeline stage of the first stage stage and the digital correction circuit are respectively connected to provide two-phase non-overlapping clock control signals for the first pipeline stage, the second pipeline stage, the third pipeline stage and the digital correction circuit respectively the clock circuit. The solution of the invention reduces the power consumption of the system while ensuring the system performance of high speed and high linearity.

Description

A Pipeline Analog-to-Digital Converter

technical field

The invention relates to the field of integrated circuit design, in particular to a pipeline analog-to-digital converter.

Background technique

With the rapid development of semiconductor technology, analog-to-digital converters have been widely used in data communications, military radar and other fields, and these systems have higher and higher performance requirements for analog-to-digital converters. While pursuing high speed and high precision, the analog-to-digital converter is required to have lower power consumption. The performance of the analog-to-digital converter plays an extremely important role in the whole system, so it is of great significance to design a high-performance analog-to-digital converter.

Among the analog-to-digital converters with many structures, the pipelined analog-to-digital converter has the advantages of high speed and high precision at the same time, and has become the first choice in high-speed and high-precision applications. In practical applications, how to reduce the power consumption of the system has become a research hotspot under the premise of ensuring the speed and precision performance of the pipeline structure analog-to-digital converter.

The front end of the traditional pipeline analog-to-digital A/D converter has a sample-and-hold circuit, and the sample-and-hold circuit is used as a front-end circuit for non-quantized signals, which will reduce the linearity and signal-to-noise ratio of the system. Secondly, as the level with the highest requirements for precision and linearity, the sample-and-hold circuit accounts for considerable power consumption and area of the entire system. In order to reduce power consumption and area, no sampling and holding circuit structure is adopted, but this also increases the design difficulty of the first-stage multiplication digital-to-analog converter.

Contents of the invention

The purpose of the present invention is to provide a pipelined analog-to-digital converter, which can solve the problem that the front-end of the current analog-to-digital converter has a sample-and-hold circuit. The design of the sample-and-hold circuit increases the power consumption of the system.

In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a pipelined analog-to-digital converter, which includes: a first pipeline stage connected in stages for quantizing signals and outputting quantized signals, and a seven-stage second pipeline stage Pipeline level, first level and third pipeline level;

It is respectively connected with the first pipeline stage of the one stage, the second pipeline stage of the seven stages, and the third pipeline stage of the one stage, and is used to output quantized signals to the first pipeline stage of the one stage, and the first pipeline stage of the seven stages The quantized signal output by the second pipeline stage and the quantized signal output by the third pipeline stage of the first stage are subjected to delay alignment and dislocation addition processing, and a digital correction circuit for outputting the processed quantized signal;

It is respectively connected with the first pipeline stage of the first stage, the second pipeline stage of the seven stages, the third pipeline stage of the first stage and the digital correction circuit, and is used to provide the first pipeline stage of the first stage and the first pipeline stage of the first stage respectively. The seven-stage second pipeline stage, the one-stage third pipeline stage and the digital correction circuit provide a clock circuit with two-phase non-overlapping clock control signals.

Wherein, the first pipeline stage includes a first multiplying digital-to-analog converter, a dynamic element matching circuit for dynamically randomly selecting the sampling capacitor array in the first multiplying digital-to-analog converter, and a first sub-analog-to-digital converter; Wherein, the first sub-analog-to-digital converter includes a first differential input terminal, a second differential input terminal, a first differential output terminal, and a second differential output terminal; the dynamic element matching circuit includes a third differential input terminal, a second differential input terminal, Four differential input terminals, a third differential output terminal and a fourth differential output terminal; the first multiplication digital-to-analog converter includes a fifth differential input terminal, a sixth differential input terminal, a fifth differential output terminal and a sixth differential output terminal ; Wherein, the first differential input terminal is connected to the first differential voltage of the analog-to-digital converter, and the second differential input terminal is connected to the second differential voltage of the analog-to-digital converter; the first differential output terminal is connected to the first differential voltage of the analog-to-digital converter Three differential input terminals are connected, the second differential output terminal is connected to the fourth differential input terminal; the first differential output terminal is connected to the digital correction circuit; the third differential output terminal is connected to the fifth differential output terminal. The differential input terminal is connected, and the fourth differential output terminal is connected to the sixth differential input terminal.

Wherein, the second pipeline stage of the seven stages is respectively: the second pipeline stage of the first stage, the second pipeline stage of the second stage, the second pipeline stage of the third stage, the second pipeline stage of the fourth stage, and the second pipeline stage of the fifth stage. Pipeline stage, the sixth stage and the second pipeline stage, the seventh stage and the second pipeline stage; wherein, the second pipeline stage of each level includes a second sub-analog converter and a second multiplication digital-to-analog converter;

Wherein, the second sub-digital-to-analog converter includes a seventh differential input terminal, an eighth differential input terminal, a seventh differential output terminal, and an eighth differential output terminal; the second multiplication digital-to-analog converter includes: a ninth differential input terminal, a tenth differential input terminal, a ninth differential output terminal and a tenth differential output terminal; the seventh differential output terminal is connected to the digital correction circuit; the seventh differential output terminal is connected to the ninth differential output terminal connected to the input terminal; the eighth differential output terminal is connected to the tenth differential input terminal;

Wherein, the seventh differential input terminal of the second sub-analog-to-digital converter of the second pipeline stage of the first stage is connected to the fifth differential output terminal, and the second pipeline stage of the first stage is connected to the fifth differential output terminal. The eighth differential input terminal of the second sub-analog-to-digital converter is connected to the sixth differential output terminal; The differential input terminals are all connected to the ninth differential output terminal of the second multiplication digital-to-analog converter of the second pipeline stage of the previous stage, and the second sub-analog-to-digital conversion of the second pipeline stage of each subsequent stage The eighth differential input terminals of the converters are all connected to the tenth differential output terminals of the second multiplying digital-to-analog converter in the second pipeline stage of the previous stage.

Wherein, the third pipeline stage includes:

The third sub-digital-to-analog converter; wherein, the third sub-digital-to-analog converter includes an eleventh differential input terminal, a twelfth differential input terminal, an eleventh differential output terminal, and a twelfth differential output terminal; the The eleventh differential input terminal is connected to the ninth differential output terminal of the second multiplying digital-to-analog converter in the second pipeline stage of the seventh stage, and the twelfth differential input terminal is connected to the seventh differential input terminal. The tenth differential output terminal of the second multiplying digital-to-analog converter in the second pipeline stage is connected; the eleventh differential output terminal is connected to the digital correction circuit.

Wherein, the first sub-analog-to-digital converter is composed of fourteen first comparators; wherein, each first comparator includes: a first-stage pre-amplifier, a second-stage pre-amplifier, and a first latch; The first stage pre-amplifier includes a first non-inverting input end, a first inverting input end, a first non-inverting output end and a first inverting output end; the second stage pre-amplifier includes a second non-inverting input end, a first non-inverting input end Two inverting input terminals, a second non-inverting output terminal and a second inverting output terminal; the first latch includes a thirteenth differential input terminal, a fourteenth differential input terminal, a thirteenth differential output terminal, and a tenth differential input terminal. Four differential output terminals; the first inverting output terminal is connected to the second non-inverting input terminal, and the first non-inverting output terminal is connected to the second inverting input and output terminal; the second inverting output terminal is connected connected to the thirteenth differential input terminal, and the second non-inverting output terminal is connected to the fourteenth differential input terminal; the thirteenth differential input terminal of the first latch in each first comparator The output terminal is connected to the first differential output terminal, and the fourteenth differential output terminal of the first latch of each first comparator is connected to the second differential output terminal; The phase input terminal is connected to the first inverting output terminal through a first clock switch; the first inverting input terminal is connected to the first non-inverting output terminal through the first clock switch; each first comparison The first non-inverting input terminal of the device is connected to the first differential input terminal through the second clock switch through the first capacitor and connected to the first reference voltage through the first capacitor through the first clock switch; The first inverting input terminal of a first comparator is connected to the second differential input terminal through the second capacitor through the second clock switch, and is connected to the second reference voltage through the second capacitor through the first A clock switch connection.

Wherein, the first multiplication digital-to-analog converter is composed of:

The first multiplying digital-to-analog converter consists of:

The third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor, the seventh capacitor, the eighth capacitor, the ninth capacitor, the tenth capacitor, the eleventh capacitor, the twelfth capacitor, the thirteenth capacitor, the fourteenth capacitor Capacitor, fifteenth capacitor, sixteenth capacitor, seventeenth capacitor, eighteenth capacitor, nineteenth capacitor, twentieth capacitor, twenty-first capacitor, twenty-second capacitor, twenty-third capacitor, The twenty-fourth capacitor, the twenty-fifth capacitor, the twenty-sixth capacitor, the twenty-seventh capacitor, the twenty-eighth capacitor, the twenty-ninth capacitor, the thirtieth capacitor, the thirty-first capacitor, the thirty-first capacitor The second capacitor, the thirty-third capacitor, the thirty-fourth capacitor, the thirty-fifth capacitor, the thirty-sixth capacitor, the thirty-seventh capacitor, the thirty-eighth capacitor and the first operational amplifier; wherein, the first operational amplifier An operational amplifier includes a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal; the non-inverting output terminal and the inverting output terminal are connected through a first clock switch; the non-inverting input terminal Both the inverting input terminal and the common-mode voltage are connected through a third clock switch; the non-inverting output terminal is connected to the fifth differential output terminal; the inverting output terminal is connected to the sixth differential output terminal;

The first end of the third capacitor, the first end of the fourth capacitor, the first end of the fifth capacitor, the first end of the sixth capacitor, the first end of the seventh capacitor, The first end of the eighth capacitor, the first end of the ninth capacitor, the first end of the tenth capacitor, the first end of the eleventh capacitor, the first end of the twelfth capacitor end, the first end of the thirteenth capacitor, the first end of the fourteenth capacitor, the first end of the fifteenth capacitor, the first end of the sixteenth capacitor, the tenth capacitor The first end of the seventh capacitor, the first end of the eighteenth capacitor, the first end of the nineteenth capacitor, and the first end of the twentieth capacitor are connected to the non-inverting input terminal through a common connection line connection; the second end of the third capacitor, the second end of the fourth capacitor, the second end of the fifth capacitor, the second end of the sixth capacitor, the second end of the seventh capacitor end, the second end of the eighth capacitor, the second end of the ninth capacitor, the second end of the tenth capacitor, the second end of the eleventh capacitor, the second end of the twelfth capacitor The second end, the second end of the thirteenth capacitor, the second end of the fourteenth capacitor, the second end of the fifteenth capacitor, the second end of the sixteenth capacitor, the The second end of the seventeenth capacitor, the second end of the eighteenth capacitor, the second end of the nineteenth capacitor, and the second end of the twentieth capacitor are respectively connected to the fifth differential input end connected through the first clock switch, respectively connected to the first reference voltage through the first clock switch, respectively connected to the second reference voltage through the first clock switch, respectively connected to the inverting output terminal through the second clock switch connect;

The first end of the twenty-first capacitor, the first end of the twenty-second capacitor, the first end of the twenty-third capacitor, the first end of the twenty-fourth capacitor, the The first end of the twenty-fifth capacitor, the first end of the twenty-sixth capacitor, the first end of the twenty-seventh capacitor, the first end of the twenty-eighth capacitor, the second The first end of the nineteenth capacitor, the first end of the thirtieth capacitor, the first end of the thirty-first capacitor, the first end of the thirty-second capacitor, the thirty-third capacitor The first end of the thirty-fourth capacitor, the first end of the thirty-fifth capacitor, the first end of the thirty-sixth capacitor, the first end of the thirty-seventh capacitor One end and the first end of the thirty-eighth capacitor are connected to the inverting input end through a common connection line; the second end of the twenty-first capacitor, the second end of the twenty-second capacitor end, the second end of the twenty-third capacitor, the second end of the twenty-fourth capacitor, the second end of the twenty-fifth capacitor, the second end of the twenty-sixth capacitor, The second end of the twenty-seventh capacitor, the second end of the twenty-eighth capacitor, the second end of the twenty-ninth capacitor, the second end of the thirtieth capacitor, the second end of the first The second end of the thirty-first capacitor, the second end of the thirty-second capacitor, the second end of the thirty-third capacitor, the second end of the thirty-fourth capacitor, the thirty-second capacitor The second end of the fifth capacitor, the second end of the thirty-sixth capacitor, the second end of the thirty-seventh capacitor, and the second end of the thirty-eighth capacitor are respectively connected to the sixth differential input connected to the first reference voltage through the first clock switch, respectively connected to the second reference voltage through the first clock switch, respectively connected to the non-inverting output terminals are connected through the second clock switch.

Wherein, the second sub-analog-to-digital converters in the second pipeline stages of each level are composed of two second comparators; wherein, each second comparator includes: a third pre-amplifier, a fourth pre-amplifier and a second A latch; the third pre-amplifier includes a second non-inverting input end, a second inverting input end, a second non-inverting output end and a second inverting output end; the fourth pre-amplifier includes a third non-inverting input end, The third inverting input terminal, the third non-inverting output terminal and the third inverting output terminal; the second latch includes a fifteenth differential input terminal, a sixteenth differential input terminal, a fifteenth differential output terminal, a first Sixteen differential output terminals; the second inverting output terminal is connected to the third non-inverting input terminal, and the second non-inverting output terminal is connected to the third inverting input terminal; the third inverting output terminal connected to the fifteenth differential input terminal, and the third non-inverting output terminal is connected to the sixteenth differential input terminal;

Wherein, the second non-inverting input terminal of the third pre-amplifier in each second comparator is connected to the seventh differential input terminal through a second clock switch through a thirty-ninth capacitor, and through the third The nineteenth capacitor is connected to the first reference voltage through the first clock switch; the second inverting input terminal of the third pre-amplifier in each second comparator is connected to the eighth differential input terminal through the fortieth capacitor Connected through the second clock switch, and connected with the second reference voltage through the fortieth capacitor through the first clock switch; the tenth of the second latch in each second comparator The fifth differential output terminal is connected to the seventh differential output terminal; the sixteenth differential output terminal of the second latch in each second comparator is connected to the eighth differential output terminal.

Wherein, the second multiplying digital-to-analog converter in the second pipeline stage of each level is composed of a first one-out-of-three selector, a second one-out-of-three selector, a second operational amplifier, a third operational amplifier, a fourth Composed of eleven capacitors, forty-second capacitors, forty-third capacitors, and forty-fourth capacitors;

Wherein, the first three-choice selector includes: a seventeenth differential input terminal, an eighteenth differential input terminal, a nineteenth differential input terminal, a first control terminal, and a seventeenth differential output terminal; the second The one-out-of-three selector includes: a twentieth differential input terminal, a twenty-first differential input terminal, a twenty-second differential input terminal, a second control terminal, and an eighteenth differential output terminal; the second operational amplifier includes a first Four non-inverting input terminals, a fourth inverting input terminal and a nineteenth differential output terminal; the third operational amplifier includes a fifth non-inverting input terminal, a fifth inverting input terminal and a twentieth differential output terminal;

The seventeenth differential input terminal and the twentieth differential input terminal are respectively connected to the third reference voltage; the eighteenth differential input terminal and the twenty-first differential input terminal are respectively connected to the fourth reference voltage; the The nineteenth differential input terminal and the twenty-second differential input terminal are respectively connected to a low level;

The fourth non-inverting input terminal is connected to the common-mode voltage; the nineteenth differential output terminal is connected to the common-mode voltage through the first clock switch; the fourth inverting input terminal is respectively connected to the forty-first capacitor The first end of the forty-second capacitor is connected to the first end of the forty-second capacitor; the first end of the forty-second capacitor is also connected to the common mode voltage through the third clock switch; the fortieth The second end of a capacitor is connected to the nineteenth differential output end through the second clock switch; the second end of the forty-second capacitor is connected to the first end of the forty-first capacitor through the first clock switch The two terminals are connected; the second terminal of the forty-second capacitor is also connected to the seventeenth differential output terminal through the second clock switch; wherein, the second terminal of the forty-second capacitor is also connected through the The first clock switch is connected to the ninth differential input terminal; the nineteenth differential output terminal of the second operational amplifier is connected to the ninth differential output terminal;

The fifth non-inverting input terminal is connected to the common-mode voltage; the twentieth differential output terminal is connected to the common-mode voltage through the first clock switch; the fifth inverting input terminal is respectively connected to the fortieth The first end of the three capacitors is connected to the first end of the forty-fourth capacitor; the first end of the forty-fourth capacitor is also connected to the common-mode voltage through the third clock switch; The second end of the forty-third capacitor is connected to the twenty differential output end through the second clock switch; the second end of the forty-fourth capacitor is connected to the fourth The second end of the thirteenth capacitor is connected; the second end of the forty-fourth capacitor is also connected to the eighteenth differential output end through the second clock switch; wherein, the first end of the forty-fourth capacitor The two terminals are also connected to the tenth differential input terminal through the first clock switch; the twentieth differential output terminal of the third operational amplifier is connected to the tenth differential output terminal;

The fifteenth differential output terminals of the second latches in the second sub-DACs at each stage are all connected to the first control terminals in the corresponding second multiplication DACs; The sixteenth differential output terminals of the second latches in the second sub-DACs of each stage are all connected to the second control terminals in the corresponding second multiplication DACs.

Wherein, the third sub-digital-to-analog converter is composed of seven third comparators; wherein, each third comparator includes: a fifth preamplifier, a sixth preamplifier, and a third latch; the fifth The pre-amplifier includes a sixth non-inverting input end, a sixth inverting input end, a sixth non-inverting output end and a sixth inverting output end; the sixth pre-amplifier includes a seventh non-inverting input end, a seventh inverting input end, a sixth Seven non-inverting output terminals and a seventh inverting output terminal; the third latch includes a twenty-first differential input terminal, a twenty-second differential input terminal, a twenty-first differential output terminal, and a twenty-second differential output terminal end;

The sixth inverting output terminal is connected to the seventh non-inverting input terminal, and the sixth non-inverting output terminal is connected to the seventh inverting input terminal; the seventh inverting output terminal is connected to the twentieth A differential input terminal is connected, and the seventh non-inverting output terminal is connected to the twenty-second differential input terminal;

Wherein, the sixth non-inverting input terminal of the fifth pre-amplifier in each third comparator is connected to the eleventh differential input terminal through a second clock switch through a forty-fifth capacitor, and through the first The forty-five capacitor is connected to the fifth reference voltage through the first clock switch; the sixth inverting input terminal of the fifth pre-amplifier in each third comparator is connected to the twelfth through the forty-sixth capacitor. The differential input end is connected through the second clock switch, and is connected with the sixth reference voltage through the first clock switch through the forty-sixth capacitor; the third latch in each third comparator The twenty-first differential output terminal is connected to the eleventh differential output terminal; the twenty-second differential output terminal of the third latch in each third comparator is connected to the twelfth differential output terminal Differential output connections.

The beneficial effects of the present invention are as follows:

The pipeline analog-to-digital converter of the present invention adopts a pipeline structure without a sampling circuit at the front end, and uses the first pipeline stage of the present invention as the front end. Since the first pipeline stage adopts dynamic component matching technology, the first pipeline stage of the first pipeline stage is dynamically averaged. A matching error of the sampling capacitance in the multiplication digital-to-analog converter improves the linearity of the pipelined analog-to-digital converter of the present invention, and further reduces the power consumption of the system by reducing the requirement of the capacitance.

Description of drawings

Fig. 1 shows the overall structure schematic diagram of the pipeline analog-to-digital converter of the present invention;

Fig. 2 represents the structural representation of the first pipeline stage in the pipeline analog-to-digital converter of the present invention;

Fig. 3 shows the structural representation of the second pipeline stage of each stage in the pipeline analog-to-digital converter of the present invention;

Fig. 4 shows the structural representation of the third pipeline stage in the pipeline analog-to-digital converter of the present invention;

FIG. 5 shows a schematic structural diagram of the first comparator in the first sub-ADC of the first pipeline stage in the pipeline AD converter of the present invention;

Fig. 6 shows the structural schematic diagram 1 of the first multiplication digital-to-analog converter of the first pipeline stage in the pipelined analog-to-digital converter of the present invention;

Fig. 7 shows the structural schematic diagram 2 of the first multiplication digital-to-analog converter of the first pipeline stage in the pipelined analog-to-digital converter of the present invention;

Fig. 8 shows the structure diagram of the second comparator in the second sub-analog-digital converter of the second pipeline stage in the pipeline analog-to-digital converter of the present invention;

Fig. 9 shows the structure schematic diagram of the second multiplying digital-analog converter of the second pipeline stage of each stage in the pipeline analog-to-digital converter of the invention;

FIG. 10 shows a schematic structural diagram of the second multiplication digital-to-analog converter of the second pipeline stage of each stage in the pipeline analog-to-digital converter of the present invention;

Fig. 11 shows the schematic diagram of the first clock control signal and the second clock control signal of the clock circuit of the present invention;

Fig. 12 shows the schematic diagram of the working principle of the first pipeline stage of the present invention;

Fig. 13 shows a schematic diagram of the transmission curve of the first multiplication digital-to-analog converter in the first pipeline stage of the present invention;

Fig. 14 represents the working principle figure of the second pipeline stage of each stage of the present invention;

FIG. 15 shows a schematic diagram of the transfer curve of the second multiplication DAC in the second pipeline stage of each stage of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

As shown in Figure 1, in a specific embodiment of the present invention, the embodiment of the present invention provides a pipelined analog-to-digital converter, especially a 13-bit pipelined analog-to-digital converter, the 13-bit pipelined analog-to-digital converter mainly includes:

A first pipeline stage, a seven-stage second pipeline stage (the part included in the dotted line box in Fig. 1 ), a third pipeline stage for quantizing the signal and outputting the quantized signal connected step by stage; The first pipeline stage of the stage, the second pipeline stage of the seven stages, and the third pipeline stage of the one stage are connected respectively, and are used for the quantized signal (digital code) outputted by the first pipeline stage of the one stage, the second pipeline stage of the seven stages The output quantized signal (digital code) and the quantized signal (digital code) output by the third pipeline stage of the first stage are subjected to delay alignment and misalignment addition processing, and a digital correction circuit that outputs the processed quantized signal (digital code) ; be respectively connected with the first pipeline stage of the one stage, the second pipeline stage of the seven stages, the third pipeline stage of the one stage and the digital correction circuit, and be used for the first pipeline stage of the one stage and the second pipeline stage of the seven stages respectively. The pipeline stage, the one-third pipeline stage, and the digital correction circuit provide clock circuits with two-phase non-overlapping clock control signals.

Wherein, the first pipeline stage of the first stage is used to output 4-digit digital codes, the third pipeline stage of the first stage is used to output 3-digit digital codes, and the second pipeline stage of the seven stages is shown in Figure 1, which are respectively connected step by step The second pipeline stage of the first stage, the second pipeline stage of the second stage, the second pipeline stage of the third stage, the second pipeline stage of the fourth stage, the second pipeline stage of the fifth stage, the second pipeline stage of the sixth stage and the second pipeline stage of the sixth stage Seven stages of the second pipeline stage, wherein each stage of the second pipeline stage is used to output a 2-digit digital code, and the above-mentioned digital correction circuit is used to convert the above-mentioned first stage of the first stage of the pipeline, the second stage of the seven stages of the pipeline, and the third stage of the first stage The quantized signal (digital code) output by the pipeline stage is processed by delay alignment and offset addition to output a 13-bit quantized signal (digital code).

The structure of the above-mentioned first pipeline stage of the present invention, the second pipeline stage of each stage, the third pipeline stage of one stage and the connection relationship between each stage of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments:

The first pipeline stage of this stage is shown in Figure 2, including: a first sub-analog-to-digital converter, a first multiplication digital-to-analog converter, and is used to dynamically randomly select the sampling capacitor array in the first multiplication digital-to-analog converter A dynamic element matching circuit, that is, a DEM circuit; wherein, the first sub-analog-to-digital converter includes a first differential input terminal 11, a second differential input terminal 12, a first differential output terminal 13, and a second differential output terminal 14, the The DEM circuit comprises a third differential input terminal 21, a fourth differential input terminal 22, a third differential output terminal 23 and a fourth differential output terminal 24, and the first multiplication digital-to-analog converter comprises: a fifth differential input terminal 31, a sixth differential output terminal The differential input terminal 32, the fifth differential output terminal 33 and the sixth differential output terminal 34; wherein, the input electrical signal Vin=1.6 volts of the pipeline analog-to-digital converter, which includes a pair of differential signals, respectively the first differential signal Vin+ (a value of 0.8 volts) and the second differential signal Vin- (a value of 0.8 volts), the value of the above-mentioned Vin is the difference between the value of the first differential signal and the value of the second differential signal, and the above-mentioned first differential input terminal 11 is connected to the The first differential signal Vin+ of the analog-to-digital converter, the second differential input terminal 12 is connected to the second differential signal Vin- of the analog-to-digital converter, and the first differential output terminal 13 is connected to the third differential input terminal 21 , the above-mentioned second differential output terminal 14 is connected to the above-mentioned fourth differential input terminal 22, the above-mentioned first differential output terminal 13 is connected to a digital correction circuit for outputting 4-digit digital codes to the above-mentioned digital correction circuit, and the above-mentioned third differential output terminal 23 It is connected to the fifth differential input end 31 , and the fourth differential output end 24 is connected to the sixth differential input end 32 .

As shown in Figure 3, the first stage second pipeline stage, the second stage second pipeline stage, the third stage second pipeline stage, the fourth stage second pipeline stage, the fifth stage second pipeline stage, the sixth stage The second pipeline stage and the seventh pipeline stage both include a second sub-ADC and a second multiplication DAC; wherein, the second sub-ADC includes: a seventh differential input terminal 41, a second sub-ADC Eight differential input terminals 42, the seventh differential output terminal 43 and the eighth differential output terminal 44; the second multiplication digital-to-analog converter includes: the ninth differential input terminal 51, the tenth differential input terminal 52, the ninth differential output terminal 53 and the tenth differential output terminal 54; the seventh differential output terminal 43 is connected to the digital correction circuit for outputting 2-digit digital codes to the above-mentioned digital correction circuit, the seventh differential output terminal 43 is connected to the ninth differential input terminal 51, The eighth differential output terminal 44 is connected to the tenth differential input terminal 52; wherein, the seventh differential input terminal 41 of the second sub-analog-to-digital converter of the second pipeline stage of the first stage is connected to the first pipeline stage in the first pipeline stage. The fifth differential output terminal 33 of a multiplying digital-to-analog converter is connected, and the eighth differential input terminal 42 of the second sub-analog-to-digital converter in the second pipeline stage of the first stage is connected with the first multiplying digital-to-analog converter in the first pipeline stage. The sixth differential output terminal 34 of the device is connected; the seventh differential input terminal 41 of the second sub-DAC in the second pipeline stage of each stage afterwards is all connected with the second multiplication digital-analog converter in the second pipeline stage of the previous stage. The ninth differential output terminal 53 of the converter is connected, and the eighth differential input terminal 42 of the second sub-analog-to-digital converter in the second pipeline stage of each stage afterwards is all connected with the second multiplication digital-analog of the second pipeline stage of the previous stage. The tenth output 54 of the converter is connected.

As shown in FIG. 4, the third pipeline stage (which may be a flash analog-to-digital converter) includes: a third sub-digital-to-analog converter, wherein the third sub-digital-to-analog converter includes: an eleventh differential input terminal, the twelfth differential input terminal 62, the eleventh differential output terminal 63 and the twelfth differential output terminal 64; wherein, the eleventh differential input terminal is connected to the second multiplication digital-analog The ninth differential output terminal 53 of the converter is connected, and the twelfth differential input terminal 62 is connected with the tenth differential output terminal 54 of the second multiplication digital-to-analog converter in the second pipeline stage of the seventh stage, and the eleventh differential The output terminal 63 is connected with the above-mentioned digital correction circuit, and is used for outputting the digital correction circuit of a 3-digit digital code system.

The internal specific structure of the first sub-analog-to-digital converter in the first pipeline stage of the present invention will be described in detail below in conjunction with the accompanying drawings:

As shown in Figure 5, the first sub-analog-to-digital converter in the first pipeline stage of the present invention is made up of fourteen first comparators; Wherein, each first comparator includes: first stage pre-amplifier, second stage A pre-amplifier and a first latch; the first-stage pre-amplifier includes a first non-inverting input end, a first inverting input end, a first non-inverting output end and a first inverting output end; the second-stage pre-amplifier Including a second non-inverting input terminal, a second inverting input terminal, a second non-inverting output terminal and a second inverting output terminal; the first latch includes a thirteenth differential input terminal 71, a fourteenth differential input terminal 72, The thirteenth differential output terminal 73, the fourteenth differential output terminal 74; the first inverting output terminal is connected to the second non-inverting input terminal, and the first non-inverting output terminal is connected to the second inverting input and output terminal The second inverting output terminal is connected with the thirteenth differential input terminal 71, and the second non-inverting output terminal is connected with the fourteenth differential input terminal 72; the first latch in each first comparator The thirteenth differential output terminal 73 of each first comparator is connected to the first differential output terminal 13, and the fourteenth differential output terminal 74 of the first latch of each first comparator is connected to the second The differential output terminal 14 is connected; the first non-inverting input terminal and the first inverting output terminal are connected through the first clock switch Φ1; the first inverting input terminal and the first non-inverting output terminal are connected through the The first clock switch Φ1 is connected; the first non-inverting input terminal of each first comparator is connected to the first differential input terminal 11 through the first capacitor C1 through the second clock switch Φ2 and through the first The capacitor C1 is connected to the first reference voltage Vref1+ (value is 1.65 volts) through the first clock switch Φ1; the first inverting input terminal of each first comparator is connected to the second differential input terminal through the second capacitor C2 The input terminal 12 is connected through the second clock switch Φ2 and connected with the second reference voltage Vref1− (value is 0.85 volts) through the first clock switch Φ1 through the second capacitor C2.

The internal specific structure of the first multiplication digital-to-analog converter in the first pipeline stage of the present invention will be described in detail below in conjunction with the accompanying drawings:

As shown in Figure 6 and Figure 7, the first multiplying digital-to-analog converter consists of a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor Capacitor C9, tenth capacitor C10, eleventh capacitor C11, twelfth capacitor C12, thirteenth capacitor C13, fourteenth capacitor C14, fifteenth capacitor C15, sixteenth capacitor C16, seventeenth capacitor C17, The eighteenth capacitor C18, the nineteenth capacitor C19, the twentieth capacitor C20, the twenty-first capacitor C21, the twenty-second capacitor C22, the twenty-third capacitor C23, the twenty-fourth capacitor C24, the twenty-fifth capacitor Capacitor C25, twenty-sixth capacitor C26, twenty-seventh capacitor C27, twenty-eighth capacitor C28, twenty-ninth capacitor C29, thirtieth capacitor C30, thirty-first capacitor C31, thirty-second capacitor C32 , the thirty-third capacitor C33, the thirty-fourth capacitor C34, the thirty-fifth capacitor C35, the thirty-sixth capacitor C36, the thirty-seventh capacitor C37, the thirty-eighth capacitor C38 and the first operational amplifier; wherein , the first operational amplifier includes a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal; the non-inverting output terminal and the inverting output terminal are connected through a first clock switch Φ1; Both the non-inverting input terminal and the inverting input terminal are connected to the common mode voltage Vcm (value is 1.25 volts) through the third clock switch Φ3; the non-inverting output terminal is connected to the fifth differential output terminal 33; the inverting The phase output terminal is connected to the sixth differential output terminal 34;

The first end of the third capacitor C3, the first end of the fourth capacitor C4, the first end of the fifth capacitor C5, the first end of the sixth capacitor C6, the seventh capacitor C7 the first end of the eighth capacitor C8, the first end of the ninth capacitor C9, the first end of the tenth capacitor C10, the first end of the eleventh capacitor C11, The first end of the twelfth capacitor C12, the first end of the thirteenth capacitor C13, the first end of the fourteenth capacitor C14, the first end of the fifteenth capacitor C15, the The first end of the sixteenth capacitor C16, the first end of the seventeenth capacitor C17, the first end of the eighteenth capacitor C18, the first end of the nineteenth capacitor C19 and the second The first end of the ten-capacitor C20 is connected to the non-inverting input end through a common connection line; the second end of the third capacitor C3, the second end of the fourth capacitor C4, the first end of the fifth capacitor C5 two terminals, the second terminal of the sixth capacitor C6, the second terminal of the seventh capacitor C7, the second terminal of the eighth capacitor C8, the second terminal of the ninth capacitor C9, the second terminal of the first The second end of the tenth capacitor C10, the second end of the eleventh capacitor C11, the second end of the twelfth capacitor C12, the second end of the thirteenth capacitor C13, the fourteenth capacitor The second end of C14, the second end of the fifteenth capacitor C15, the second end of the sixteenth capacitor C16, the second end of the seventeenth capacitor C17, the eighteenth capacitor C18 The second terminal, the second terminal of the nineteenth capacitor C19 and the second terminal of the twentieth capacitor C20 are respectively connected to the fifth differential input terminal 31 through the first clock switch Φ1, respectively connected to the first reference The voltage Vref1+ (with a value of 1.65 volts) is connected to the second reference voltage Vref1- (with a value of 0.85 volts) through the first clock switch Φ1 and connected to the inverting output terminals respectively through the first clock switch Φ1 connected through the second clock switch Φ2 (not shown in the figure);

The first end of the twenty-first capacitor C21, the first end of the twenty-second capacitor C22, the first end of the twenty-third capacitor C23, the first end of the twenty-fourth capacitor C24 end, the first end of the twenty-fifth capacitor C25, the first end of the twenty-sixth capacitor C26, the first end of the twenty-seventh capacitor C27, the first end of the twenty-eighth capacitor C28 The first end, the first end of the twenty-ninth capacitor C29, the first end of the thirtieth capacitor C30, the first end of the thirty-first capacitor C31, the thirty-second capacitor C32 the first end of the thirty-third capacitor C33, the first end of the thirty-fourth capacitor C34, the first end of the thirty-fifth capacitor C35, the thirty-sixth The first end of the capacitor C36, the first end of the thirty-seventh capacitor C37 and the first end of the thirty-eighth capacitor C38 are connected to the inverting input end through a common connection line; the second The second end of the eleventh capacitor C21, the second end of the twenty-second capacitor C22, the second end of the twenty-third capacitor C23, the second end of the twenty-fourth capacitor C24, the The second end of the twenty-fifth capacitor C25, the second end of the twenty-sixth capacitor C26, the second end of the twenty-seventh capacitor C27, the second end of the twenty-eighth capacitor C28, The second end of the twenty-ninth capacitor C29, the second end of the thirtieth capacitor C30, the second end of the thirty-first capacitor C31, the second end of the thirty-second capacitor C32 , the second end of the thirty-third capacitor C33, the second end of the thirty-fourth capacitor C34, the second end of the thirty-fifth capacitor C35, the first end of the thirty-sixth capacitor C36 Two terminals, the second terminal of the thirty-seventh capacitor C37 and the second terminal of the thirty-eighth capacitor C38 are respectively connected to the sixth differential input terminal 32 through the first clock switch Φ1, respectively to the The first reference voltage Vref1+ (with a value of 1.65 volts) is connected through the first clock switch Φ1, respectively connected with the second reference voltage Vref1- (with a value of 0.85 volts) through the first clock switch Φ1, respectively It is connected with the non-inverting output terminal through the second clock switch Φ2 (not shown in the figure).

The internal specific structure of the second sub-analog-to-digital converter of each level of the second pipeline stage in the seven-stage second pipeline stage of the present invention will be described in detail below in conjunction with the accompanying drawings:

As shown in Figure 8, the second sub-analog-to-digital converter in the second pipeline stage of each level is composed of two comparators; wherein, each second comparator includes: the third pre-amplifier, the fourth pre-amplifier and A second latch; the third pre-amplifier includes a second non-inverting input, a second inverting input, a second non-inverting output, and a second inverting output; the fourth pre-amplifier includes a third non-inverting input terminal, a third inverting input terminal, a third non-inverting output terminal and a third inverting output terminal; the second latch includes a fifteenth differential input terminal 81, a sixteenth differential input terminal 82, a fifteenth differential input terminal output terminal 83, the sixteenth differential output terminal 84; the second inverting output terminal is connected to the third non-inverting input terminal, and the second non-inverting output terminal is connected to the third inverting input terminal; the The third inverting output terminal is connected to the fifteenth differential input terminal 81, and the third non-inverting output terminal is connected to the sixteenth differential input terminal 82;

Wherein, the second non-inverting input terminal of the third pre-amplifier in each second comparator is connected to the seventh differential input terminal 41 through the 39th capacitor C39 through the second clock switch Φ2, and through the The thirty-ninth capacitor C39 is connected to the third reference voltage Vref2+ (value is 1.65/2 volts) through the first clock switch Φ1; the second inverting input of the third pre-amplifier in each second comparator terminal is connected to the eighth differential input terminal 42 through the second clock switch Φ2 through the fortieth capacitor C40, and is connected to the fourth reference voltage Vref2- (value is 0.85/2 volts) through the fortieth capacitor C40 Connected through the first clock switch Φ1; the fifteenth differential output terminal 83 of the second latch in each second comparator is connected to the seventh differential output terminal 43; each second comparator The sixteenth differential output terminal 84 of the second latch in the register is connected to the eighth differential output terminal 44 .

The internal specific structure of the second multiplication digital-to-analog converter of each second pipeline stage in the second pipeline stage of each level in the seven-stage second pipeline stage of the present invention will be described in detail below in conjunction with the accompanying drawings:

As shown in Figure 9, the second multiplying digital-to-analog converters in the second pipeline stages of each level are all fully differential structures (only a single-sided structural schematic diagram is shown in the figure), and all are selected by the first three A selector, a second three-choice selector, a second operational amplifier, a third operational amplifier, a forty-first capacitor C41, a forty-second capacitor C42, a forty-third capacitor, and a forty-fourth capacitor;

Wherein, the first three selector includes: a seventeenth differential input terminal 91, an eighteenth differential input terminal 92, a nineteenth differential input terminal 93, a first control terminal 94, and a seventeenth differential output terminal 95 ; The second three-choice selector (not shown in the figure) includes: the twentieth differential input terminal, the twenty-first differential input terminal, the twenty-second differential input terminal, the second control terminal, and the eighteenth differential input terminal. output terminal; the second operational amplifier includes a fourth non-inverting input terminal, a fourth inverting input terminal and a nineteenth differential output terminal 101; the third operational amplifier (not shown in the figure) includes a fifth non-inverting input terminal, a fifth inverting input terminal and a twentieth differential output terminal;

The seventeenth differential input terminal 91 and the twentieth differential input terminal are respectively connected to the third reference voltage Vref2+ (set according to specific conditions); the eighteenth differential input terminal 92 and the twenty-first differential input terminal The input terminals are respectively connected to the fourth reference voltage Vref2- (set according to specific conditions); the nineteenth differential input terminal 93 and the twenty-second differential input terminal are respectively connected to a low level "0";

The fourth non-inverting input terminal is connected to the common-mode voltage Vcm (value is 1.25 volts); the nineteenth differential output terminal 101 is connected to the common-mode voltage through the first clock switch Φ1; the fourth inverting input terminal respectively connected to the first end of the forty-first capacitor C41 and the first end of the forty-second capacitor C42; the first end of the forty-second capacitor C42 also passes through the third clock switch Φ3 connected to the common-mode voltage; the second end of the forty-first capacitor C41 is connected to the nineteenth differential output end 101 through the second clock switch Φ2; the second end of the forty-second capacitor C42 The second end of the forty-first capacitor C41 is connected through the first clock switch Φ1; the second end of the forty-second capacitor C42 is also connected to the seventeenth capacitor C42 through the second clock switch Φ2. The differential output terminal 95 is connected; wherein, the second terminal of the forty-second capacitor is also connected to the ninth differential input terminal 51 through the first clock switch Φ1; the tenth terminal of the second operational amplifier Nine differential output terminals 101 are connected to the ninth differential output terminal 53;

The fifth non-inverting input terminal is connected to the common-mode voltage; the twentieth differential output terminal is connected to the common-mode voltage through the first clock switch Φ1; the fifth inverting input terminal is respectively connected to the The first end of the forty-third capacitor is connected to the first end of the forty-fourth capacitor; the first end of the forty-fourth capacitor is also connected to the common mode through the third clock switch Φ3 Voltage connection; the second end of the forty-third capacitor is connected to the twenty differential output end through the second clock switch Φ2; the second end of the forty-fourth capacitor is connected through the first clock switch Φ1 is connected to the second end of the forty-third capacitor; the second end of the forty-fourth capacitor is also connected to the eighteenth differential output end through the second clock switch Φ2; wherein, the The second terminal of the forty-fourth capacitor is also connected to the tenth differential input terminal 52 through the first clock switch Φ1; the twentieth differential output terminal of the third operational amplifier is connected to the tenth differential output terminal 54 connections;

The fifteenth differential output terminal 83 of the second latch in each stage of the second sub-digital-to-analog converter is connected to the first control terminal 94 in the corresponding second multiplication digital-to-analog converter. connected; the sixteenth differential output terminal 84 of the second latch in each stage of the second sub-digital-analog converter is connected to the second control in the corresponding second multiplication digital-analog converter end connection.

The internal specific structure of the third sub-analog-to-digital converter in the third pipeline stage of the present invention will be described in detail below in conjunction with the accompanying drawings:

As shown in FIG. 10, the third sub-digital-to-analog converter is composed of seven third comparators; wherein, each third comparator includes: a fifth pre-amplifier, a sixth pre-amplifier and a third latch; The fifth pre-amplifier includes a sixth non-inverting input end, a sixth inverting input end, a sixth non-inverting output end and a sixth inverting output end; the sixth pre-amplifier includes a seventh non-inverting input end, a seventh inverting input terminal, the seventh non-inverting output terminal and the seventh inverting output terminal; the third latch includes a twenty-first differential input terminal 201, a twenty-second differential input terminal 202, and a twenty-first differential output terminal 203 , the twenty-second differential output terminal 204;

The sixth inverting output terminal is connected to the seventh non-inverting input terminal, and the sixth non-inverting output terminal is connected to the seventh inverting input terminal; the seventh inverting output terminal is connected to the twentieth A differential input terminal 201 is connected, and the seventh non-inverting output terminal is connected to the twenty-second differential input terminal 202;

Wherein, the sixth non-inverting input terminal of the fifth pre-amplifier in each third comparator is connected to the eleventh differential input terminal 61 through the forty-fifth capacitor C45 through the second clock switch Φ2, and through The forty-fifth capacitor C45 is connected to the fifth reference voltage Vref3+ through the first clock switch Φ1; the sixth inverting input terminal of the fifth pre-amplifier in each third comparator is connected through the forty-sixth capacitor C46 is connected to the twelfth differential input terminal 62 through the second clock switch Φ2, and is connected to the sixth reference voltage Vref3 through the forty-sixth capacitor C46-through the first clock switch Φ1; each The twenty-first differential output terminal 203 of the third latch in the third comparator is connected to the eleventh differential output terminal 63; the third latch in each third comparator The twenty-second differential output terminal 204 is connected to the twelfth differential output terminal 64 .

The working principle of the present invention will be analyzed below:

As shown in FIG. 11 , the two phases of non-overlapping clock control signals are respectively a first clock control signal and a second clock control signal, wherein the third clock control signal has a time delay compared with the first clock control signal.

In combination with Fig. 12, the input signal Vin is firstly quantized by the first sub-DAC to output a 4-digit digital code, the 4-bit output code of the first sub-ADC is first encoded by the DEM circuit, and the DEM circuit generates a pseudo-random code , randomly select a capacitor array combination each time, average the error caused by capacitor mismatch, and improve the linearity of the system.

In conjunction with Fig. 2, Fig. 6, Fig. 11, Fig. 12 (the one in the dotted line box is the first multiplication digital-to-analog converter), the working process of the first multiplication digital-to-analog converter is as follows: sampling phase, the first clock control signal is at a high potential State, analyze the unilateral circuit, at this time the first clock switch Φ1 is turned on, the non-inverting input terminal and the inverting input terminal of the first operational amplifier are both connected to the common mode voltage Vcm, and the non-inverting output terminal and the inverting output terminal are short-circuited, at this time , the first operational amplifier is in the reset state, the first differential signal Vin+ is sampled to the third capacitor C3 to the eighteenth capacitor C18, the nineteenth capacitor C19 and the twentieth capacitor C20 are respectively connected to the second reference voltage Vref1- and The first reference voltage Vref1+, when the sampling phase ends, the potential of the corresponding third clock control signal at the third clock switch will be at low level before the first clock control signal, and this sampling timing is bottom plate sampling. The signal distortion caused by the charge injection into the switch channel can be effectively reduced through the timing optimization. In the amplification phase, referring to Fig. 2, Fig. 7, Fig. 11, and Fig. 12, the second clock control signal is at a high potential, and the DEM circuit will randomly select four flipping capacitors from the third capacitor C3 to the eighteenth capacitor C18 The inverting output terminal of an operational amplifier is connected, and the output result of the first sub-digital-analog converter in the first multiplication digital-analog converter is determined by DEM circuit coding in the remaining 14 capacitors from the third capacitor C3 to the twentieth capacitor C20 The capacitor is connected to the first reference voltage Vref1+ or to the second reference voltage Vref1- to complete signal subtraction.

Among them, the quantitative analysis of the working process of the first multiplication digital-to-analog converter in the first pipeline stage is as follows:

In the sampling phase, analyze the single-ended circuit, the third capacitor C3 to the eighteenth capacitor C18 sample the first differential signal Vin+, the nineteenth capacitor C19 and the twentieth capacitor C20 are respectively connected to the second reference voltage Vref1- and the first reference Voltage Vref1+, the charge at the input point X of the first operational amplifier is: Among them, Qx is the charge at point X, and Ci is the i-th capacitance.

In the amplification phase, among the 18 single-ended capacitors, according to the pseudo-random code generated by the DEM circuit, four capacitors from the third capacitor C3 to the twentieth capacitor C20 are randomly selected to be connected to the non-inverting output terminal as the feedback capacitor; the first The output codes of the 14 comparators in the pipeline stage control whether the remaining 14 sampling capacitors are connected to the first reference voltage Vref1+ or to the second reference voltage Vref11-, if the i-th comparator output bit Di=1, then the corresponding The i-th capacitor Ci is connected to the first reference voltage Vref1+; if Di=0, the corresponding i-th capacitor Ci is connected to the second reference voltage Vref1-, the DEM circuit generates a set of random codes to encode Di, and the original corresponding feedback capacitor combination Random distribution is performed, and Di corresponds to Bi after re-encoding, so even if the encoding of Di is the same, Bi is different from Di after the pseudo-random code configuration, and the capacitors selected each time are different. Through the random average capacitance mismatch error of the DEM circuit, for the convenience of analysis, it is assumed that the four capacitors fed back are the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6, (actually four capacitors are randomly selected) . According to the principle of charge conservation, the transfer function of the first multiplication digital-to-analog converter can be derived as:

Wherein, Vref1 is the difference between the value of the first reference voltage Vref1+ and the value of the second reference voltage Vref1-, C31 is the capacitance value of the third capacitor, C41 is the capacitance value of the fourth capacitor, and C51 is the capacitance value of the fifth capacitor , C61 is the capacitance value of the sixth capacitor. As shown in Figure 13, it is the transmission curve diagram of the first multiplying digital-to-analog converter. From this figure, it can be seen that the output full rail of the first pipeline stage becomes half of the input full rail due to gain compression, that is, Vout =1/2Vin, so the reference voltages of the second pipeline stages in the second pipeline stage are half of the reference voltage of the first pipeline stage, that is, Vref2+=1/2Vref1+, Vref2-=1/2Vref1-.

Wherein, the quantitative analysis of the working process of the second multiplication digital-to-analog converter of each stage in the second pipeline stage is as follows:

Analyzing unilateral circuits:

In conjunction with Fig. 8, Fig. 9, Fig. 11, Fig. 14 (the second multiplying digital-to-analog converter in the dotted line box), the second multiplying digital-to-analog converter circuit works alternately in the sampling stage and under two non-overlapping clock control signals Amplifying stage; its timing signal is the same as that of the first multiplying digital-to-analog converter. In the sampling stage, when the first clock control signal is at a high potential, the input signal is sampled by the forty-first capacitor C41 and the forty-second capacitor C42; in the amplification stage, when the second clock control signal is at a high potential, the forty-second The capacitor C42 is disconnected from the input signal terminal and connected to the output terminal of the operational amplifier to form a negative feedback loop. The first control terminal 94 of the multiplexer (MUX). The transfer function of the second multiplying digital-to-analog converter is: Wherein, C411 is the capacitance value of the forty-first capacitor C41, C421 is the capacitance value of the forty-second capacitor C42, S0 is a parameter, Vrefj is the reference voltage value of the second pipeline stage of each stage, and the value of the Vrefj is equal to is the difference between the value of 1/2Vref1+ and the value of 1/2Vref1-, Voutj is the output voltage of the second multiplication digital-to-analog converter in the second pipeline stage of the jth stage, and Vinj is the second sub-voltage in the second pipeline stage of the jth stage. The input voltage value of the analog-to-digital converter, wherein, j is 1, 2, 3, 4, 5, 6 or 7; for the first stage and the second pipeline stage, the second submodule of the first stage and the second pipeline stage The input voltage of the digital converter is Vin1, which is the output voltage of the first pipeline stage, that is, the margin voltage Vout, and the input voltage of the second pipeline stage of the second stage is Vin2, which is the margin voltage of the second pipeline stage of the previous stage. Vout1, and so on.

Wherein, the capacitance values of the forty-first capacitor C41 and the forty-second capacitor C42 are equal, and the magnitude of the input signal is determined by the value of a parameter S0, which has three values, namely +1, 0, and -1. Therefore, the transfer function of the second multiplying DAC can be written as:

An ideal transfer curve of the second multiplying digital-to-analog converter at the second pipeline stage of each stage should be as shown in FIG. 15 .

The margin voltage output by the first pipeline stage will be continuously quantized by the first and second pipeline stages, and the margin voltage of the first and second pipeline stages will be continuously quantized by the second pipeline stage of the next stage, and so on. The first pipeline stage to the seventh pipeline stage and the second pipeline stage, the first multiplication digital-analog converter and the second multiplication digital-analog converter in these eight stages work alternately, add the last third pipeline stage, complete the quantization of the signal, and finally A 13-bit digital code is output through a digital correction circuit.

The above is only a preferred embodiment of the present invention, and it should be pointed out that for those of ordinary skill in the art, some improvements and modifications can be made without departing from the principle of the present invention. It should be regarded as the protection scope of the present invention.

Claims (9)

1. a kind of production line analog-digital converter is it is characterised in that include：

Connect step by step for carrying out to signal quantifying and one-level first pipeline stages of output quantization signal, seven grade of second flowing water Line level, one-level the 3rd pipeline stages；

It is connected respectively with described one-level first pipeline stages, described seven grade of second pipeline stages, described one-level the 3rd pipeline stages, For described one-level first pipeline stages are exported quantized signal, the quantized signal of described seven grade of second pipeline stages output, The quantized signal of described one-level the 3rd pipeline stages output is entered line delay be aligned and is added process with dislocation, and exports treated The digital correction circuit of quantized signal；

With described one-level first pipeline stages, described seven grade of second pipeline stages, described one-level the 3rd pipeline stages and described Digital correction circuit connects respectively, for being respectively described one-level first pipeline stages, described seven grade of second pipeline stages, described The clock circuit of the clock control signal of one-level the 3rd pipeline stages and the described digital correction circuit biphase non-overlapping of offer.

2. production line analog-digital converter according to claim 1 is it is characterised in that described first pipeline stages include first Multiplying digital-to-analog converter, for the dynamic of dynamic random selection is carried out to the sampling capacitance array in the first multiplying digital-to-analog converter Element matching circuit and the first sub-adc converter；Wherein, described first sub-adc converter includes the first differential input end (11), the second differential input end (12), the first difference output end (13) and the second difference output end (14)；Described dynamic element Distribution road includes the 3rd differential input end (21), the 4th differential input end (22), the 3rd difference output end (23) and the 4th difference Outfan (24)；Described first multiplying digital-to-analog converter include the 5th differential input end (31), the 6th differential input end (32), Five difference output ends (33) and the 6th difference output end (34)；Wherein, described first differential input end (11) connects analog digital conversion First differential voltage of device, described second differential input end (12) connects the second differential voltage of analog-digital converter；Described first Difference output end (13) is connected with described 3rd differential input end (21), and described second difference output end (14) is poor with the described 4th Input (22) is divided to connect；Described first difference output end (13) is connected with described digital correction circuit；Described 3rd difference is defeated Go out end (23) to be connected with described 5th differential input end (31), described 4th difference output end (24) and described 6th Differential Input End (32) connects.

3. production line analog-digital converter according to claim 2 is it is characterised in that described seven grade of second pipeline stages are distinguished For：The first order second pipeline stages, the second level second pipeline stages, the third level second pipeline stages, the fourth stage second streamline Level, level V second pipeline stages, the 6th grade of the second pipeline stages, the 7th grade of the second pipeline stages；Wherein, the second flowing water at different levels Line level all includes the second sub-adc converter and the second multiplying digital-to-analog converter；

Wherein, described second subnumber weighted-voltage D/A converter includes the 7th differential input end (41), the 8th differential input end (42), the 7th poor Divide outfan (43) and the 8th difference output end (44)；Described second multiplying digital-to-analog converter includes：9th differential input end (51), the tenth differential input end (52), the 9th difference output end (53) and the tenth difference output end (54)；Described 7th difference is defeated Go out end (43) to be connected with described numeral emphasizer circuit；Described 7th difference output end (43) and described 9th differential input end (51) Connect；Described 8th difference output end (44) is connected with described tenth differential input end (52)；

Wherein, described 7th differential input end (41) of described second sub-adc converter of the described first order second pipeline stages It is connected with described 5th difference output end (33), the institute of described second sub-adc converter of the described first order second pipeline stages State the 8th differential input end (42) to be connected with described 6th difference output end (34)；Every one-level second pipeline stage is described backward Described second multiplication all with previous stage second pipeline stages for described 7th differential input end (41) of the second sub-adc converter Described 9th difference output end (53) of digital to analog converter connects, backward the described second submodule number of every one-level second pipeline stage Described second multiplying digital-to-analog converter all with previous stage second pipeline stages for described 8th differential input end (42) of transducer Described tenth difference output end (54) connect.

4. production line analog-digital converter according to claim 3 is it is characterised in that described 3rd pipeline stages include：

3rd subnumber weighted-voltage D/A converter；Wherein, described 3rd subnumber weighted-voltage D/A converter include the 11st differential input end (61), the 12nd Differential input end (62), the 11st difference output end (63) and the 12nd difference output end (64)；Described 11st measurement shoutage is divided into Described 9th difference output end of the second multiplying digital-to-analog converter described in end (61) and described 7th grade of the second pipeline stages (53) connect, described 12nd differential input end (62) is turned with the second multiplication digital-to-analogue described in described 7th grade of the second pipeline stages Described tenth difference output end (54) of parallel operation connects；Described 11st difference output end (63) is with described digital correction circuit even Connect.

5. production line analog-digital converter according to claim 2 is it is characterised in that described first sub-adc converter is by ten Four first comparator compositions；Wherein, each first comparator includes：First order prime amplifier, second level prime amplifier and One latch；Described first order prime amplifier include the first in-phase input end, the first inverting input, the first in-phase output end and First reversed-phase output；It is defeated that described second level prime amplifier includes the second in-phase input end, the second inverting input, the second homophase Go out end and the second reversed-phase output；Described first latch includes the 13rd differential input end (71), the 14th differential input end (72), the 13rd difference output end (73), the 14th difference output end (74)；Described first reversed-phase output is same with described second Phase input connects, and described first in-phase output end is connected with the described second anti-phase access port；Described second reversed-phase output with Described 13rd differential input end (71) connects, and described second in-phase output end is with described 14th differential input end (72) even Connect；Described 13rd difference output end (73) of the first latch described in each first comparator and described first difference output End (13) connects, described 14th difference output end (74) and described second of described first latch of each first comparator Difference output end (14) connects；Described first in-phase input end passes through the first clock switch (Φ with described first reversed-phase output 1) connect；Described first inverting input is connected by described first clock switch (Φ 1) with described first in-phase output end；Often Described first in-phase input end of individual first comparator is passed through with described first differential input end (11) by the first electric capacity (C1) Second clock switch (Φ 2) is connected and is opened by described first clock by described first electric capacity (C1) and the first reference voltage Close (Φ 1) to connect；Described first inverting input of each first comparator passes through the second electric capacity (C2) and described second difference Input (12) passes through described second clock switch (Φ 2) and connects and by described second electric capacity (C2) and the second reference voltage Connected by described first clock switch (Φ 1).

6. production line analog-digital converter according to claim 2 is it is characterised in that described first multiplying digital-to-analog converter By：

3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, 11st electric capacity, the 12nd electric capacity, the 13rd electric capacity, the 14th electric capacity, the 15th electric capacity, the 16th electric capacity, the 17th electric capacity, 18th electric capacity, the 19th electric capacity, the 20th electric capacity, the 21st electric capacity, the 22nd electric capacity, the 23rd electric capacity, second 14 electric capacity, the 25th electric capacity, the 26th electric capacity, the 27th electric capacity, the 28th electric capacity, the 29th electric capacity, 30 electric capacity, the 31st electric capacity, the 32nd electric capacity, the 33rd electric capacity, the 34th electric capacity, the 35th electric capacity, 36 electric capacity, the 37th electric capacity, the 38th electric capacity and the first operational amplifier composition；Wherein, described first computing Amplifier includes an in-phase input end, an inverting input, an in-phase output end and a reversed-phase output；Described in-phase output end It is connected by the first clock switch (Φ 1) with described inverse output terminal；Described in-phase input end is all logical with described reverse input end Cross the 3rd clock switch (Φ 3) and connect common-mode voltage；Described in-phase output end is connected with described 5th difference output end (33)；Institute State reversed-phase output to be connected with described 6th difference output end (34)；

The first end of described 3rd electric capacity, the first end of described 4th electric capacity, the first end of described 5th electric capacity, described 6th electricity The first end of appearance, the first end of described 7th electric capacity, the first end of described 8th electric capacity, the first end of described 9th electric capacity, institute State the first end of the tenth electric capacity, the first end of described 11st electric capacity, the first end of described 12nd electric capacity, described 13rd electricity Hold first end, the first end of described 14th electric capacity, the first end of described 15th electric capacity, the first of described 16th electric capacity End, the first end of described 17th electric capacity, the first end of described 18th electric capacity, the first end of described 19th electric capacity and described The first end of the 20th electric capacity is connected with described in-phase input end by buss；Second end of described 3rd electric capacity, Second end of described 4th electric capacity, the second end of described 5th electric capacity, the second end of described 6th electric capacity, described 7th electric capacity Second end, the second end of described 8th electric capacity, the second end of described 9th electric capacity, the second end of described tenth electric capacity, described Second end of 11 electric capacity, the second end of described 12nd electric capacity, the second end of described 13rd electric capacity, described 14th electric capacity The second end, the second end of described 15th electric capacity, the second end of described 16th electric capacity, the second of described 17th electric capacity Second end of end, the second end of described 18th electric capacity, the second end of described 19th electric capacity and described 20th electric capacity is respectively Be connected by the first clock switch (Φ 1) with described 5th differential input end (31), respectively with the first reference voltage pass through described First clock switch (Φ 1) connected, is connected by described first clock switch (Φ 1) with the second reference voltage respectively, respectively with Described reversed-phase output is connected by second clock switch (Φ 2)；

The first end of described 21st electric capacity, the first end of described 22nd electric capacity, the first of described 23rd electric capacity End, the first end of described 24th electric capacity, the first end of described 25th electric capacity, the first of described 26th electric capacity End, the first end of described 27th electric capacity, the first end of described 28th electric capacity, the first of described 29th electric capacity End, the first end of described 30th electric capacity, the first end of described 31st electric capacity, the first end of described 32nd electric capacity, The first end of described 33rd electric capacity, the first end of described 34th electric capacity, the first end of described 35th electric capacity, institute First end, the first end of described 37th electric capacity and the first end of described 38th electric capacity of stating the 36th electric capacity are passed through One buss are connected with described inverting input；Second end of described 21st electric capacity, described 22nd electric capacity Second end, the second end of described 23rd electric capacity, the second end of described 24th electric capacity, the of described 25th electric capacity Two ends, the second end of described 26th electric capacity, the second end of described 27th electric capacity, the second of described 28th electric capacity End, the second end of described 29th electric capacity, the second end of described 30th electric capacity, the second end of described 31st electric capacity, Second end of described 32nd electric capacity, the second end of described 33rd electric capacity, the second end of described 34th electric capacity, institute State the second end, the second end of described 36th electric capacity, the second end of described 37th electric capacity and the institute of the 35th electric capacity Described first clock switch (Φ 1) is passed through even with described 6th differential input end (32) respectively in the second end stating the 38th electric capacity Connect, be connected by described first clock switch (Φ 1) with described first reference voltage respectively, respectively with described second reference voltage Connected by described first clock switch (Φ 1), pass through described second clock switch (Φ 2) even with described in-phase output end respectively Connect.

7. production line analog-digital converter according to claim 3 it is characterised in that

Second sub-adc converter described in second pipeline stages at different levels is by two the second comparator compositions；Wherein, each Two comparators include：3rd prime amplifier, the 4th prime amplifier and the second latch；It is same that described 3rd prime amplifier includes second Phase input, the second inverting input, the second in-phase output end and the second reversed-phase output；Described 4th prime amplifier includes Three in-phase input ends, the 3rd inverting input, the 3rd in-phase output end and the 3rd reversed-phase output；Described second latch includes 15th differential input end (81), the 16th differential input end (82), the 15th difference output end (83), the 16th difference output End (84)；Described second reversed-phase output is connected with described 3rd in-phase input end, described second in-phase output end and described the Three inverting inputs connect；Described 3rd reversed-phase output is connected with described 15th differential input end (81), and the described 3rd is same Phase output terminal is connected with described 16th differential input end (82)；

Wherein, described second in-phase input end of the 3rd prime amplifier described in each second comparator passes through the 39th electric capacity (C39) it is connected by second clock switch (Φ 2) with described 7th differential input end (41), and by described 39th electricity Hold (C39) to be connected by the first clock switch (Φ 1) with the first reference voltage；3rd pre-amplification described in each second comparator Described second inverting input of device passes through the 40th electric capacity (C40) and passes through described second with described 8th differential input end (42) Clock switch (Φ 2) connects, and is opened by described first clock with the second reference voltage by described 40th electric capacity (C40) Close (Φ 1) to connect；Described 15th difference output end (83) of the second latch described in each second comparator and described the Seven difference output ends (43) connect；Described 16th difference output end (84) of the second latch described in each second comparator It is connected with described 8th difference output end (44).

8. production line analog-digital converter according to claim 7 is it is characterised in that institute in described second pipeline stages at different levels State the second multiplying digital-to-analog converter by the first one-out-three selector, the second one-out-three selector, the second operational amplifier, the 3rd Operational amplifier, the 41st electric capacity (C41), the 42nd electric capacity (C42), the 43rd electric capacity, the 44th electric capacity composition；

Wherein, described first one-out-three selector includes：17th differential input end (91), the 18th differential input end (92), 19th differential input end (93), the first control end (94), the 17th difference output end (95)；Described second one-out-three selector Including：20th differential input end, the 21st differential input end, the 22nd differential input end, the second control end, the 18th Difference output end；It is defeated that described second operational amplifier includes the 4th in-phase input end, the 4th inverting input and the 19th difference Go out end (101)；Described 3rd operational amplifier includes the 5th in-phase input end, the 5th inverting input and the 20th difference output End；

Described 17th differential input end (91), the 20th differential input end are connected with the 3rd reference voltage respectively；Described tenth Eight differential input ends (92), described 21st differential input end are connected with the 4th reference voltage respectively；Described 19th difference Input (93), described 22nd differential input end connect low level respectively；

Described 4th in-phase input end connects common-mode voltage；Described 19th difference output end (101) passes through the first clock switch (Φ 1) is connected with described common-mode voltage；The described 4th inverting input first end with described 41st electric capacity (C41) respectively Connect and be connected with the first end of described 42nd electric capacity (C42)；The first end of described 42nd electric capacity (C42) also by 3rd clock switch (Φ 3) is connected with described common-mode voltage；Second clock is passed through at second end of described 41st electric capacity (C41) Switch (Φ 2) is connected with described 19th difference output end (101)；Institute is passed through at second end of described 42nd electric capacity (C42) The second end stating the first clock switch (Φ 1) with described 41st electric capacity (C41) is connected；Described 42nd electric capacity (C42) The second end switch (Φ 2) also by described second clock and be connected with described 17th difference output end (95)；Wherein, described Second end of 42 electric capacity is connected with described 9th differential input end (51) also by described first clock switch (Φ 1)；Institute Described 19th difference output end (101) stating the second operational amplifier is connected with described 9th difference output end (53)；

Described 5th in-phase input end connects common-mode voltage；Described 20th difference output end passes through described first clock switch (Φ 1) is connected with described common-mode voltage；Described 5th inverting input is connected with the first end of described 43rd electric capacity respectively, It is connected with the first end of described 44th electric capacity；The first end of described 44th electric capacity is also by described 3rd clock switch (Φ 3) is connected with described common-mode voltage；Described second clock switch (Φ 2) and institute are passed through in second end of described 43rd electric capacity State 20 difference output ends to connect；Second end of described 44th electric capacity pass through described first clock switch (Φ 1) with described Second end of the 43rd electric capacity connects；Second end of described 44th electric capacity switchs (Φ 2) also by described second clock It is connected with described 18th difference output end；Wherein, the second end of described 44th electric capacity is opened also by described first clock Close (Φ 1) to be connected with described tenth differential input end (52)；20th difference output end of described 3rd operational amplifier and institute State the tenth difference output end (54) to connect；

Described 15th difference output end (83) of the second latch described in described second subnumber weighted-voltage D/A converters at different levels all with right First control end (94) described in described second multiplying digital-to-analog converter answered connects；In described second subnumber weighted-voltage D/A converters at different levels Described 16th difference output end (84) of described second latch all with institute in corresponding described second multiplying digital-to-analog converter State the second control end to connect.

9. production line analog-digital converter according to claim 4 is it is characterised in that described 3rd subnumber weighted-voltage D/A converter is by seven Individual 3rd comparator composition；Wherein, each the 3rd comparator includes：5th prime amplifier, the 6th prime amplifier and the 3rd latch Device；It is anti-phase that described 5th prime amplifier includes the 6th in-phase input end, the 6th inverting input, the 6th in-phase output end and the 6th Outfan；Described 6th prime amplifier includes the 7th in-phase input end, the 7th inverting input, the 7th in-phase output end and the 7th Reversed-phase output；Described 3rd latch include the 21st differential input end (201), the 22nd differential input end (202), 21st difference output end (203), the 22nd difference output end (204)；

Described 6th reversed-phase output is connected with described 7th in-phase input end, and described 6th in-phase output end is anti-with the described 7th Phase input connects；Described 7th reversed-phase output is connected with described 21st differential input end (201), described 7th homophase Outfan is connected with described 22nd differential input end (202)；

Wherein, described 6th in-phase input end of the 5th prime amplifier described in each the 3rd comparator passes through the 45th electric capacity (C45) it is connected by second clock switch (Φ 2) with described 11st differential input end (61), and pass through the described 45th Electric capacity (C45) is connected by the first clock switch (Φ 1) with the 5th reference voltage；Described in each the 3rd comparator, the 5th puts in advance Described 6th inverting input of big device passes through the 46th electric capacity (C46) and passes through institute with described 12nd differential input end (62) State second clock switch (Φ 2) to connect, and pass through described the by described 46th electric capacity (C46) and the 6th reference voltage One clock switch (Φ 1) connects；Described 21st difference output end of the 3rd latch described in each the 3rd comparator (203) it is connected with described 11st difference output end (63)；Described the second of 3rd latch described in each the 3rd comparator 12 difference output ends (204) are connected with described 12nd difference output end (64).