CN104143553A - Memory device and method of manufacturing the same - Google Patents

Abstract

The invention relates to a memory element and a manufacturing method thereof. The memory device includes a substrate, a plurality of insulating structures, a plurality of bit lines, a plurality of dielectric layers, a plurality of pairs of charge storage structures, and a plurality of word lines. The substrate has a plurality of trenches arranged along a first direction. The insulating structure is located in the trench. The bit line is located in the substrate below the insulating structure. Each dielectric layer is located on the substrate between two adjacent insulating structures. Each charge storage structure is located on the substrate between the adjacent insulating structure and the dielectric layer. The word lines are arranged along a second direction and cover the insulating structure, the charge storage structure, the dielectric layer and part of the substrate. The memory device of the present invention can provide localized charge storage regions to allow complete localized storage of charge, reduce second bit effects, and reduce programming disturb. The invention also provides a method for manufacturing the memory element.

Description

Memory element and manufacturing method thereof

technical field

The invention relates to a memory element and a manufacturing method thereof.

Background technique

Non-volatile memory allows multiple data programming, reading, and erasing operations, and the data stored in it can be preserved even after the memory's power supply is interrupted. Due to these advantages, non-volatile memory has become a widely used memory in personal computers and electronic equipment.

Well-known electrically programmable and erasable non-volatile memory technologies using charge storage structures, such as electronically programmable and erasable read-only memory (EEPROM) and flash memory Memory (flash memory) has been used in various modern applications. A typical flash memory cell stores charge in a floating gate. Another type of flash memory uses a charge-trapping structure composed of a non-conductive material, such as silicon nitride, to replace the conductive material of the floating gate. When charge-trapping memory cells are woven, charges are trapped and do not move through the non-conductive charge-trapping structure. When the power is not continuously supplied, the charge will remain in the charge trapping layer, maintaining its data state until the memory cell is erased. Charge trapping memory cells can be operated as two-sided cells. That is, since the charges do not move through the nonconductive charge trapping layer, the charges can be located at different charge traps. In other words, in the charge-trapping flash memory device, more than one bit of information can be stored in each memory cell.

Operating margin (memory operation window). In other words, memory operating margin is defined by the difference between program level and erase level. Since memory cell operations require good level separation between various states, large memory operating margins are required. However, the performance of 2-bit memory cells usually decreases with the so-called "second bit effect". Under the second-bit effect, the localized charges in the charge-trapping structure influence each other. For example, during reverse read, a read bias is applied to the drain terminal and the charge stored near the source region (ie, the first bit) is detected. However, the bit near the drain region (ie, the second bit) then creates a potential barrier to read the first bit near the source region. This energy barrier can be overcome by applying an appropriate bias voltage, using the drain-induced energy barrier lowering (DIBL) effect to suppress the effect of the second bit near the drain region and allow detection of the storage state of the first bit. However, when the second bit near the drain region is programmed to a high threshold voltage state and the first bit near the source region is in an unprogrammed state, the second bit substantially raises the energy barrier. Therefore, as the threshold voltage with respect to the second bit increases, the read bias voltage of the first bit is not sufficient to overcome the potential barrier generated by the second bit. Therefore, since the threshold voltage of the second bit is increased, the threshold voltage of the first bit is increased, thereby reducing the operating margin of the memory. The second bit effect reduces the operating margin of 2-bit memory.

In addition, the weaving of the memory cell can utilize channel hot electron injection, and generate hot electrons in the channel region. When the memory cells on the drain side are programmed, due to the thermal electron drift of the programmed memory cells, it will also cause the interference problem that the memory cells on the adjacent source side are programmed at the same time.

It can be seen that the above-mentioned existing memory element and its manufacturing method obviously still have inconveniences and defects in product structure, manufacturing method and use, and need to be further improved urgently. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure and method for general products and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve. Therefore, how to create a new memory element and its manufacturing method to suppress the second bit effect and avoid programming interference is one of the current important research and development issues, and it has also become a goal that the industry needs to improve.

Contents of the invention

The purpose of the present invention is to overcome the defects of the existing memory elements and provide a new memory element. The technical problem to be solved is to provide a positioned charge storage area so that the charges can be completely positioned and stored. Reduce the second bit effect, reduce the behavior of editing interference, very suitable for practical use.

Another object of the present invention is to overcome the defects of the existing memory element manufacturing method, and provide a new memory element manufacturing method, the technical problem to be solved is to make it possible to make the manufactured The memory element can provide a positioned charge storage area, so that the charge can be completely positioned and stored, a better second bit can be obtained, and the behavior of programming interference can be reduced, so it is more suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A memory element proposed according to the present invention includes a substrate, multiple first insulating structures, multiple bit lines, multiple dielectric layers, multiple pairs of charge storage structures, and multiple word lines. There are multiple ditches in the base, and each ditch is arranged along the first direction. The first insulating structure is located in the trench. The bit line is located in the substrate under the first insulating structure. Each dielectric layer is located on the base between two adjacent first insulating structures. Each charge storage structure is located on the substrate between adjacent first insulating structures and the dielectric layer. Each word line is arranged along the second direction, covering the first insulating structure, the charge storage structure, the dielectric layer and part of the substrate.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned memory element, each word line is composed of a single conductor layer, and the single conductor layer is filled in the first gap between two adjacent pairs of charge storage structures and between each pair of charge storage structures the second gap.

The aforementioned memory element further includes a plurality of second insulating structures, and wherein each second insulating structure is located on the corresponding first insulating structure and filled in the first insulating structure between two adjacent pairs of charge storage structures. gap. Each word line includes a patterned first conductor layer and a patterned second conductor layer. Wherein, each patterned first conductor layer is located between two adjacent second insulating structures, fills the second gap between each pair of charge storage structures, and covers the charge storage structures and the a dielectric layer; and the patterned second conductor layer covering the patterned first conductor layer and the second insulating structure.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. A memory element proposed according to the present invention includes: a substrate, a plurality of first insulating structures, a plurality of bit lines, a plurality of dielectric layers, a plurality of pairs of charge storage structures and a plurality of word lines. There are multiple ditches in the base, and each ditch is arranged along the first direction. The above-mentioned first insulating structure is located in the trench. The bit line is located in the substrate under the first insulating structure. Each dielectric layer is located on the base between two adjacent first insulating structures. Each charge storage structure is located on the substrate between adjacent first insulating structures and the dielectric layer. Each word line is arranged along the second direction. The word line is composed of a single conductor layer, and the conductor layer is filled in the first gap between two adjacent pairs of charge storage structures and between each pair of charge storage structures. and in contact with the first insulating structure, the charge storage structure, the dielectric layer, and part of the substrate.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The aforementioned memory device, wherein the charge storage structure includes a dielectric charge storage layer.

The purpose of the present invention and its technical problems are solved by adopting the following technical solutions in addition. A method for manufacturing a memory element according to the present invention includes: forming a plurality of trenches in a substrate, and each trench is arranged along a first direction. A plurality of first insulating structures are formed in the trenches. A plurality of bit lines are formed, and the bit lines are located in the substrate under the first insulating structure. A plurality of dielectric layers are formed, and each dielectric layer is located on the substrate between two adjacent first insulating structures. Multiple pairs of charge storage structures are formed, and each charge storage structure is located on the substrate between adjacent first insulating structures and the dielectric layer. A plurality of word lines are formed, and each word line is arranged along a second direction, covering the first insulating structure, the charge storage structure, the dielectric layer and part of the substrate.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The manufacturing method of the aforementioned memory element, wherein the step of forming the word line includes: forming a single conductor layer; and patterning the single conductor layer to form the word line, and the word line is filled in two adjacent A first gap between pairs of charge storage structures and a second gap between each pair of charge storage structures are in contact with the first insulating structure, the charge storage structure, the dielectric layer and part of the substrate.

In the aforementioned manufacturing method of a memory element, wherein the method for forming the charge storage structure, the dielectric layer, the bit line, and the word line includes: forming a charge storage stack layer on the substrate. The charge storage stack layers are patterned to form a plurality of patterned charge storage stack layers with the second gaps between the patterned charge storage stack layers. The dielectric layer is formed in the second gap. A mask layer is formed to cover the patterned charge storage stack layer, the dielectric layer and the substrate, and is filled in the second gap. patterning the mask layer and the patterned charge storage stack layer to form a plurality of patterned mask layers and the charge storage structure, and forming the first gap, exposing the first an insulating structure. Using the patterned mask layer as a mask, an ion implantation process is performed to form the bit line in the substrate under the first insulating structure. The patterned mask layer is removed to expose the second gap and the first gap. The word lines are formed.

The aforementioned method for manufacturing a memory element, wherein the step of forming the word line includes: forming a plurality of patterned first conductor layers, and the patterned first conductor layers are located in the second gap between each pair of charge storage structures , and cover the charge storage structure, exposing the first insulating structure. A plurality of second insulating structures are formed, and the second insulating structures are filled in the first gap between two adjacent pairs of charge storage structures and cover the first insulating structures. A plurality of patterned second conductor layers are formed, and the patterned second conductor layers cover the patterned first conductor layer and the second insulating structure.

The aforementioned method for manufacturing a memory element, wherein the method for forming the charge storage structure, the dielectric layer, the bit line, the patterned first conductor layer, and the second insulating structure includes: A charge storage stack layer is formed on the substrate. The charge storage stack layers are patterned to form a plurality of patterned charge storage stack layers with the second gaps between the patterned charge storage stack layers. The dielectric layer is formed in the second gap. A first conductor layer is formed to cover the patterned charge storage stack layer, the dielectric layer and the substrate, and fill in the second gap. patterning the first conductor layer and the patterned charge storage stack layer to form the patterned first conductor layer and the charge storage structure, and forming the first gap, exposing the first an insulating structure. Using the patterned first conductor layer as a mask, an ion implantation process is performed to form the bit line in the substrate under the first insulating structure. The second insulating structure is formed in the first gap.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. By virtue of the above technical solutions, the memory element and its manufacturing method of the present invention have at least the following advantages and beneficial effects:

The memory element of the present invention can provide a localized charge storage area, so that the charge can be completely localized and stored, reducing the second bit effect, and reducing the behavior of programming interference.

The manufacturing method of the memory element of the present invention can make the manufactured memory element provide a positioned charge storage area through a simple process, so that the charge can be completely positioned and stored, a better second bit can be obtained, and the programming interference can be reduced the behavior of.

In summary, the present invention relates to a memory element and a manufacturing method thereof. The memory element includes a substrate, a plurality of insulating structures, a plurality of bit lines, a plurality of dielectric layers, a plurality of pairs of charge storage structures and a plurality of word lines. There are multiple ditches in the base, and each ditch is arranged along the first direction. The insulating structure is located in the trench. The bit line is located in the substrate below the insulating structure. Each dielectric layer is located on the base between two adjacent insulating structures. Each charge storage structure is located on the substrate between adjacent insulating structures and the dielectric layer. Each word line is arranged along the second direction, covering the insulating structure, the charge storage structure, the dielectric layer and part of the substrate. The present invention has significant progress in technology, and has obvious positive effects, and is a novel, progressive and practical new design.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows.

Description of drawings

FIG. 1A is a top view illustrating a memory device according to the first embodiment of the present invention.

FIG. 1B is a cross-sectional view along line I-I of FIG. 1A .

FIG. 1C is a cross-sectional view along line II-II of FIG. 1A .

2A to 2E are cross-sectional views illustrating a manufacturing method of a memory device according to the first embodiment of the present invention.

FIG. 3A is a top view illustrating a memory device according to a second embodiment of the present invention.

FIG. 3B is a cross-sectional view along line IV-IV of FIG. 3A .

FIG. 3C is a cross-sectional view of FIG. 3A along line V-V.

4A to 4D are cross-sectional views illustrating a manufacturing method of a memory device according to a second embodiment of the present invention.

FIG. 5 is a graph showing the initial voltage distribution curves of the memory element in the prior art and the second embodiment of the present invention.

10: Base 12: Ditch

14: Pad oxide layer 16: Mask layer

18, 40: Insulation structure 20: Well area

22, 26: Silicon oxide layer 24: Silicon nitride layer

28: Charge storage stack 29: Patterned charge storage stack

30: Charge storage structure 32, 38: Gap

34: Dielectric layer 36: Conductor layer

36a, 42: patterned conductor layer 44, 54: word line

50: bit line 100, 200: curve

I-I, II-II, IV-IV, V-V: hatching

Detailed ways

In order to further explain the technical means and effects that the present invention adopts to achieve the intended purpose of the invention, below in conjunction with the accompanying drawings and preferred embodiments, the specific implementation, structure, method, Steps, features and effects thereof are described in detail below.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of specific embodiments, it should be possible to obtain a deeper and more specific understanding of the technical means and effects of the present invention to achieve the intended purpose, but the attached drawings are only for reference and description, and are not used to explain the present invention. be restricted.

FIG. 1A is a top view illustrating a memory device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view along line I-I of FIG. 1A . FIG. 1C is a cross-sectional view along line II-II of FIG. 1A .

Please refer to FIG. 1A, FIG. 1B and FIG. 1C, a memory element according to the first embodiment of the present invention includes a substrate 10, a plurality of bit lines 50, a plurality of word lines 44, a plurality of pairs of charge storage structures 30, a plurality of interlayers The electrical layer 34 , the plurality of insulating structures 18 and the plurality of insulating structures 40 . Each memory cell includes a word line 44 , two bit lines 50 , two charge storage structures 30 , and a dielectric layer 34 . The two charge storage structures 30 are physically separated by a dielectric layer 34 and a word line 44 .

The substrate 10 has a well region 20 therein. The well region 20 has a plurality of trenches 12 extending along a first direction and arranged in a parallel or substantially parallel manner. An insulating structure 18 is located in the trench 12 . The bit line 50 is located in the well region 20 below the insulating structure 18 . Each dielectric layer 34 is located on the well region 20 between two adjacent insulating structures 18 . Each charge storage structure 30 is located on the substrate 10 between adjacent insulating structures 18 and dielectric layers 34 . The insulating structure 40 is located on the corresponding insulating structure 18 and fills the gap 38 between two adjacent pairs of charge storage structures 30 . A plurality of word lines 44 extend along the second direction and are arranged in a parallel or substantially parallel manner, covering the insulating structure 18 , the charge storage structure 30 , the dielectric layer 34 and part of the well region 20 . Each word line 44 includes a patterned conductor layer 36 a and a patterned conductor layer 42 . Each patterned conductive layer 36a is located between two adjacent insulating structures 40, fills the gap 32 between each pair of charge storage structures 30, and covers the charge storage structures 30, the dielectric layer 34 and the well region 20. , whose cross section is, for example, T-shaped. Each patterned conductive layer 42 extends in the second direction, covering the patterned conductive layer 36 a and the insulating structure 40 . The second extending direction and the first extending direction may be perpendicular to each other, or substantially perpendicular to each other.

2A to 2E are cross-sectional views illustrating a manufacturing method of a memory device according to the first embodiment of the present invention.

Referring to FIG. 2A , a plurality of trenches 12 are formed in the substrate 10 , and the trenches 12 extend along a first direction and are arranged in a parallel or substantially parallel manner. The substrate 10 can be a semiconductor substrate, such as a silicon substrate, or a semiconductor compound substrate, such as a gallium arsenide substrate. The trench 12 can be formed by forming a patterned pad oxide layer 14 and a mask layer 16 on the substrate 10 and then etching the substrate 10 . The depth of the trench 12 is, for example, 300 to 1500 angstroms.

The pad oxide layer 14 can be formed by thermal oxidation or chemical vapor deposition. The material of the mask layer 16 can be silicon nitride, and its formation method is, for example, chemical vapor deposition.

An insulating structure 18 is formed within the trench 12 . The method for forming the insulating structure 18 is, for example, forming an insulating layer on the substrate 10, the insulating layer covers the mask layer 16 and fills the trench 12, and then performs a chemical mechanical polishing process or an etching process to remove the insulating layer outside the trench 12. . The material of the insulating layer is, for example, silicon oxide or other dielectric materials, and the method of forming it is, for example, chemical vapor deposition.

Please refer to FIG. 2B , after that, the mask layer 16 and the pad oxide layer 14 are removed. Then, well region 20 is formed in substrate 10 . The well region 20 can be formed by ion implantation. The dopant of the first conductivity type in the well region 20 is, for example, a P-type dopant, such as boron or boron difluoride ions.

Afterwards, a charge storage stack layer 28 is formed on the substrate 10 . The charge storage stack 28 includes a dielectric charge storage layer, such as silicon nitride. In one embodiment, the charge storage structure 30 includes a silicon oxide layer 22 , a silicon nitride layer 24 and a silicon oxide layer 26 . The silicon oxide layer 22 and the silicon oxide layer 26 are formed by thermal oxidation, chemical vapor deposition or in-situ steam generation, for example. The silicon nitride layer 24 can be formed by furnace nitriding or chemical vapor deposition. The thicknesses of the silicon oxide layer 22 , the silicon nitride layer 24 and the silicon oxide layer 26 may be, for example, 25 to 45 angstroms, 45 to 65 angstroms and 80 to 120 angstroms, respectively.

Referring to FIG. 2C , the charge storage stack layer 28 is patterned to form a patterned charge storage stack layer 29 . The patterned charge storage stack layer 29 is located above the insulating structure 18 and extends to the well region 20 on both sides of the insulating structure 18 . There is a gap 32 between two adjacent patterned charge storage stack layers 29 .

Next, a dielectric layer 34 is formed in the gap 32 between two adjacent patterned charge storage stack layers 29 . The material of the dielectric layer 34 is, for example, silicon oxide, and its forming method is, for example, thermal oxidation. The thickness of the dielectric layer 34 is, for example, 25 to 70 angstroms.

Afterwards, a conductor layer 36 is formed on the substrate 10 . Conductor layer 36 covers patterned charge storage stack 29 , fills gap 32 , and covers dielectric layer 34 . The material of the conductive layer 36 is, for example, doped polysilicon, and its formation method is, for example, chemical vapor deposition or sputtering. The material of the conductive layer 36 is, for example, doped polysilicon, and the formation method is, for example, chemical vapor deposition. The thickness of the conductive layer 36 is, for example, 300 to 500 angstroms.

Thereafter, as shown in FIG. 2D , the conductive layer 36 and the patterned charge storage stack layer 29 are patterned to form the patterned conductive layer 36 a, the charge storage structure 30 and the gap 38 . There is a pair of charge storage structures 30 on the substrate 10 between two adjacent insulating structures 18, and there is a gap 32 between each pair of charge storage structures 30, and a dielectric layer 34 is filled in the gap 32; and the patterned The conductive layer 36 a covers the charge storage structure 30 , fills in the gap 32 , and covers the dielectric layer 34 . The gap 38 is located between two adjacent pairs of charge storage structures 30 , exposing the insulating structure 18 .

Afterwards, bit lines 50 (or referred to as source and drain regions) are formed in the well region 20 under the insulating structure 18 . The formation method of the bit line 50 is, for example, using the patterned conductive layer 36 a as a mask to perform an ion implantation process to implant dopants of the second conductivity type into the well region 20 . The dopant of the second conductivity type is an N-type dopant, such as phosphorus or arsenic.

Thereafter, as shown in FIG. 2E , an insulating structure 40 is formed in the gap 38 . The material of the insulating layer 40 is, for example, silicon oxide or other dielectric materials. A method for forming the insulating structure 40 is, for example, forming an insulating layer (not shown) on the substrate 10 . The insulating layer covers the patterned conductive layer 36 a and fills in the gap 38 . Then, a chemical mechanical polishing process or an etching process is performed to remove the insulating layer outside the gap 38 .

Afterwards, a patterned conductor layer 42 is formed on the substrate 10 . The patterned conductive layer 42 extends along the second direction, is arranged in parallel or substantially parallel, and covers the insulating structure 40 and the charge storage structure 30 . The formation method of the patterned conductor layer 42 is, for example, forming a conductor material layer and then patterning through lithographic etching. The material of the conductive material layer of the patterned conductive layer 42 is, for example, doped polysilicon, which is formed by, for example, chemical vapor deposition or sputtering, with a thickness of, for example, 200 to 700 angstroms. Before forming the conductive material layer, an etching process may be performed to remove the native oxide layer formed on the surface of the patterned conductive layer 36a. The patterned conductive layer 42 and the patterned conductive layer 36 a serve as word lines 44 .

FIG. 3A is a top view illustrating a memory device according to a second embodiment of the present invention. FIG. 3B is a cross-sectional view along line IV-IV of FIG. 3A . FIG. 3C is a cross-sectional view of FIG. 3A along line V-V.

Referring to FIG. 3A, FIG. 3B and FIG. 3C, a memory element according to the second embodiment of the present invention includes a substrate 10, a plurality of bit lines 50, a plurality of word lines 54, a plurality of pairs of charge storage structures 30, and a plurality of interlayers. Electrical layer 34 and a plurality of insulating structures 18 . Each memory cell includes a word line 54 , two bit lines 50 , two charge storage structures 30 , and a dielectric layer 34 . The two charge storage structures 30 are physically separated by the dielectric layer 34 and the word line 54 .

The substrate 10 has a well region 20 therein. The well region 20 has a plurality of trenches 12 extending along a first direction and arranged in a parallel or substantially parallel manner. An insulating structure 18 is located in the trench 12 . The bit line 50 is located in the well region 20 below the insulating structure 18 . Each dielectric layer 34 is located on the well region 20 between two adjacent insulating structures 18 . Each charge storage structure 30 is located on the substrate 10 between adjacent insulating structures 18 and dielectric layers 34 . A plurality of word lines 54 extend along the second direction and are arranged in a parallel or substantially parallel manner. Each word line 54 is composed of a single patterned conductor layer, which fills the gap 38 between two adjacent pairs of charge storage structures 30, covers the insulating structure 18, and fills the space between each pair of charge storage structures 30. The gap 32 covers the dielectric layer 34 , the charge storage structure 30 and the well region 20 . In other words, the word line 54 formed by a single patterned conductor layer extends in the second direction, and its shape is, for example, a comb shape.

4A to 4D are cross-sectional views illustrating a manufacturing method of a memory device according to a second embodiment of the present invention.

Please refer to FIG. 4A , according to the method of the above-mentioned first embodiment, a plurality of trenches 12 extending along the first direction and arranged in parallel or substantially parallel manner are formed in the substrate 10, and an insulating structure is formed in the trenches 12. 18. Then, well region 20 is formed in substrate 10 . Afterwards, a patterned charge storage stack layer 29 is formed on the substrate 10 . Next, a dielectric layer 34 is formed in the gap 32 between two adjacent patterned charge storage stack layers 29 .

Thereafter, a hard mask layer 46 is formed on the substrate 10 . A hard mask layer 46 covers the patterned charge storage stack layer 29 , fills the gap 32 , and covers the dielectric layer 34 . The material of the hard mask layer 46 is, for example, silicon nitride, and its formation method is, for example, chemical vapor deposition or furnace tube nitriding. The thickness of the hard mask layer 46 is, for example, 500 to 1000 angstroms.

Thereafter, as shown in FIG. 4B , the hard mask layer 46 and the patterned charge storage stack layer 29 are patterned to form the patterned hard mask layer 46 a , the charge storage structure 30 and the gap 38 . There is a pair of charge storage structures 30 on the substrate 10 between two adjacent insulating structures 18, and there is a gap 32 between each pair of charge storage structures 30, and a dielectric layer 34 is filled in the gap 32; and the patterned The hard mask layer 46 a covers the charge storage structure 30 , fills in the gap 32 , and covers the dielectric layer 34 . The gap 38 is located between two adjacent pairs of charge storage structures 30 , exposing the insulating structure 18 .

Afterwards, a bit line 50 is formed in the well region 20 under the insulating structure 18 . The formation method of the bit line 50 is, for example, using the patterned hard mask layer 46 a as a mask to perform an ion implantation process to implant dopants of the second conductivity type into the well region 20 . The dopant of the second conductivity type is an N-type dopant, such as phosphorus or arsenic.

Thereafter, as shown in FIG. 4C , the patterned hard mask layer 46 a is removed to expose the charge storage structure 30 , the dielectric layer 34 and the insulating structure 18 .

Afterwards, as shown in FIG. 4D , a patterned conductor layer is formed on the substrate 10 to serve as word lines 54 . The word lines 54 extend along the second direction and are arranged in a parallel or substantially parallel manner. More specifically, each word line 54 is composed of a single patterned conductor layer, which fills the gap 38 between two adjacent pairs of charge storage structures 30, covers the insulating structure 18, and fills in each pair of charge storage structures 30. The gap 32 between the structures 30 covers the dielectric layer 34, the charge storage structure 30 and the well region 20 (FIG. 3C). In other words, the word lines 54 formed by a single patterned conductor layer extend in the second direction, and part of them extend toward the surface of the substrate 10 (downward), such as in a comb shape. The forming method of the word line 54 is, for example, forming a conductive material layer and then patterning through lithographic etching. The material of the conductive material layer of the patterned conductive layer 54 is, for example, doped polysilicon, which is formed by, for example, chemical vapor deposition or sputtering, and has a thickness of, for example, 300 to 700 angstroms.

The word line of the second embodiment of the present invention is composed of a single conductor layer, which can avoid the problem of using two layers of conductor layers to form a native oxide layer between the conductor layers. Therefore, an additional step of removing the native oxide layer may not be required. Simplify the process steps and improve the reliability of components.

Referring to FIG. 1C and FIG. 3C , in the above embodiment of the present invention, each memory cell includes a word line 44 / 54 , two bit lines 50 , two charge storage structures 30 , and a dielectric layer 34 . The two charge storage structures 30 are physically separated by the dielectric layer 34 and the word lines 44/54. According to the following formula, the embodiment of the present invention can narrow the distribution width of the threshold voltage and avoid the second bit effect.

$g_m=\frac{{\∂I}_{\mathrm{D.}}}{{\∂V}_G}|V_{\mathrm{D.}}\&Right\; Arrow;\frac{W}{L}{\mathrm{\μ}}_{\mathrm{no}}\frac{K_{\mathrm{ox}}}{t_{\mathrm{ox}}}{V}_{\mathrm{D.}}$ linear region

$\&Right\; Arrow;\frac{W}{L}{\mathrm{\μ}}_{\mathrm{no}}\frac{K_{\mathrm{ox}}}{t_{\mathrm{ox}}}(V_G-V_T)$ saturation region

Where g _m is the transfer conductance (transconductance). _ID is the drain current. V _G is the gate voltage. W is the gate (word line) width. μ _n is electron/hole mobility (mobility). L is the gate length. K _ox is the oxide dielectric constant. t _ox is the oxide thickness. V _D is the drain voltage. V _T is the starting threshold voltage (threshold voltage).

FIG. 5 is a graph showing the distribution curves of the initial voltage of the memory device of the prior art and the memory device of the second embodiment of the present invention.

Please refer to FIG. 5 , compared with the initial voltage distribution curve 200 of the conventional memory device, the width of the initial voltage distribution curve 100 of the memory device according to the second embodiment of the present invention is narrower.

Please refer to FIG. 1C and FIG. 3C, in the above embodiment of the present invention, the insulating structure 18 in the well region 20 and the insulating structure 40 on the substrate 10 are used between the two charge storage structures 30 of two adjacent memory cells. separated (the first embodiment) or separated by the insulating structure 18 in the well region 20 and the word line 54 on the substrate 10 (the second embodiment), since the insulating structure 18 is located in the trench 12 with sufficient depth, Therefore, when the memory cells on the drain side are programmed, the thermal electron drift of the programmed memory cells can avoid the interference problem that the memory cells on the adjacent source side are also programmed simultaneously.

Based on the above, the two charge storage structures of the memory cell of the present invention are physically separated, so the second bit effect can be avoided. Two adjacent memory cells are separated by the insulating structure in the trench of the substrate and the insulating structure on the substrate, or separated by the insulating structure in the trench of the substrate and the word line on the substrate, so that weaving can be avoided. Interference (PDX) issues.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the method and technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but if they do not depart from the content of the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solutions of the present invention.

Claims (10)

1. A memory element, characterized in that it comprises: a base, the base has a plurality of trenches, and each trench is arranged along a first direction; a plurality of first insulating structures located in the trench; a plurality of bit lines located in the substrate below the first insulating structure; a plurality of dielectric layers, each dielectric layer is located on the substrate between two adjacent first insulating structures; a plurality of pairs of charge storage structures, each charge storage structure is located on the substrate between adjacent first insulating structures and the dielectric layer; and A plurality of word lines, each word line is arranged along a second direction, covering the first insulating structure, the charge storage structure, the dielectric layer and part of the substrate. 2. The memory device according to claim 1, wherein each word line is composed of a single conductor layer, and the single conductor layer is filled in the first layer between two adjacent pairs of charge storage structures. A gap and a second gap between each pair of charge storage structures. 3. The memory element according to claim 1, further comprising a plurality of second insulating structures, and wherein Each second insulating structure is located on the corresponding first insulating structure and fills a first gap between two adjacent pairs of charge storage structures; Each word line includes a patterned first conductor layer and a patterned second conductor layer, wherein: Each patterned first conductor layer is located between two adjacent second insulating structures, fills the second gap between each pair of charge storage structures, and covers the charge storage structures and the dielectric layers; and The patterned second conductor layer covers the patterned first conductor layer and the second insulating structure. 4. A memory element, characterized in that it comprises: a base, the base has a plurality of trenches, and each trench is arranged along a first direction; a plurality of first insulating structures located in the trench; a plurality of bit lines located in the substrate below the first insulating structure; a plurality of dielectric layers, each dielectric layer is located on the substrate between two adjacent first insulating structures; a plurality of pairs of charge storage structures, each charge storage structure is located on the substrate between adjacent first insulating structures and the dielectric layer; and A plurality of word lines, each word line is arranged along a second direction, the word line is composed of a single conductor layer, and the conductor layer is filled in the first gap between two adjacent pairs of charge storage structures and The second gap between each pair of charge storage structures is in contact with the first insulating structure, the charge storage structure, the dielectric layer and part of the substrate. 5. The memory device of claim 4, wherein the charge storage structure comprises a dielectric charge storage layer. 6. A method for manufacturing a memory element, characterized in that it comprises the following steps: forming a plurality of trenches in a substrate, each of the trenches being aligned along a first direction; forming a plurality of first insulating structures in the trench; forming a plurality of bit lines, each bit line is located in the substrate under the first insulating structure; forming a plurality of dielectric layers, each dielectric layer is located on the substrate between two adjacent first insulating structures; forming a plurality of pairs of charge storage structures, each charge storage structure being located on the substrate between adjacent first insulating structures and the dielectric layer; and A plurality of word lines are formed, and each word line is arranged along a second direction, covering the first insulating structure, the charge storage structure, the dielectric layer and part of the substrate. 7. The manufacturing method of the memory element according to claim 6, wherein the step of forming the word line comprises: forming a single conductor layer; and patterning the single conductor layer to form the word line, the word line fills the first gap between two adjacent pairs of charge storage structures and the second gap between each pair of charge storage structures, and is connected with The first insulating structure, the charge storage structure, the dielectric layer and a part of the base contact. 8. The manufacturing method of the memory element according to claim 7, wherein the forming method of the charge storage structure, the dielectric layer, the bit line and the word line comprises: forming a charge storage stack layer on the substrate; patterning the charge storage stack layer to form a plurality of patterned charge storage stack layers having the second gap therebetween; forming the dielectric layer in the second gap; forming a mask layer covering the patterned charge storage stack layer, the dielectric layer and the substrate, and filling in the second gap; patterning the mask layer and the patterned charge storage stack layer to form a plurality of patterned mask layers and the charge storage structure, and forming the first gap to expose the first an insulating structure; performing an ion implantation process using the patterned mask layer as a mask to form the bit line in the substrate under the first insulating structure; removing the patterned mask layer to expose the second gap and the first gap; and The word lines are formed. 9. The manufacturing method of the memory element according to claim 6, wherein the step of forming the word line comprises: forming a plurality of patterned first conductor layers, the patterned first conductor layers are located in the second gap between each pair of charge storage structures, and cover the charge storage structures, exposing the first insulating structure; forming a plurality of second insulating structures, the second insulating structures filling a first gap between two adjacent pairs of charge storage structures and covering the first insulating structures; and A plurality of patterned second conductor layers are formed, and the patterned second conductor layers cover the patterned first conductor layer and the second insulating structure. 10. The manufacturing method of the memory element according to claim 9, wherein the charge storage structure, the dielectric layer, the bit line, the patterned first conductor layer and the second The method of forming the insulating structure includes: forming a charge storage stack layer on the substrate; patterning the charge storage stack layer to form a plurality of patterned charge storage stack layers having the second gap therebetween; forming the dielectric layer in the second gap; forming a first conductor layer covering the patterned charge storage stack layer, the dielectric layer and the substrate, and filling in the second gap; patterning the first conductor layer and the patterned charge storage stack layer to form the patterned first conductor layer and the charge storage structure, and forming the first gap to expose the first an insulating structure; performing an ion implantation process using the patterned first conductor layer as a mask to form the bit line in the substrate under the first insulating structure; and The second insulating structure is formed in the first gap.