CN104183481B - Method for improving deposition quality of metal barrier layer - Google Patents
Method for improving deposition quality of metal barrier layer Download PDFInfo
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- CN104183481B CN104183481B CN201410428647.4A CN201410428647A CN104183481B CN 104183481 B CN104183481 B CN 104183481B CN 201410428647 A CN201410428647 A CN 201410428647A CN 104183481 B CN104183481 B CN 104183481B
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- Prior art keywords
- barrier layer
- semiconductor substrate
- metal barrier
- stripping
- deposition
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000002184 metal Substances 0.000 title claims abstract description 60
- 230000004888 barrier function Effects 0.000 title claims abstract description 54
- 230000008021 deposition Effects 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 27
- 238000002955 isolation Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 230000001680 brushing effect Effects 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 10
- 238000007791 dehumidification Methods 0.000 abstract description 6
- 238000005137 deposition process Methods 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 3
- 230000008646 thermal stress Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021642 ultra pure water Inorganic materials 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for improving the deposition quality of a metal barrier layer, which comprises the step of carrying out preheating treatment on the surface of a semiconductor substrate before carrying out dehumidification treatment on the surface of the semiconductor substrate, wherein the preheating treatment can cause the generation of stripping substances on the back surface of the edge of the semiconductor substrate due to nonuniform heating. And then the stripping objects are removed by a brushing process, and then a subsequent dehumidification process, a pre-cleaning process and a metal barrier layer deposition process are carried out, so that the stripping defect generated after the existing metal barrier layer is deposited is avoided, the deposition quality of the metal barrier layer is improved, the subsequent process is favorably carried out smoothly, and the quality of the whole device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving the deposition quality of a metal barrier layer.
Background
With the development of integrated circuit processes and the scaling down of critical dimensions, new processes are continuously introduced, such as a metal barrier layer process in a back-end process, and referring to fig. 1, a schematic flow chart of a conventional metal barrier layer deposition method is shown, which mainly includes the following steps:
step L01: removing moisture on the surface of the semiconductor substrate at high temperature; the temperature for removing moisture is relatively high, generally around 350 ℃.
Step L02: pre-cleaning the surface of the semiconductor substrate;
Step L03: and depositing a metal barrier layer on the surface of the semiconductor substrate.
After the deposition of the above-mentioned metal barrier layer, lift-off defects often occur for the following reasons: due to the complexity of the back-end process, the defects of uneven surface and the like inevitably exist at the position of the edge of the semiconductor substrate close to the back surface before the metal barrier layer is deposited; the high temperature environment of removing moisture in the step L01 causes uneven thermal stress on the back side of the edge of the semiconductor substrate, and thus, the edge of the semiconductor substrate may have a peeling object, which may fall on any part of the surface of the semiconductor substrate including the functional region.
Generally, the method for solving the defect of the stripped object is to perform a brushing process on the surface of the semiconductor substrate after the deposition process of the metal barrier layer is completed, and although the brushing process can remove the stripping defect on the surface of the semiconductor substrate, part of the metal barrier layer is also removed at the same time, so that the completeness of the metal barrier layer is damaged. Since the stripper is usually located in the functional region of the semiconductor substrate, the metal barrier layer covering the stripper is removed along with the stripping of the stripper, which may result in the metal barrier layer of the functional region being missing; the metal barrier layer is important for the subsequent process, and therefore, it is important to study the method for removing the stripping material.
in another method, the semiconductor substrate is optimized by adding an etching process to the edge of the semiconductor substrate, but this method requires a professional etching machine and needs to evaluate the influence on the whole process, which consumes a lot of manpower and material resources, and thus, is not an optimized method.
Disclosure of Invention
In order to overcome the problems, the invention aims to provide a method for improving the deposition quality of a metal barrier layer, so that a stripping object on the surface of a semiconductor substrate is removed before the metal barrier layer is deposited, and the stripping defect generated after the metal barrier layer is deposited is avoided.
The invention provides a method for improving the deposition quality of a metal barrier layer, which comprises the following steps:
Step 01: providing a semiconductor substrate with a dielectric layer on the surface;
Step 02: carrying out preheating treatment on the semiconductor substrate;
Step 03: carrying out a brushing process on the surface of the semiconductor substrate;
step 04; removing moisture on the surface of the semiconductor substrate and performing a pre-cleaning process;
step 05: and depositing a metal barrier layer on the semiconductor substrate.
Preferably, the step 01 includes: the forming of the dielectric layer comprises depositing an etching barrier layer and a metal isolation layer on the semiconductor substrate in sequence; the step 05 comprises the following steps: and depositing a metal barrier layer on the surface of the metal isolation layer.
Preferably, in the step 02, the temperature used for the preheating treatment is 350-450 ℃.
preferably, in the step 02, the preheating treatment is performed in a vacuum environment for more than 3 seconds.
Preferably, in the step 03, the brushing process is performed by using water.
According to the method for improving the deposition quality of the metal barrier layer, the surface of the semiconductor substrate is subjected to preheating treatment before being subjected to dehumidification treatment, and the preheating treatment can cause the stripping substances on the back surface of the edge of the semiconductor substrate due to nonuniform heating. And then the stripping objects are removed by a brushing process, and then a subsequent dehumidification process, a pre-cleaning process and a metal barrier layer deposition process are carried out, so that the stripping defect generated after the existing metal barrier layer is deposited is avoided, the deposition quality of the metal barrier layer is improved, the subsequent process is favorably carried out smoothly, and the quality of the whole device is improved.
drawings
Fig. 1 is a schematic flow chart of a conventional metal barrier layer deposition method.
Fig. 2 is a flow chart illustrating a method for improving the deposition quality of a metal barrier layer according to a preferred embodiment of the invention.
Detailed Description
in order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
As described above, due to the complexity of the back-end process, the back surface of the edge of the semiconductor substrate may have unevenness before the deposition of the metal barrier layer, and the conventional metal barrier layer deposition process may be subjected to a moisture removal process, which requires a high-temperature environment and may cause a problem of uneven thermal stress on the back surface of the edge of the semiconductor substrate, thereby causing a peeling-off object on the surface of the semiconductor substrate. Once the stripping matter falls on the functional area of the semiconductor substrate, the metal barrier layer is deposited on the functional area, and after the subsequent brushing process, the metal barrier layer of the functional area is removed, so that the smooth proceeding of the subsequent process and the performance of the whole device are influenced, and even the scrapping of the device is caused. Therefore, the invention provides a method for improving the deposition quality of a metal barrier layer, which comprises the step of carrying out preheating treatment on the surface of a semiconductor substrate before carrying out dehumidification treatment on the surface of the semiconductor substrate, wherein the preheating treatment can cause the stripping substances on the back surface of the edge of the semiconductor substrate due to nonuniform heating. And then the stripping objects are removed by a brushing process, and then a subsequent dehumidification process, a precleaning process and a metal barrier layer deposition process are carried out, so that the stripping defect generated after the existing metal barrier layer is deposited is avoided.
the method for improving the deposition quality of the metal barrier layer according to the present invention will be described in further detail with reference to fig. 2 and the specific embodiment. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.
Referring to fig. 2, a flow chart of a method for improving deposition quality of a metal barrier layer according to a preferred embodiment of the invention is shown, in which the method for improving deposition quality of a metal barrier layer of the present embodiment includes:
Step 01: providing a semiconductor substrate with a dielectric layer on the surface;
Specifically, the forming of the dielectric layer on the surface of the semiconductor substrate may include depositing an etching barrier layer and a metal isolation layer on the semiconductor substrate in sequence, which is not intended to limit the scope of the present invention; in the present invention, the dielectric layer may include a plurality of layers, for example, a Tetraethylorthosilicate (TEOS) layer may be further included under the metal isolation layer. The semiconductor substrate may be any substrate in a back-end process, for example, a semiconductor substrate having a contact hole structure or a metal interconnection structure below a dielectric layer.
Step 02: carrying out preheating treatment on the semiconductor substrate;
specifically, the specific process parameters of the pre-heating treatment may include, but are not limited to: under vacuum environment, inert atmosphere at 350-450 deg.C for more than 3 s. The inert atmosphere may be nitrogen or argon.
The semiconductor substrate is subjected to the preheating treatment, so that the semiconductor substrate can be in a certain high-temperature environment, the thermal stress on the back surface of the edge of the semiconductor substrate is uneven, and a stripping object is generated, so that the stripping object on the back surface of the edge of the semiconductor substrate is stripped from the semiconductor substrate through the preheating treatment, and the semiconductor substrate is conveniently brushed subsequently.
Step 03: carrying out a brushing process on the surface of the semiconductor substrate;
Specifically, the cleaning solution used in the brushing process may be water. Such as deionized water, ultrapure water, and the like, to avoid etching the surface of the semiconductor substrate. The brushing process may also be performed by conventional brushing methods, and the present invention is not described herein again.
therefore, the idea of the invention is that: firstly, the stripped objects are removed by utilizing the high temperature and the brushing process, and then the metal barrier layer is deposited.
step 04; removing moisture on the surface of the semiconductor substrate and performing a precleaning process;
Specifically, the step 04 may adopt a conventional moisture removal and pre-cleaning process, which is not limited by the present invention.
Step 05: a metal barrier layer is deposited on the semiconductor substrate.
specifically, in this embodiment, the dielectric layer on the outermost layer of the surface of the semiconductor substrate is a metal isolation layer, so that the metal barrier layer is deposited on the surface of the metal isolation layer, and the deposition method of the metal barrier layer may be, but is not limited to, a physical vapor deposition method.
it should be noted that, after the step 03, other steps in the existing metal barrier layer deposition process may be further included, and the present invention is not limited thereto.
in conclusion, the invention can effectively avoid the defect of stripping defects generated after the existing metal barrier layer is deposited, improves the deposition quality of the metal barrier layer, and is beneficial to the smooth operation of the subsequent process and the improvement of the quality of the whole device.
although the present invention has been described with reference to preferred embodiments, which are illustrated for the purpose of illustration only and not for the purpose of limitation, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (4)
1. A method for improving the deposition quality of a metal barrier layer is characterized by comprising the following steps:
Step 01: providing a semiconductor substrate with a dielectric layer on the surface;
Step 02: carrying out preheating treatment on the semiconductor substrate in a vacuum environment to cause the back of the edge of the semiconductor substrate to generate a stripping object due to nonuniform heating;
Step 03: adopting water to brush the surface of the semiconductor substrate;
Step 04; removing moisture on the surface of the semiconductor substrate and performing a pre-cleaning process;
step 05: and depositing a metal barrier layer on the semiconductor substrate.
2. the method for improving the deposition quality of the metal barrier layer according to claim 1, wherein the step 01 comprises: the forming of the dielectric layer comprises depositing an etching barrier layer and a metal isolation layer on the semiconductor substrate in sequence; the step 05 comprises the following steps: and depositing a metal barrier layer on the surface of the metal isolation layer.
3. The method according to claim 1, wherein the temperature used in the pre-heating treatment in step 02 is 350-450 ℃.
4. The method according to claim 1, wherein the preheating treatment is performed in a vacuum environment for more than 3 seconds in the step 02.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410428647.4A CN104183481B (en) | 2014-08-27 | 2014-08-27 | Method for improving deposition quality of metal barrier layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410428647.4A CN104183481B (en) | 2014-08-27 | 2014-08-27 | Method for improving deposition quality of metal barrier layer |
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| CN104183481A CN104183481A (en) | 2014-12-03 |
| CN104183481B true CN104183481B (en) | 2019-12-13 |
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| CN110459479B (en) * | 2018-05-07 | 2021-07-13 | 北京北方华创微电子装备有限公司 | Barrier layer deposition method, bottom metal film of gold bump and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1674215A (en) * | 2004-03-26 | 2005-09-28 | 力晶半导体股份有限公司 | How to make a barrier |
| CN1992221A (en) * | 2005-12-28 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating complementary metal oxide silicon image sensor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10146359B4 (en) * | 2001-09-20 | 2006-12-28 | Advanced Micro Devices, Inc., Sunnyvale | A metallization process sequence |
| JP2005142473A (en) * | 2003-11-10 | 2005-06-02 | Semiconductor Leading Edge Technologies Inc | Manufacturing method of semiconductor device |
| KR100875819B1 (en) * | 2007-09-20 | 2008-12-26 | 주식회사 동부하이텍 | Manufacturing Method of Semiconductor Device |
| CN101728229B (en) * | 2008-10-31 | 2011-11-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal pad |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1674215A (en) * | 2004-03-26 | 2005-09-28 | 力晶半导体股份有限公司 | How to make a barrier |
| CN1992221A (en) * | 2005-12-28 | 2007-07-04 | 东部电子股份有限公司 | Method of fabricating complementary metal oxide silicon image sensor |
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| CN104183481A (en) | 2014-12-03 |
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Effective date of registration: 20200414 Address after: 201203 1060, room 1, 298 Cambridge East Road, Pudong New Area, Shanghai. Patentee after: SHANGHAI HUALI INTEGRATED CIRCUIT MANUFACTURING Co.,Ltd. Address before: 201210, Gauss road 568, Zhangjiang hi tech park, Shanghai, Pudong New Area Patentee before: Shanghai Huali Microelectronics Corp. |
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