CN104183571B - Through silicon via and manufacturing process thereof - Google Patents

Abstract

The present invention discloses a through-silicon via and a manufacturing process thereof, wherein the through-silicon via comprises a substrate and a conductive plug. The substrate has a hole located in a surface. The conductive plug is disposed in the hole, and the conductive plug has an upper half protruding from the surface, wherein the upper half has a top and a bottom, and the top is thinner than the bottom. In addition, the present invention further provides a manufacturing process for forming the aforementioned through-silicon via. First, a substrate having a surface is provided. Then, a hole is formed from the surface of the substrate. Subsequently, a first conductive material is formed to cover the hole and the surface. Subsequently, a patterned photoresist is formed to cover the surface and expose the hole. Subsequently, a second conductive material is formed on the exposed first conductive material. Then, the patterned photoresist is removed. Thereafter, the first conductive material located on the surface is removed to form a conductive plug in the hole.

Description

Through silicon via and its manufacturing process

technical field

The present invention relates to a through-silicon crystal via and its manufacturing process, and in particular to a through-silicon crystal via forming a conductive filling material in a hole before forming a photoresist and its manufacturing process.

Background technique

Through-silicon via technology is mainly to solve the problem of interconnection between chips, which belongs to a new three-dimensional three-dimensional packaging technology. The popular through-silicon via technology creates light, thin, short, and small products that are more in line with market demand through three-dimensional stacking through silicon vias, and provides micro-electromechanical systems (MEMS), optoelectronics, and electronic components. The required packaging manufacturing process technology.

In detail, the TSV technology drills holes on the wafer by etching or laser, and then fills conductive materials such as copper, polysilicon, tungsten, etc. into the vias (Via) to form conductive channels (that is, connect internal and external splicing lines). Finally, the wafers or dies are thinned and then stacked and bonded to form a three-dimensional stacked integrated circuit (3DIC). In this way, it can replace the wire bonding method. Drilling holes (Via) and forming conductive electrodes by etching can not only save the wiring space, but also reduce the use area of the circuit board and the volume of the package. Because the internal bonding distance of the structure using TSV technology is the thickness of the thinned wafer or die, compared with the traditional stacked package that adopts wire bonding, the internal connection path of the three-dimensional stacked integrated circuit is much shorter. Shorter, relatively smaller transmission resistance between chips, faster speed, smaller noise, and better performance. Especially in central processing unit (CPU) and cache memory, as well as data transmission in memory card applications, it can highlight the performance advantages brought by the short-distance internal bonding path of TSV technology. In addition, the packaged size of the three-dimensional stacked integrated circuit is equivalent to the die size. In the field of portable electronic products that emphasize multi-function and small size, the miniaturization characteristics of three-dimensional space stacked integrated circuits are the primary factor for market introduction.

However, as the size of semiconductor devices shrinks, the TSVs in these semiconductor devices are difficult to form in the current semiconductor manufacturing process due to their high aspect ratio.

Contents of the invention

The object of the present invention is to provide a TSV and its manufacturing process. Before forming a photoresist, a conductive material is filled in a hole to form a part of the TSV, so that the TSV can be formed. Reduce the depth to which subsequent photoresist fills this hole.

To achieve the above purpose, the present invention provides a TSV, which includes a substrate and a conductive plug. The base has a hole located in one side. The conductive plug is arranged in the hole, and the conductive plug has an upper half protruding from the surface, wherein the upper half has a top and a bottom, and the top is thinner than the bottom.

The present invention provides a TSV manufacturing process, which includes the following steps. First, a substrate is provided, which has one side. Then, form a hole from the surface of the base. Next, a first conductive material is formed to cover the hole and the surface. Next, a patterned photoresist coverage is formed and the holes are exposed. Next, a second conductive material is formed on the exposed first conductive material. Then, the patterned photoresist is removed. Thereafter, the first conductive material on the surface is removed to form a conductive plug in the hole.

Based on the above, the present invention proposes a TSV and its manufacturing process. Before forming a patterned photoresist, a first conductive material is filled in a hole of a substrate. Therefore, the depth at which the photoresist is filled into the holes can be reduced so that the photoresist can be easily removed. Moreover, after the patterned photoresist is formed, a second conductive material is filled on the first conductive material in the hole, and then the patterned photoresist is removed, and then the photoresist located outside the hole is removed. The first conductive material is used to form a conductive plug. Since the first conductive material located outside the hole is removed by, for example, etching, the conductive plug protrudes from an upper half of the base, and has a thinner top than a bottom.

Description of drawings

1 is a schematic cross-sectional view illustrating a TSV manufacturing process according to an embodiment of the present invention;

2-4 are schematic cross-sectional views illustrating a TSV manufacturing process according to a first embodiment of the present invention;

5-10 are schematic cross-sectional views illustrating a TSV manufacturing process according to a second embodiment of the present invention;

11 is a schematic cross-sectional view illustrating a TSV manufacturing process according to an embodiment of the present invention;

FIG. 12 is a schematic cross-sectional view illustrating a TSV manufacturing process according to an embodiment of the present invention.

Description of main component symbols

100, 200: TSV

110, 310, 410: base

120, 120’, 220, 220’: barrier layer

130, 130', 230, 230': seed layer

140: main conductive material

150, 250: conductive pad

242: The first conductive material

242a: hole part

242b: surface part

246: Second conductive material

320, 420: interlayer dielectric layer

340, 440: multi-layer interconnection structure

C1, C2: Conductive plug

K1, K2: patterned photoresist

M: MOS transistor

S1: Surface

S2: front

S3: back

T1: top half

T11: top

T12: Bottom

T2: lower half

V, V1, V2: holes

detailed description

FIG. 1 is a schematic cross-sectional view illustrating a TSV manufacturing process according to an embodiment of the present invention. As shown in FIG. 1 , a substrate 110 having a hole V is provided. In this embodiment, the hole V is formed on one side S1 of the substrate 110 , wherein the side S1 may be the other side opposite to the active side, or the same side as the active side, but the invention is not limited thereto. The substrate 110 is, for example, a silicon substrate, a silicon-containing substrate, a group III-V silicon-on-silicon substrate (such as GaN-on-silicon), a graphene-on-silicon substrate (graphene-on-silicon), or a silicon-on-insulator (silicon-on-silicon) substrate. on-insulator, SOI) substrate and other semiconductor substrates. The hole V can be formed by etching, but the invention is not limited thereto. The hole V has a high aspect ratio for forming a TSV structure. Generally, the aspect ratio of the hole V is between 3.5-10, and its critical dimension (CD) is less than 18 micrometers (micrometer, μm), but the invention is not limited thereto.

Two embodiments are presented below, following the steps in FIG. 1 to form TSVs.

2-4 are schematic cross-sectional views illustrating a TSV manufacturing process according to a first embodiment of the present invention. As shown in FIG. 2 , a liner layer (not shown) is selectively formed to conformably cover the base 110 . The liner layer (not shown) is, for example, an oxide layer to electrically insulate the base 110 , but the invention is not limited to this material. Then, a barrier layer 120 is formed on the liner layer. The barrier layer 120 may include a single-layer or multi-layer structure composed of a titanium nitride layer or a tantalum nitride layer, but the invention is not limited thereto.

After that, a seed layer 130 is selectively formed on the barrier layer 120 . The seed layer 130 can be formed by a physical vapor deposition (PVD) process to provide the attachment of the main conductive material subsequently formed thereon, but the invention is not limited thereto. A patterned photoresist K1 is formed covering the surface S1 but exposing the holes V. In detail, a photoresist (not shown) may be formed first to fully cover the surface S1 and at least fill a part of the hole V. Then, photoresist is patterned to cover side S1 but expose holes V. FIG.

As shown in FIG. 3 , a main conductive material 140 is filled into the exposed hole V and formed on a part of the seed layer 130 . The main conductive material 140 may be composed of copper (Cu), for example, and may be formed by electroplating, but the invention is not limited thereto. Next, a conductive pad 150 is formed on the main conductive material 140 . The conductive pad 150 can be, for example, nickel, tin or gold, and it can be formed by pressing, but the invention is not limited thereto.

Afterwards, the patterned photoresist K1 is removed, and the exposed portion of the seed layer 130 and the barrier layer 120 located directly under the patterned photoresist K1 are removed together, thereby forming a barrier layer 120' and the seed layer 130', as shown in FIG. 4 . The patterned photoresist K1 , the seed layer 130 and the barrier layer 120 can be removed by the same manufacturing process, or can be removed sequentially by multiple manufacturing processes such as etching. Therefore, a plurality of conductive plugs C1 can be formed in the hole V, and the conductive plugs C1 can include the barrier layer 120', the seed layer 130' and the main conductive material 140.

As above, the TSV 100 is formed in the hole V of the substrate 110 , wherein the TSV 100 includes the conductive plug C1 and the conductive pad 150 . However, since the holes V for forming the TSVs 100 have an aspect ratio of 3.5˜10 and a critical dimension smaller than 18 μm, serious problems are encountered in forming the patterned photoresist K1 . Because when the photoresist is fully formed, the photoresist will also fill in the hole V, and when the photoresist is to be patterned to form a patterned photoresist K1, it will be located in the hole V However, the photoresist is difficult to remove due to the capillary phenomenon generated by the high aspect ratio of the holes V.

Therefore, a second embodiment is proposed below to form an improved TSV to solve the above problems. 5-10 are schematic cross-sectional views illustrating a TSV manufacturing process according to a second embodiment of the present invention.

After performing the steps in FIG. 1 , referring to FIG. 5 , a liner layer (not shown) is selectively formed to conformably cover the base 110 . The liner layer is, for example, an oxide layer to electrically insulate the base 110 , but the invention is not limited to this material. A barrier layer 220 and a seed layer 230 are sequentially formed to cover the hole V and the surface S1. The barrier layer 220 may comprise a single-layer or multi-layer structure composed of a titanium nitride layer or a tantalum nitride layer; the seed layer 230 may be formed by a physical vapor deposition (PVD) process to provide subsequent The conductive material formed thereon is used for adhering, but the present invention is not limited thereto.

As shown in FIG. 6 , a first conductive material 242 is formed to cover the hole V and the surface S1 , such that the first conductive material 242 includes a hole portion 242 a in the hole V and a surface portion 242 b on the surface S1 . The first conductive material 242 can be, for example, copper, and it can be formed by, for example, electroplating, but the invention is not limited thereto. Preferably, the first conductive material 242 is formed until the aspect ratio of the remaining holes V is less than 3. More preferably, the first conductive material 242 is formed until the remaining hole V has an aspect ratio of 2.5. In this way, when the aspect ratio of the remaining holes is less than 3, the photoresist subsequently filled into the holes V can be easily removed.

As shown in FIG. 7 , a patterned photoresist K2 is formed to cover the surface S1 but expose the hole V. As shown in FIG. In detail, a photoresist (not shown) can be formed to fully cover the surface S1 and fill at least part of the holes V. Then, photoresist is patterned to cover side S1 but expose holes V. FIG. Thereafter, an oxygen treatment process is selectively performed to further remove the photoresist remaining in the hole V after the patterned photoresist K2 is formed. Since the hole portion 242a of the first conductive material 242 has been filled into the hole V until the aspect ratio of the hole V is less than 3, the photoresist located in the hole V can be completely removed when patterning the photoresist. etchant.

As shown in FIG. 8 , a second conductive material 246 is formed on the exposed hole portion 242 a of the first conductive material 242 . The second conductive material 246 can be, for example, copper, and it can be formed by, for example, electroplating, but the invention is not limited thereto. Then, a conductive pad 250 is formed on the second conductive material 246 . The conductive pad 250 can be, for example, nickel, tin or gold, and it can be formed by pressing, but the invention is not limited thereto.

The patterned photoresist K2 is removed, and the surface portion 242b of the first conductive material 242 is exposed, as shown in FIG. 9 . Next, an etching process is performed to remove the surface portion 242b of the first conductive material 242, as shown in FIG. 10 . In this embodiment, the etching process is performed using the conductive pad 250 as a mask to remove the surface portion 242b. At this time, the barrier layer 220 and the portion of the seed layer 230 located on the surface S1 or directly below the surface portion 242b are removed together, thereby forming a barrier layer 220' and a seed layer 230'. The surface portion 242b, part of the barrier layer 220 and the seed layer 230 can be removed in the same manufacturing process or a plurality of manufacturing processes can be removed sequentially. In this way, the conductive plug C2 is formed in the hole V, wherein the conductive plug C2 may include a barrier layer 220 ′, a seed layer 230 ′, a first conductive material 242 and a second conductive material 246 . The conductive plug C2 may be made of copper, for example, but the invention is not limited thereto. In this way, the TSV 200 is formed in the hole V of the substrate 110 , and the TSV 200 may include a plurality of conductive plugs C2 and a conductive pad 250 .

Each conductive plug C2 has an upper half T1 and a lower half T2, wherein the upper half T1 protrudes from the surface S1, and the lower half T2 is located below the upper half T1. It is emphasized here that when the surface portion 242b of the first conductive material 242 is removed using the conductive pad 250 as a mask, a top T11 higher than the upper half T1 of the surface portion 242b of the first conductive material 242 will be etched, However, a bottom T12 of the upper half T1 that is as high as the surface portion 242b of the first conductive material 242 will not be etched because it is covered by the surface portion 242b. Therefore, the top T11 will be thinner than the bottom T12. When the conductive pad 250 is used as a mask for etching, the top T11 will be thinner than the conductive pad 250 . Preferably, the conductive pad 250 has the same diameter as the bottom T12, so (especially when the distances between the conductive plugs C2 are close) the conductive plugs C2 can be prevented from contacting each other and short-circuited, so as to be more easily controlled to pass through the TSV 200 Layout of the formed semiconductor elements. Furthermore, the bottom T12 has the same diameter as the lower half T2 to form a precise TSV 200 with excellent electrical conductivity.

The TSVs 200 have six conductive plugs C2 located in the six holes V respectively. However, the number of the conductive plugs C2 is not limited thereto, and may be less than or greater than six, for example. In other words, the TSV 200 may have only one conductive plug C2, for example, and the TSV structure 200 and its manufacturing process of the present invention can be applied to various TSV manufacturing processes, such as a post-drilling ( via last) production process, etc. Two TSV fabrication processes applicable to the TSV structure 200 of the present invention and the fabrication process thereof will be listed below, but the scope of application of the present invention is not limited thereto.

As shown in FIG. 11, in the post-drilling manufacturing process step after the metal interconnection, a MOS transistor M is first formed on the substrate 310 (as shown in the left figure), and an interlayer dielectric layer 320 and A multilayer interconnection structure 340; then, form a hole V1 in the multilayer interconnection structure 340, the interlayer dielectric layer 320 and the substrate 310 from a front surface S2 of the substrate 310, and form a through silicon TSV 200 (as shown in the figure on the right).

As shown in FIG. 12 , the post-drilling process steps after the metal oxide semiconductor and before the metal interconnection, that is, to complete the fabrication of a semiconductor structure to be formed on the substrate 410 such as a MOS transistor M (as shown in the left figure) shown); then form the required interlayer dielectric layer 420, a multi-layer interconnection structure 440, then thin the substrate 410, and form a hole V2 through the substrate 410 and from a back surface S3 of the substrate 410 interlayer dielectric layer 420 , and form a through-silicon via 200 to connect with metal such as a multi-layer interconnection structure 440 (as shown in the right figure).

To sum up, the present invention proposes a TSV and its manufacturing process. Before covering and patterning to form a patterned photoresist, the present invention first fills a hole in a substrate with a first conductive material middle. Therefore, the depth at which the photoresist is filled into the holes can be reduced so that the photoresist can be easily removed during patterning. Preferably, the aspect ratio of the remaining holes after forming the first conductive material is less than 3.

Moreover, after forming the patterned photoresist, fill a second conductive material on the first conductive material in the hole, form a conductive pad on the second conductive material, and then remove the patterned photoresist agent and remove the first conductive material outside the hole to form a conductive plug. Since the first conductive material located outside the hole is removed by, for example, etching, the conductive plug protrudes from an upper half of the base, and has a top portion that is thinner than a bottom portion. Preferably, the first conductive material is etched using the conductive pad as a mask, so the top is also thinner than the conductive pad. More preferably, the conductive pad and the bottom have the same diameter, so (especially when the adjacent conductive plugs are close to each other), it is possible to prevent these conductive plugs from contacting each other and short circuiting. What's more, the bottom has the same diameter as the bottom half of each conductive plug in the hole, so that a precise TSV with excellent conductivity can be formed.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (18)

1. A through-silicon via, comprising: a base having a hole in one side; a conductive plug disposed in the hole, and the conductive plug has an upper half protruding from the surface, wherein the upper half has a top and a bottom, and the top is thinner than the bottom; and A conductive pad is located on the conductive plug, and the conductive pad has the same diameter as the bottom. 2. The TSV of claim 1, wherein the conductive plug comprises copper. 3. The TSV of claim 1, wherein the conductive pad comprises nickel, tin or gold. 4. The TSV of claim 1, wherein the top portion is thinner than the conductive pad. 5. The TSV of claim 1, wherein the bottom has the same diameter as a lower half of the conductive plug in the hole. 6 . The TSV of claim 1 , wherein an aspect ratio of the hole is between 3.5-10. 7. The TSV of claim 1, wherein the critical dimension (CD) of the hole is smaller than 18 micrometers (micrometer, μm). 8. A TSV manufacturing process, comprising: providing a substrate having one side; a hole is formed from the face of the base; forming a first conductive material covering the hole and the surface; forming a patterned photoresist covering the surface and exposing the hole; forming a second conductive material on the exposed first conductive material; removing the patterned photoresist; and The first conductive material on the surface is removed to form a conductive plug in the hole. 9. The TSV manufacturing process as claimed in claim 8, wherein the conductive plug has an upper half protruding from the surface, the upper half has a top and a bottom, and the top is thinner than the bottom. 10 . The TSV manufacturing process as claimed in claim 8 , wherein an aspect ratio of the hole is between 3.5˜10. 11 . 11. The TSV manufacturing process as claimed in claim 8, wherein the critical dimension (CD) of the hole is smaller than 18 micrometers (micrometer, μm). 12. The TSV manufacturing process according to claim 8, before forming the first conductive material, further comprising: A barrier layer and a seed layer are sequentially formed to cover the hole and the surface. 13. The TSV manufacturing process as claimed in claim 8, wherein the first conductive material and the second conductive material are formed by electroplating. 14. The TSV manufacturing process as claimed in claim 10, wherein the first conductive material is formed until the aspect ratio of the remaining hole is less than 3. 15. The TSV manufacturing process as claimed in claim 14, wherein the first conductive material is formed until the remaining hole has an aspect ratio of 2.5. 16. The TSV manufacturing process as claimed in claim 8, before removing the first conductive material, further comprising: A conductive pad is formed on the second conductive material. 17. The TSV manufacturing process as claimed in claim 16, wherein the first conductive material is removed to use the conductive pad as a mask. 18. The TSV manufacturing process as claimed in claim 8, after forming the patterned photoresist, further comprising: Carry out an oxygen treatment manufacturing process.