CN104201880A - Low current mismatch charge pump circuit for resisting process fluctuation under low voltage of phase lock loop - Google Patents

Abstract

The invention discloses a low-current mismatch charge pump circuit used for resisting technological fluctuations under low voltage of a phase-locked loop. The charge pump circuit includes: a current mirror composed of PMOS devices P1, P2, P3, P4 and NMOS devices N1, N2, N3; a charging circuit composed of PMOS devices P5, P6 and transmission gate T1; a charging circuit composed of NMOS devices N4, N5 and the discharge circuit composed of transmission gate T2; the feedback circuit composed of PMOS devices P7, P8 and NMOS devices N6, N7; and the body bias circuit composed of PMOS device P9, NMOS device N8 and polysilicon resistors R1, R2. The gate of the charging and discharging current tube is controlled by the transmission gate to ensure the voltage output range of the charge pump under low power supply voltage. Feedback regulation is performed through MOS tubes with two different thresholds, high and low, to ensure a good match between charge and discharge currents. A body bias circuit is introduced to reduce the impact of process angle fluctuations on the performance of the charge pump.

Description

Low Current Mismatch Charge Pump Circuit for Resisting Process Fluctuation at Low Voltage of Phase Locked Loop

technical field

The invention relates to the field of integrated circuit design, in particular to a low-current-mismatch charge-pump circuit used in a phase-locked loop to resist process fluctuations at low voltage.

Background technique

As the most popular frequency synthesizer structure in modern wireless communication system applications, phase-locked loop (PLL) can complete signal modulation and demodulation, clock recovery, and generate local oscillator for mixer and carrier recovery of wireless receiver Signal. The charge pump phase-locked loop (CP-PLL) has become the most common phase-locked loop circuit because of its high speed and low noise. The charge pump (CP) circuit plays a very important role in the charge pump phase-locked loop. Its main function is to pass the UP and DN pulse digital signals from the phase frequency detector (PFD) through the low-pass filter (LPF) Converted to an analog voltage signal, the signal controls the oscillation frequency of the voltage-controlled oscillator (VCO). Therefore, the charge pump circuit has a very important influence on the characteristics of the entire phase-locked loop loop.

For the design of the charge pump circuit, the mismatch of charge and discharge current is one of the main design challenges. Various non-ideal effects of MOS tubes, non-zero load voltages of current sources and current mirrors, and different characteristic changes of charge and discharge MOS tubes under different process angles are all factors that can cause charge and discharge current mismatch. In order to eliminate the dead zone effect of the PFD, the PFD introduces a delay to remove the dead zone, which causes the charging branch and the discharging branch of the charge pump to be turned on at the same time. Therefore, when the charging and discharging currents are inconsistent, the output voltage of the charge pump will fluctuate, which will cause the jitter of the VCO output frequency, generate phase noise, and generate reference spurs in the output spectrum.

Another design problem of the charge pump phase-locked loop is that the frequency bandwidth of the output signal needs to reach a certain coverage, which requires the charge pump circuit to have sufficient output voltage swing to control the output frequency of the VCO. With the development of microelectronics technology to nanometer size, the design requirements of integrated circuits are increasingly moving closer to low voltage (within 1.0V) and low power consumption.

In order to improve the mismatch problem of charging and discharging current, the traditional charge pump circuit usually adopts a cascaded structure to increase the output resistance of the current source and the load terminal of the current mirror to improve the current matching. Under low voltage operation, the voltage drop generated by this structure will be This makes the charge pump unable to provide enough voltage headroom to meet the swing requirements of the signal.

Another common way to deal with current mismatch is to use a high-gain op amp to control the voltage difference between the output node of the charge pump and the nodes of the pull-up and pull-down circuits through negative feedback, thereby reducing the difference between the pull-up and pull-down currents. lost pair. However, the high-gain operational amplifier circuit itself has a certain design complexity, and when the operating voltage is very low, the operational amplifier nested in the charge pump circuit may not be able to guarantee normal operation itself, so further improving the overall design difficulty.

In a traditional charge pump circuit, a MOS tube is usually used as a switch tube to control the charge and discharge of the charge pump, which can be placed at the drain, source or gate of the current tube. When it is placed on the drain or source, it will seriously reduce the swing of the output voltage at low voltage, especially when the drain is off, because it is directly connected to the output, the charge injection and charge sharing effects will be very obvious. However, if it is placed at the gate terminal, the turn-on and turn-off time of charge pump charging and discharging will increase due to the gate capacitance of the current tube, and the output impedance of the charge pump is small, which is easily affected by the output voltage, resulting in current mismatch.

In addition, when considering the process deviation in the integrated circuit manufacturing process, the mismatch between the charging current and the discharging current of the traditional charge pump circuit will be amplified again.

To sum up, under low voltage operation, it is difficult for the traditional charge pump circuit to obtain a wide output voltage range and low mismatch charge and discharge current.

Contents of the invention

The invention provides a low-current-mismatch charge-pump circuit which is used in a charge-pump phase-locked loop and can resist technological fluctuations under low operating voltage.

A low-current-mismatch charge-pump circuit for resisting process fluctuations under low-voltage phase-locked loops, comprising: a current mirror, a charging circuit, a discharging circuit, a feedback circuit, and a body bias circuit;

Described current mirror comprises PMOS device P1, P2, P3, P4 and NMOS device N1, N2, N3; Wherein, the drain electrode of P1 connects current source and connects with its gate, links to each other with the gate of P2 again; The drain of P3 The pole is connected to its gate, and then connected to the gate of P4 and the drain of N1 respectively; the drain of N2 is connected to its gate, and then connected to the gate of N1, the gate of N3, and the drain of P2 respectively; P1, The sources of P2, P3, and P4 are all connected to the power supply voltage; the sources of N1, N2, and N3 are all connected to the ground;

The charging circuit includes: a PMOS device P5 used as a charging current tube, a PMOS device P6 used as a charging controlled transistor, and a transmission gate T1 used as a charging control switch; wherein, the drain of P5 is connected to its gate , and then respectively connected to the gate of P6 and the drain of N3 in the current mirror; the drain of P6 is connected to the output node of the charge pump; the sources of P5 and P6 are connected to the power supply voltage; one end of the transmission gate T1 is connected to the power supply The voltage is connected, and the other end is connected to the gate of P5 and P6. The gate of the PMOS device forming the transmission gate T1 is controlled by the charging signal UP, and the gate of the NMOS device in T1 is controlled by the complementary signal of the charging signal UP; the charging signal UP is controlled by The pulse signal generated by the frequency and phase detector;

The discharge circuit includes: an NMOS device N4 used as a discharge current tube, an NMOS device N5 used as a discharge controlled transistor, and a transfer gate T2 used as a discharge control switch; wherein, the drain of N4 is connected to its gate , and then respectively connected to the gate of N5 and the drain of P4 in the current mirror; the drain of N5 is connected to the output node of the charge pump; the sources of N4 and N5 are connected to the ground; one end of the transmission gate T2 is connected to the ground , the other end is connected to the gates of N4 and N5, the gate of the PMOS device constituting the transmission gate T2 is controlled by the discharge signal DN, the gate of the NMOS device in T2 is controlled by the complementary signal of the discharge signal DN; the discharge signal DN is controlled by the frequency discrimination The pulse signal generated by the phase detector;

The feedback circuit includes: a PMOS device P7 used for feedback regulation of the charging circuit, a high-threshold PMOS device P8, and an NMOS device N6 and a high-threshold NMOS device N7 used for feedback regulation of the discharge circuit; wherein, the gates of P7 and P8 The poles are all connected with the output node of the charge pump, the drains of P7 and P8 are connected with the gate of P6 in the charging circuit, the sources of P7 and P8 are all connected with the power supply voltage; the gates of N6 and N7 are connected with the charge The output nodes of the pump are connected, the drains of N6 and N7 are connected with the grid of N5 in the discharge circuit, and the sources of N6 and N7 are connected with the ground;

The body bias circuit includes: PMOS device P9, NMOS device N8, and resistors R1, R2; wherein, the gate of P9 is connected to the ground, the source is connected to the power supply, the drain is connected to one end of R1, and the R1 The other end is connected to the ground; the net connecting the drain of P9 to one end of R1 is named PBB, and connected to the body ends of P5, P6, P7, and P8 respectively; the gate of N8 is connected to the power supply, and the source The pole is connected to the ground, the drain is connected to one end of R2, and the other end of R2 is connected to the power supply; the network (net) connecting the drain of N8 to one end of R2 is named NBB, and is connected to N4, N5, N6, The body ends of N7 are connected.

Described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and NMOS device N1, N2, N3, N4, N5, N6, N7, N8 all have source, drain, gate The four-port structure of poles and body ends; among them, the body ends of P1, P2, P3, P4, and P9 are all connected to the power supply voltage; the body ends of N1, N2, N3, and N8 are all grounded; the body ends of P5, P6, P7, and P8 Connect to PBB in the body bias circuit; N4, N5, N6, and N7 body terminals are connected to NBB in the body bias circuit.

The PMOS device P8 and the NMOS device N7 are high-threshold transistors formed through a threshold adjustment process; the other PMOS devices and NMOS devices all use transistors with a common threshold, or when the operating voltage is very low, they all use threshold-adjusted transistors. process formed low threshold tubes.

The PMOS devices P1, P2, P3, P4, P5, P6, P7, P8, P9 and the NMOS devices N1, N2, N3, N4, N5, N6, N7, N8 are metal oxide semiconductor MOS transistors.

The resistors R1 and R2 are two-port polysilicon resistors.

Compared with the prior art, the present invention has the following beneficial technical effects:

The control signal for charging and discharging the charge pump controls the gate of the current tube to provide enough voltage clearance, so that the charge pump circuit can obtain a rail-to-rail voltage output range at low voltage, so as to better meet The output frequency bandwidth requirement of the phase-locked loop. Using a transmission gate instead of a single MOS transistor as a control switch can effectively reduce the influence of the gate capacitance of the charging and discharging current tube on the turn-on and turn-off time, and avoid current mismatch caused by an excessively long turn-on and turn-off time. Two types of transistors with low threshold and high threshold are respectively used for feedback adjustment of the charging circuit and discharging circuit, and the magnitude of the charging and discharging current within the entire charge pump output voltage range is accurately controlled to achieve good matching. At the same time, a body bias circuit is introduced to reduce the impact of process fluctuations on the matching of the charge pump charge and discharge current by controlling the body terminal voltage of the charge and discharge current tube and the feedback tube, and also reduce the impact of process deviation on the charge and discharge current value itself. Influence.

The charge pump circuit of the present invention can realize good matching of charging current and discharging current under the low working voltage of 0.8V, and the output voltage of the charge pump is in the range of 20mV-780mV. At the same time, by reasonably adjusting the parameters of each circuit device, its working principle will not be affected at a lower operating voltage (even down to 0.5V), and it can also ensure charging and discharging while basically realizing rail-to-rail output voltage Good matching of current.

Description of drawings

Figure 1 is a schematic diagram of the circuit structure of a basic charge pump circuit.

FIG. 2 is a schematic diagram of the circuit structure of the charge pump circuit in the present invention.

Fig. 3 is a schematic diagram of Specter simulation results of the charge pump circuit in the present invention.

the

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but the examples are not intended to limit the present invention.

The circuit structure of the basic charge pump circuit shown in Figure 1 controls the on-off of the charge and discharge current through the switch, so as to realize the charge and discharge of the load (loop filter) of the charge pump, and the voltage on the load capacitor is the voltage of the charge pump. The output voltage is used as the frequency control signal of the voltage controlled oscillator. According to this basic charge pump circuit, it can be designed in different ways. The switch tube can be placed on the source, drain or gate of the current tube, and other auxiliary circuits can be added. The charge pump circuit obtained in different ways There will also be differences in performance.

As shown in FIG. 2 , the low current mismatch charge pump circuit used in the present invention for resisting process fluctuations under low voltage of the PLL includes multiple transistors and two resistors. The transistors are MOS transistors, including n-channel MOS transistors (NMOS) and p-channel MOS transistors (PMOS); the resistors are polysilicon resistors.

A low-current mismatch charge pump circuit for resisting process fluctuations at low voltage of a phase-locked loop, including: a current mirror, a charging circuit, a discharging circuit, a feedback circuit and a body bias circuit, wherein,

Described current mirror is made up of PMOS device P1, P2, P3, P4 and NMOS device N1, N2, N3; Wherein, the drain electrode of P1 connects current source and is connected with its gate, is connected with the gate of P2 again; The drain is connected to its gate, and then connected to the gate of P4 and the drain of N1; the drain of N2 is connected to its gate, and then connected to the gate of N1, the gate of N3, and the drain of P2; P1, P2 The sources of , P3, and P4 are all connected to the power supply voltage; the sources of N1, N2, and N3 are all connected to the ground.

The charging circuit is used to provide a charging current to charge the output load of the charge pump (that is, the capacitor of the loop filter) to increase the output voltage of the charge pump, including: a PMOS device P5 used as a charging current tube, used as A PMOS device P6 that is a charge controlled transistor, and a transmission gate T1 that acts as a charge control switch.

Wherein, the drain of P5 is connected to its gate, and then connected to the gate of P6 and the drain of N3 in the current mirror; the drain of P6 is connected to the output node of the charge pump; the sources of P5 and P6 are connected to the power supply The voltage is connected; one end of the transmission gate T1 is connected to the power supply voltage, and the other end is connected to the gates of P5 and P6. The gate of the PMOS device forming the transmission gate T1 is controlled by the charging signal UP, and the gate of the NMOS device in T1 is controlled by the complementary charging signal. The signal UP is controlled; the charging signal UP is a pulse signal generated by a frequency and phase detector.

It can be seen that the charging controlled transistor P6 realizes the charging of the output node of the charge pump, and pulls the output voltage up to the power supply voltage. At the same time, by turning on and off the control switch T1, it is possible to control whether P6 is charged. When T1 is turned off, P6 charges the output node of the charge pump; when T1 is turned on, the gate terminals of P5 and P6 are pulled up to the power supply voltage, and the charging stops.

The discharge circuit is used to discharge the output load of the charge pump (that is, the capacitance of the loop filter) to reduce the output voltage of the charge pump, including: NMOS device N4 used as a discharge current tube, used as a discharge An NMOS device N5 of the controlled transistor, and a transmission gate T2 used as a discharge control switch.

Wherein, the drain of N4 is connected to its gate, and then connected to the gate of N5 and the drain of P4 in the current mirror; the drain of N5 is connected to the output node of the charge pump; the sources of N4 and N5 are connected to the ground One end of the transmission gate T2 is connected to the ground, and the other end is connected to the gates of N4 and N5. The gate of the PMOS device forming the transmission gate T2 is controlled by the discharge signal DN, and the gate of the NMOS device in T2 is controlled by the complementary signal DN of the discharge signal. Control; the discharge signal DN is a pulse signal generated by the frequency and phase detector.

It can be seen that the discharge controlled transistor N5 realizes the discharge of the output node of the charge pump, and pulls down the output voltage to the lowest ground voltage, and at the same time, by turning on and off the control switch T2, it can control whether N5 is discharged. When T2 is turned off, N5 discharges the output node of the charge pump; when T2 is turned on, the gate terminals of N4 and N5 are pulled down to the ground voltage, and the discharge stops.

The feedback circuit is used to detect the voltage at the output terminal of the charge pump, and control the gate voltage of the charge and discharge current tube in the charge and discharge circuit through feedback, thereby suppressing the charge and discharge current caused by the change of the voltage at the output terminal of the charge pump. lost pair. It includes: a PMOS device P7 and a high-threshold PMOS device P8 used for feedback regulation of the charging circuit, and an NMOS device N6 and a high-threshold NMOS device N7 used for feedback regulation of the discharging circuit.

Wherein, the gates of P7 and P8 are connected with the output node of the charge pump, the drains of P7 and P8 are connected with the gate of P6 in the charging circuit, and the sources of P7 and P8 are connected with the power supply voltage; N6, P8 The gate of N7 is connected to the output node of the charge pump, the drains of N6 and N7 are connected to the gate of N5 in the discharge circuit, and the sources of N6 and N7 are connected to the ground. P8 and N7 are high-threshold transistors formed by threshold adjustment, respectively cooperate with P7 and N6 to adjust the charge and discharge circuit more accurately, so that the charge and discharge currents can be kept matched within the output voltage range of the charge pump.

The body bias circuit is used to control the body terminal voltages of P5, P6, N4, N5 in the charging and discharging circuit and P7, P8, N6, N7 in the feedback circuit, thereby reducing the impact of process angle fluctuation on charging and discharging. The effect of current matching degree. Including: PMOS device P9, NMOS device N8, and polysilicon resistors R1, R2.

Among them, the gate of P9 is connected to the ground, the source is connected to the power supply, the drain is connected to one end of R1, and the other end of R1 is connected to the ground; the net connected to the drain of P9 and one end of R1 is named as PBB, and respectively connected to the bulk terminals of P5, P6, P7, and P8; the gate of N8 is connected to the power supply, the source is connected to the ground, the drain is connected to one end of R2, and the other end of R2 is connected to the power supply; the N8 The net (net) whose drain is connected to one end of R2 is named NBB, and is respectively connected to the body ends of N4, N5, N6, and N7. The body bias circuit adjusts the threshold value of the transistor by controlling the body terminal voltage of the transistor, thereby reducing the influence of process corner fluctuations.

The operating principle of the charge pump circuit in the present invention is as follows:

When the charge signal UP is high and the discharge signal DN is low, the transmission gate T1 is turned off, T2 is turned on, P6 is turned on normally, and charging is carried out. The gate of N5 is pulled to the ground and is in an off state, and the discharge path is cut off. At this time The voltage of the output node rises; when the charging signal UP is low and the discharging signal DN is high, the transmission gate T1 is turned on, T2 is turned off, the gate of P6 is pulled to the power supply voltage and is in the off state, the charging path is cut off, and N5 conducts normally. When the charging signal UP is low and the discharging signal DN is low, the transmission gate T1 is turned on, T2 is turned on, and the gate of P6 is pulled to the power supply voltage to be in the off state, charging The path is cut off, the gate of N5 is pulled to the ground and is in the off state, the discharge path is cut off, and the output node voltage remains unchanged at this time; when the charging signal UP is high and the discharge signal DN is high, the transmission gate T1 is turned off, and T2 is turned off Off, P6 is normally turned on for charging, and N5 is normally turned on for discharging. At this time, the charging current and discharging current need to have a good matching degree, so as to ensure that the output node voltage remains unchanged.

When the output of the charge pump is gradually approaching the power supply voltage, N6 and N7 are gradually turned on, and the gate voltage of N5 is gradually pulled down to a low level, so that the discharge current Idn is reduced to match the smaller charging current at this time; When the output of the charge pump gradually approaches zero level, P7 and P8 are gradually turned on, and the gate voltage of P6 is gradually pulled up to a high level, so that the charging current Iup is reduced to match the smaller discharge current at this time. The current mirror adopts a two-stage structure, thereby effectively isolating the feedback voltage of the feedback circuit and preventing it from directly affecting the output current of the current source.

In the body bias circuit, PBB at the junction of P9 and R1 is connected to the body terminals of P5, P6, P7, and P8 respectively, and NBB at the junction of N8 and R2 is connected to the body terminals of N4, N5, N6, and N7 respectively. When the process angle is tt (typical-typical), by setting the parameters of the device in the body bias circuit reasonably, the voltage values at PBB and NBB are adjusted to ensure that the charge and discharge currents are well matched. When the process angle is ss (slow-slow), the absolute value of the threshold voltage of the MOS transistor increases compared with the tt process angle, and the transconductance and source-leakage current decrease, and at this time the source-leakage current of P9 and N8 also decreases , the body bias voltage PBB is reduced and NBB is increased through the resistors R1 and R2 respectively, and the forward body bias is implemented on all target transistors whose body terminals are connected to the body bias voltage, reducing the absolute value of the threshold voltage of the tube and increasing source-drain current of the target transistor, enabling negative feedback modulation. When the process angle is ff (fast-fast), the body bias voltages PBB and NBB respectively implement reverse body bias on the target transistor, increase the absolute value of the threshold voltage of the tube, and reduce the source-drain current of the target transistor. Negative feedback modulation is also realized. Therefore, it can be ensured that the charging and discharging currents of the charge pump can be matched as much as possible under different process angles.

The size of the above-mentioned MOS transistors is determined by Specter simulation, so that the charging current and discharging current of the charge pump can be well matched under typical process angles. All PMOS tubes and NMOS tubes used in the present invention can adopt common four-port structure, including: source (S), drain (D), gate (G), body terminal (B). Among them, P8 and N7 are high-threshold transistors with threshold adjustment, and other transistors use ordinary threshold or low-threshold transistors; The NBB in the termination body bias circuit, all other PMOS body terminations are connected to the power supply, and the NMOS body terminations are grounded.

Fig. 3 shows the Specter simulation result of the charge pump circuit of the present invention, wherein the abscissa represents the output voltage Vout, and the ordinate represents the size of charging and discharging current (I), and the solid line represents the size of the charging current (Iup), and the dotted line adds The small squares represent the magnitude of the discharge current (Idn). The three sets of simulation results respectively represent the charge and discharge currents under the three process corners of SS, TT, and FF. When the working voltage is 0.8V, within the output voltage range of 20mV~780mV, the charging current and discharging current have a good matching degree under the typical process angle. Even if the process angle is biased to SS or FF, the charge and discharge currents still maintain a good match. Under the typical process angle, the maximum charge and discharge current is 125uA.

Claims (5)

1. A low-current mismatch charge pump circuit for resisting process fluctuations under the low voltage of a phase-locked loop, comprising: a current mirror, a charging circuit, a discharging circuit, a feedback circuit and a body bias circuit, characterized in that: Described current mirror comprises PMOS device P1, P2, P3, P4 and NMOS device N1, N2, N3; Wherein, the drain electrode of P1 connects current source and connects with its gate, links to each other with the gate of P2 again; The drain of P3 The pole is connected to its gate, and then connected to the gate of P4 and the drain of N1 respectively; the drain of N2 is connected to its gate, and then connected to the gate of N1, the gate of N3, and the drain of P2 respectively; P1, The sources of P2, P3, and P4 are all connected to the power supply voltage; the sources of N1, N2, and N3 are all connected to the ground; The charging circuit includes: a PMOS device P5 used as a charging current tube, a PMOS device P6 used as a charging controlled transistor, and a transmission gate T1 used as a charging control switch; wherein, the drain of P5 is connected to its gate , and then respectively connected to the gate of P6 and the drain of N3 in the current mirror; the drain of P6 is connected to the output node of the charge pump; the sources of P5 and P6 are connected to the power supply voltage; one end of the transmission gate T1 is connected to the power supply The voltage is connected, and the other end is connected to the gate of P5 and P6. The gate of the PMOS device forming the transmission gate T1 is controlled by the charging signal UP, and the gate of the NMOS device in T1 is controlled by the complementary signal of the charging signal UP; the charging signal UP is controlled by The pulse signal generated by the frequency and phase detector; The discharge circuit includes: an NMOS device N4 used as a discharge current tube, an NMOS device N5 used as a discharge controlled transistor, and a transfer gate T2 used as a discharge control switch; wherein, the drain of N4 is connected to its gate , and then respectively connected to the gate of N5 and the drain of P4 in the current mirror; the drain of N5 is connected to the output node of the charge pump; the sources of N4 and N5 are connected to the ground; one end of the transmission gate T2 is connected to the ground , the other end is connected to the gates of N4 and N5, the gate of the PMOS device constituting the transmission gate T2 is controlled by the discharge signal DN, the gate of the NMOS device in T2 is controlled by the complementary signal of the discharge signal DN; the discharge signal DN is controlled by the frequency discrimination The pulse signal generated by the phase detector; The feedback circuit includes: a PMOS device P7 used for feedback regulation of the charging circuit, a high-threshold PMOS device P8, and an NMOS device N6 and a high-threshold NMOS device N7 used for feedback regulation of the discharge circuit; wherein, the gates of P7 and P8 The poles are all connected with the output node of the charge pump, the drains of P7 and P8 are connected with the gate of P6 in the charging circuit, the sources of P7 and P8 are all connected with the power supply voltage; the gates of N6 and N7 are connected with the charge The output nodes of the pump are connected, the drains of N6 and N7 are connected with the grid of N5 in the discharge circuit, and the sources of N6 and N7 are connected with the ground; The body bias circuit includes: PMOS device P9, NMOS device N8, and resistors R1, R2; wherein, the gate of P9 is connected to the ground, the source is connected to the power supply, the drain is connected to one end of R1, and the R1 The other end is connected to the ground; the net connecting the drain of P9 to one end of R1 is named PBB, and connected to the body ends of P5, P6, P7, and P8 respectively; the gate of N8 is connected to the power supply, and the source The pole is connected to the ground, the drain is connected to one end of R2, and the other end of R2 is connected to the power supply; the network (net) connecting the drain of N8 to one end of R2 is named NBB, and is connected to N4, N5, N6, The body ends of N7 are connected. 2. The charge pump circuit according to claim 1, characterized in that: said PMOS devices P1, P2, P3, P4, P5, P6, P7, P8, P9 and NMOS devices N1, N2, N3, N4, N5, N6, N7, and N8 are all four-port structures with source, drain, gate, and body terminals; among them, the body terminals of P1, P2, P3, P4, and P9 are all connected to the power supply voltage; N1, N2, N3, The body terminals of N8 are all grounded; the body terminals of P5, P6, P7, and P8 are connected to the PBB in the body bias circuit described above; the body terminals of N4, N5, N6, and N7 are connected to the NBB in the body bias circuit described above . 3. The charge pump circuit as claimed in claim 1, characterized in that: said PMOS device P8 and NMOS device N7 are high threshold transistors formed through a threshold adjustment process; other said PMOS devices and NMOS devices are all made of common Threshold transistors, or when the operating voltage is very low, use low-threshold transistors formed through a threshold adjustment process. 4. charge pump circuit as claimed in claim 1 is characterized in that: described PMOS device P1, P2, P3, P4, P5, P6, P7, P8, P9 and NMOS device N1, N2, N3, N4, N5, N6, N7, and N8 are metal oxide semiconductor MOS transistors. 5. The charge pump circuit according to claim 1, wherein the resistors R1 and R2 are two-port polysilicon resistors.