CN104202552B - The method and apparatus that both of which MIPI signals are realized by bridging chip - Google Patents
The method and apparatus that both of which MIPI signals are realized by bridging chip Download PDFInfo
- Publication number
- CN104202552B CN104202552B CN201410414927.XA CN201410414927A CN104202552B CN 104202552 B CN104202552 B CN 104202552B CN 201410414927 A CN201410414927 A CN 201410414927A CN 104202552 B CN104202552 B CN 104202552B
- Authority
- CN
- China
- Prior art keywords
- signal
- module
- rgb
- command
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 47
- 238000012545 processing Methods 0.000 claims abstract description 37
- 241001269238 Data Species 0.000 claims abstract description 36
- 239000000872 buffer Substances 0.000 claims description 57
- 238000001514 detection method Methods 0.000 claims description 31
- 238000006243 chemical reaction Methods 0.000 claims description 29
- 238000003860 storage Methods 0.000 claims description 18
- 230000007246 mechanism Effects 0.000 claims description 12
- 230000008859 change Effects 0.000 claims description 9
- 238000012360 testing method Methods 0.000 claims description 7
- 238000005070 sampling Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000007689 inspection Methods 0.000 claims 1
- 230000006870 function Effects 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 3
- 230000007480 spreading Effects 0.000 description 3
- 108010076504 Protein Sorting Signals Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 241000238876 Acari Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Landscapes
- Controls And Circuits For Display Device (AREA)
Abstract
The invention discloses a kind of method and apparatus that both of which MIPI signals are realized by bridging chip, its device turns RGB block, mode switch, VIDEO mode datas processing module, COMMAND mode datas processing module and interface switching switch including LVDS.The device is used to set the rgb video signal that LVDS vision signals are converted into data bus interface of the bridging chip under VIDEO patterns or COMMAND patterns according to user, is shown for the liquid crystal module with MIPI interfaces.The present invention is realized based on bridging chip, the simultaneously compatible VIDEO patterns and COMMAND patterns of bridging chip, both of which can be switched in real time by the configuration order of upper layer module, suitable pattern be selected according to system real-time status, so as to effectively reduce the expense of power consumption and resource.
Description
Technical field
It is real by bridging chip in particular to one kind the invention belongs to the display field of liquid crystal module and technical field of measurement and test
The method and apparatus of existing both of which MIPI signals.
Background technology
MIPI (mobile Industry Processor Interface) is Mobile Industry Processor Interface abbreviation,
The open standard formulated for Mobile solution processor initiated by the MIPI alliances including the companies such as ARM, Samsung, Intel.
When the signal of input is converted into MIPI by bridging chip under VIDEO patterns or COMMAND patterns by internal transformation mechanism
Sequence interface signal.VIDEO patterns refer to that main frame is transferred to liquid crystal module using real-time pixel stream, and are with high-speed signal transmission
Pattern, and COMMAND patterns refer to using sending order and data arrive the controller with display caching transmits signal
Pattern.VIDEO patterns are operated mainly for the liquid crystal module for not having frame buffer (buffer area) in driving chip, according to
The refreshing frequency sequential of liquid crystal module sends pixel data；COMMAND patterns (are cached mainly for frame buffer is contained in driving
Area) CPU screens operated, master control only need change display image when send pixel data, other when drive core
Piece oneself takes out data display from internal buffer (buffer area) is inner.
When main frame needs to be periodically flushed display, and without using special data signal transmission synchronizing information, control letter
Number and RGB data be in the form of message by MIPI bus transfers, be now accomplished by using VIDEO patterns transmission MIPI letter
Number；When display content does not change (or during local change), the central processing unit of display system should just be switched to low-power consumption mode,
And the link between processor and display can be activated when needing, this when COMMAND patterns be just well suited for it is this
Situation.When the display content of MIPI liquid crystal modules does not change (or during local change), the central processing unit of display system just should
Be switched to low-power consumption mode, and the link between processor and display is only activated when needing, this when COMMAND
Pattern is just well suited for such case.At present, LVDS vision signals being converted into MIPI signals by bridging chip can only realize
VIDEO patterns, it is impossible to while realizing COMMAND patterns.
The content of the invention
The two of bridging chip can not be realized for LVDS vision signals are converted into MIPI signals by bridging chip at present
The problem of kind of mode interface signal, the present invention propose it is a kind of by bridging chip realize both of which MIPI signals method and
Device, its is simple to operate, low in energy consumption, and reliability is high.
To achieve the above object, a kind of side that both of which MIPI signals are realized by bridging chip designed by the present invention
Method, it is characterized in that, comprises the following steps：
1) LVDS signals are converted into rgb video signal；
2) according to selection VIDEO patterns or COMMAND patterns is set, if 3) selection VIDEO patterns go to step, if selection
4) COMMAND patterns go to step；
3) rgb video signal of reception is converted into rgb interface signal by the rgb video signal according to VIDEO patterns；
4) rgb video signal is converted into data/address bus by the rgb video signal of reception according to COMMAND patterns to connect
Mouth (Data Bus Interface) signal；
5) sent according to setting selection rgb interface signal or data bus interface signal to bridging chip, the bridge joint
Rgb interface signal or data bus interface signal are converted into send to liquid crystal module after MIPI signals and shown by chip.
Preferably, the step 1) before also include configuration bridging chip and the step of liquid crystal module to VIDEO patterns.
Preferably, the step 1) before also include configuration bridging chip and the step of liquid crystal module to COMMAND patterns.
Preferably, the step 3) specific steps include：
3.1) by the front two row data buffer storage in rgb video signal；
3.2) local pixel clock is produced；
3.3) local timing signals are produced；
3.4) with the local pixel clock as the local timing signal sampling of the system clock to input, simultaneously
DE in the local timing signals reads the data formation synchronizing signal of the caching when effective；
3.5) synchronizing signal is converted into rgb interface signal.
Preferably, the step 4) specific steps include：
4.1) the first frame image data in rgb video signal is cached；
4.2) view data of the caching is converted into data bus interface signal and transmitted to bridging chip, the bridge
Connect chip and data bus interface signal is converted into MIPI signals transmitted to liquid crystal module and show；
4.3) judge whether next frame image data in the rgb video signal is identical with former frame, when next frame figure
As data and former frame are not simultaneously emitted by cutting figure instruction；
4.4) according to the next two field picture for cutting figure instruction buffer rgb video signal；
4.5) repeat step 4.2) to step 4.4).
Preferably, the step 4.1) in by the rgb video signal the first frame image data cache when frame is set
Section start testing mechanism, detects start recording data after frame head, stop recording data when detecting next frame frame head.Frame is originated
Place's testing mechanism ensures that the data that write every time are the complete view data of a frame from frame head to postamble.
A kind of device that both of which MIPI signals are realized by bridging chip for realizing the above method, its special character exists
In, including LVDS turn RGB block, mode switch, VIDEO mode datas processing module, COMMAND mode datas processing module and
Interface switching switch；The LVDS, which turns RGB block, to be used to LVDS vision signals being parsed into rgb video signal；The pattern is opened
Close for setting selection VIDEO patterns or COMMAND patterns according to upper strata, and rgb video signal is transmitted to VIDEO patterns
Data processing module or COMMAND mode data processing modules；The VIDEO mode datas processing module be used for according to
The rgb video signal of reception is converted into after rgb interface signal to send to interface to switch and switched by VIDEO patterns；The COMMAND
Mode data processing module is used to the rgb video signal of reception is converted into data bus interface (Data according to COMMAND patterns
Bus Interface) send after signal to interface to switch and switch；The interface switching switch, which is used to be set according to upper strata, to be selected
VIDEO patterns or COMMAND patterns, and the rgb interface signal or data bus interface signal of reception are sent to bridge joint
The rgb interface signal or data bus interface signal of reception are converted into after MIPI signals and sent by chip, the bridging chip
Shown to liquid crystal module.
Further, the VIDEO mode datas processing module includes local clock module, local timing modules, sheet
Ground image cache module picture signal synchronization module and output interface module；The local clock module is used for according to local image
The control instruction that control interface is provided produces local pixel clock and is sent to picture signal synchronization module；The local timing moulds
Block is used to produce local timing signals (VS, HS, DE) and be sent to picture signal synchronization module；The local image buffer storage mould
Block is used to cache two pixel columns to rgb video signal；When described image signal synchronization module is used for the local pixel with input
Clock as system clock to inputting local timing signal samplings, while the DE in the local timing signals is read when effective
The data of local image buffer storage module are taken, then export to form synchronizing signal to output interface module with local pixel clock；It is described
Synchronizing signal is converted into rgb interface signal and exports to interface to switch and switched by output interface module.
Further, the COMMAND mode datas processing module includes COMMAND mode datas buffer, image
Detection module, cut figure command module, COMMAND control modules and data conversion module；The COMMAND mode datas buffer
For receiving rgb video signal and storing a frame image data；Described image detection module is used to receive in rgb video signal
Whether view data and detection image change, and are sent when image changes and cut figure instruction；It is described to cut figure order mould
Block, which is used to detect, cuts unlatching COMMAND control modules after figure instruction；The COMMAND control modules are used to read COMMAND
The view data of rgb signal and sent in mode data buffer to data conversion module；The data conversion module is used for will
Rgb video signal is converted into after data bus interface signal to send to interface to switch and switched.
Further, in addition to MIPI configuration module units, bridged for being configured according to the order of upper strata instruction interface
Chip, and liquid crystal module is configured by the bridging chip.
The present invention realizes that bridging chip can regard the MIPI that is demodulated to of RGB screens signal integrity not by mistake based on bridging chip
Frequency signal；FPGA and bridging chip, which are applied in combination, can make device performance more reliable, integrated more efficient and operate also easy.
The beneficial effects of the present invention are：
1) VESA/JEIDA LVDS vision signals can be converted into rgb signal by the present invention, then be turned by bridging chip
Change MIPI signals into；
2) present invention is except most starting to do bridging chip and liquid crystal module some initialization by MIPI configuration modules
Configuration is outer, and other functions are, by FPGA complete independentlies, to reduce interacting between FPGA and high-level interface, make to realize framework
It is simpler, it is apparent；
3) present invention can be adapted to without liquid crystal module by adjusting the parameters of COMMAND mode data buffer memory units
The demand of resolution ratio, the MIPI videos letter required by display mode therewith can be changed out to different types of MIPI liquid crystal modules
Number.COMMAND pattern data stores unit only stores a frame data every time, and also only heavy when image changes every time
The new frame data of new storage, other times will not do any operation, so as to reduce the heating power consumption of device；
4) the not only simultaneously compatible VIDEO patterns and COMMAND patterns of bridging chip of the present invention, and can be by upper
The configuration order of layer module switches both of which in real time, suitable pattern is selected according to system real-time status, so that effectively
Reduce the expense of power consumption and resource；
5) present invention realizes the MIPI signals of COMMAND patterns, improves the aobvious figure speed of liquid crystal module, and pass through figure
As whether the automatic detection image of detection module changes, and replacement mechanism control module gives bridging chip configuration order, from
And improve and cut figure speed, making the operability of system strengthens；
6) present invention not only can control the aobvious figure speed of liquid crystal module under COMMAND patterns, and can control liquid
The number of brilliant screen image vegetarian refreshments, so as to contribute to positioning and its detection of the module manufacturer to liquid crystal display progress extraordinary image vegetarian refreshments.
Brief description of the drawings
Fig. 1 realizes the structural representation of the device of COMMAND pattern MIPI signals for the present invention by bridging chip.
Fig. 2 is the structural representation of VIDEO mode data processing modules in Fig. 1.
Fig. 3 is the structural representation of COMMAND mode data processing modules in Fig. 1.
Fig. 4 is the interface sequence figure of VIDEO mode datas processing module and bridging chip in Fig. 1.
Fig. 5 is the interface sequence figure of COMMAND mode datas processing module and bridging chip in Fig. 1.
In figure：1.LVDS turns RGB block, 2. mode switch, 3.VIDEO mode data processing modules, 3-1. local clocks
Module, the local timing modules of 3-2., the local image buffer storage modules of 3-3., 3-4. picture signal synchronization modules, 3-5. outputs connect
Mouth mold block, 4.COMMAND mode data processing modules, 4-1.COMMAND mode data buffers, 4-2. image detection modules,
4-3. cuts figure command module, 4-4.COMMAND control modules, 4-5. data conversion modules, 5. interfaces switching switch, 6. bridge joint cores
Piece, 7. liquid crystal modules, 8.MIPI configuration module units.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figure 1 to Figure 3, a kind of device that both of which MIPI signals are realized by bridging chip of the present invention, including
LVDS turns RGB block 1, mode switch 2, VIDEO mode datas processing module 3, COMMAND mode datas processing module 4, interface
Switching switch 5 and MIPI configuration modules unit 8.
LVDS, which turns RGB block 1, to be used to LVDS vision signals being parsed into rgb video signal, is parsed including demodulation clock,
Pixel clock, row data enable signal, and frame data enable signal, and its order enables signal with data, will letter after the completion of conversion
Number feeding mode switch 2.
Mode switch 2 is used to set selection VIDEO patterns or COMMAND patterns according to upper strata, and by rgb video signal
Transmit to VIDEO mode datas processing module 3 or COMMAND mode datas processing module 4.
VIDEO mode datas processing module 3 is sent to transmission after being used for the rgb video signal synchronization caching processing by reception
To interface switching switch 5.
VIDEO mode datas processing module 3 includes local clock module 3-1, local timing modules 3-2, local image
Cache module 3-3, picture signal synchronization module 3-4 and output interface module 3-5.
The control instruction that local clock module 3-1 is used to be provided according to local image control interface produces local pixel clock
It is sent to picture signal synchronization module 3-4.
Local timing modules 3-2 is sent to the synchronous mould of picture signal for producing local timing signals (VS, HS, DE)
Block 3-4.Local timing signals include video vertical field sync signal (VS), video level line synchronising signal (HS), video counts
According to useful signal (DE).
Local image buffer storage module 3-3 is used to cache two pixel columns to rgb video signal.
Picture signal synchronization module 3-4 is used for local to inputting as system clock with the local pixel clock of input
Timing signal samplings, while local image buffer storage module 3-3 data are read when local DE is effective, then during with local pixel
Clock is exported to output interface module 3-5.
Sampling in the middle of signals of the output interface module 3-5 by local pixel clock phase shift to snap to local view data
Window region, then local rgb interface signal output to interface switching is switched 5.
COMMAND mode datas processing module 4 is used to be converted into the rgb video signal of reception according to COMMAND patterns
Sent after data bus interface signal to interface switching switch 5.COMMAND mode datas processing module 4 includes COMMAND patterns
Data buffer 4-1, image detection module 4-2, cut figure command module 4-3-3, COMMAND control module 4-4 and data conversion
Module 4-5.
COMMAND mode data buffers 4-1 is used to receive rgb video signal and stores a frame image data.COMMAND
Mode data buffer 4-1 can store a frame data to the rgb video signal received, the capacity of a width picture be included, when one
After frame data storage is finished, COMMAND mode data buffers 4-1 will stop the write-in of entry data, only image detection
Module, which is sent, cuts after figure instruction, and now COMMAND mode datas buffer 4-1 can just start to re-write a new frame signal,
It should be noted that, LVDE, which turns RGB block 1, can send the image to COMMAND mode data buffers 4-1, COMMAND always
A frame section start testing mechanism is had inside mode data buffer 4-1, it is ensured that be written to COMMAND mode datas every time and delay
It is the complete image of a width from frame head to postamble that data inside storage 4-1, which are,.
Whether the view data and detection image that image detection module 4-2 is used to receive in rgb video signal change,
And sent when image changes cut figure instruction.Image detection module 4-2 can be detected to each frame signal in real time, be schemed
The partial pixel point in a frame signal can be first stored as detection module 4-2, then real time contrast is with a frame signal below, works as picture
When vegetarian refreshments information is inconsistent, image detection module 4-2, which can send one and cut figure, to be instructed to cutting figure command module 4-3, COMMAND mould
Formula data buffer 4-1 and COMMAND control module 4-4, informs that these module map pictures are changed, can carry out related behaviour
Make.Image detection module 4-2 can will cut the time that figure instruction keeps a frame, after treating a frame time, module can restart into
Row image detection.
Cut figure command module 4-3 and cut unlatching COMMAND control modules 4-4 after figure instruction for detecting.Cut figure order mould
Block 4-3 is after detecting and cutting figure instruction, substitution MIPI configuration modules unit 8, and send configuration is instructed to bridging chip 6, as cutting
Figure instruction input, this reduces interacting between upper layer module, simplifies controlling mechanism, and based on FPGA realizations
Device has the function that handles in real time, can also so make to cut figure speed faster more excellent.
COMMAND control modules 4-4 is used for the view data for reading rgb signal in COMMAND mode data buffers 4-1
And send to data conversion module 4-5.COMMAND control modules 4-4 is controlled by image detection module 4-2, cuts figure detection module 4
With COMMAND control interfaces.Associating between COMMAND control modules 4-4 and COMMAND control interfaces is as follows：When MIPI matches somebody with somebody
Modular unit 8 is put when being configured to bridging chip 6, now COMMAND control interfaces can pass through COMMAND control modules 4-
4 can break the data path of COMMAND patterns, and now data conversion module 4-5 can stagnate work, will not also give bridging chip
6 send related data, and after MIPI configuration modules unit 8 terminates to the configuration of bridging chip 6, COMMAND control interfaces can be sent out
Send one to instruct and give COMMAND control module 4-4, now COMMAND control modules 4-4 can be by the Data-Link of COMMAND patterns
Road is open-minded, and data conversion module 4-5 also begins to normal work, and recognizable clock signal is sent to bridging chip 6.
COMMAND control modules 4-4 and image detection module 4-2 is as follows with cutting associating for figure command module 4-3：Work as image detection module
4-2 is sent when cutting figure and instructing to COMMAND control module 4-4, and COMMAND control modules 4-4 can break COMMAND mode datas
Path, cuts figure command module 4-3 and integrated order is sent into bridging chip 6, order hair by data conversion module 4-5
Send and inform that COMMAND control modules 4-4 opens data path after finishing, data-signal is sent by data conversion module 4-5
To bridging chip 6.
Data conversion module 4-5 is used to be converted into rgb video signal to send to interface after data bus interface signal to cut
Switch 5 is changed, interface switching switch 5 sends data bus interface signal to bridging chip 6, and bridging chip 6 connects data/address bus
Message number is converted into send to liquid crystal module 7 after MIPI signals and shown.Rgb signal is changed into bridge joint by data conversion module 4-5
Recognizable data bus interface (the Data Bus Interface) signal of chip 6, is ultimately transferred to liquid crystal module 7 and shows.Number
The rate instruction configured according to conversion module 4-5 according to COMMAND control interfaces, controls the picture display rate of liquid crystal module 7, root
The number of pixels of Interface Controller liquid crystal module 7 is set according to the resolution ratio of liquid crystal module 7, and the two functions contribute to module manufacturer to search
The problems such as whether liquid crystal module 7 has extraordinary image vegetarian refreshments.
Interface switching switch 5 is used to set selection VIDEO patterns or COMMAND patterns according to upper strata, and by reception
Rgb interface signal or data bus interface signal are sent to bridging chip 6, bridging chip 6 by the rgb interface signal of reception or
Person's data bus interface signal is converted into send to liquid crystal module 7 after MIPI signals and shown.
MIPI configuration modules unit 8 is used to configure bridging chip 6 according to the order of upper strata instruction interface.MIPI configuration modules
Unit 8 configures bridging chip 6 by the order of upper strata instruction input interface, and is connect by the link configuration MIPI of bridging chip 6
The instruction of spreading its tail of liquid crystal module 7 at mouthful.Bridging chip 6 can be realized by MIPI bridging chips in the present invention.
Complete to realize that the method for both of which MIPI signals is comprised the following steps that by bridging chip using said apparatus：
User is set to realizing under VIDEO patterns, and step is as follows：
0) be off mode switch 2, be not directed to VIDEO patterns or COMMAND patterns either party；MIPI
Configuration module unit 8 configures bridging chip 6, and bridging chip 6 is configured to be under VIDEO mode states, and by bridging core
Piece 6 carries out configuration of spreading its tail to liquid crystal module 7, and liquid crystal module 7 is also required to configuration under VIDEO patterns.
1) LVDS turns RGB block 1 LVDS vision signals is converted into rgb video signal, and this flow can exist always,
LVDS vision signals constantly enter LVDS and turn RGB block 1 in a steady stream, and LVDS turns RGB block 1 also can be continuously by LVDS
Vision signal changes into rgb video signal.
2) the related instruction of VIDEO/COMMAND switch interfaces configuration switches to current data link to mode switch 2
VIDEO mode links end.
3) rgb video signal is converted into the signal sequence that bridging chip 6 needs by VIDEO mode datas processing module 3, such as
Sequential shown in Fig. 2.Need not be cut under VIDEO patterns figure instruction, such as step 1) shown in, data can continuously from
LVDS ends are sent in the present apparatus, and VIDEO mode datas processing module 3 also can continuously parse rgb signal, now
Data rate is, than faster, energy to be expended so comparing under VIDEO patterns, but this Schema control mechanism is simple, shows
Also quickly, what can be do not missed completely is sent to image liquid crystal module 7 to figure speed.
3.1) pixel clock first, in rgb video signal, image timing signals (VS, HS, DE), view data point
Supplementary biography delivers to local clock module 3-1, local timing modules 3-2 and local image buffer storage module 3-3；
3.2) in local clock module 3-1, first the pixel clock progress de-jitter to input makes it become stable,
(instruction is according to different modules for " the clock phase, frequency trim " control instruction provided further according to local image control interface
Characteristic is set by user) produce local pixel clock and give picture signal synchronization module 3-4 output is produced on the basis of the clock
Picture signal to screen.
3.3) in local image buffer storage module 3-3, two pixel columns first are cached to view data, it is therefore an objective to avoid input
Signal because transmission, conversion caused by shake, it is unstable, then by picture signal synchronization module take out generation local image signal.
3.4) in local timing modules 3-2, the view data for being and inputting keeps synchronous, also first to image timing
Signal caches two pixel columns, and producing local timing signals (VS, HS, DE) until next frame starts again afterwards gives image letter
Number synchronization module 3-4.
3.5) in picture signal synchronization module 3-4, with the local pixel clock of input as system clock to inputting this
Ground timing samples, while reading local image buffer storage module 3-3 data when local DE is effective, then uses local pixel clock
Two minor ticks are made a call to its local timing and view data to eliminate potential metastable state to ensure that the reliable and stable RGB of output connects
Message number.
3.6) in output interface module 3-5, input after local rgb interface signal, by local pixel clock phase shift with right
The sample window mouth region arrived together in the middle of the signal of local view data, then (including clock, timing believe by local picture signal
Number, data) strengthen its drive carrying load ability after export to interface switching switch 5.
4) interface switching switch 5 sends the rgb interface signal of reception to bridging chip 6.RGB as shown in Figure 4 connects
The rgb interface signal of reception is converted into send to liquid crystal module 7 after MIPI signals and shown by message number, bridging chip 6, so as to reach
To a screen effect.
User is set to realizing under COMMAND patterns, and step is as follows：
0) be off mode switch 2, be not directed to VIDEO patterns or COMMAND patterns either party；MIPI
Configuration module unit 8 configures bridging chip 6, bridging chip 6 is configured to be under COMMAND mode states, and pass through bridge joint
Chip 6 carries out configuration of spreading its tail to liquid crystal module 7, and liquid crystal module 7 is also required to configuration under COMMAND patterns.MIPI configuration modules
When unit 8 configures bridging chip 6 and liquid crystal module 7 to COMMAND patterns, it is in COMMAND control modules 4-4 and closes shape
COMMAND control modules 4-4 is then turned on after the completion of state, configuration.
1) LVDS turns RGB block 1 LVDS vision signals is converted into rgb video signal, and this flow can exist always,
LVDS vision signals constantly enter LVDS and turn RGB block 1 in a steady stream, and LVDS turns RGB block 1 also can be continuously by LVDS
Vision signal changes into rgb video signal.
2) liquid crystal module resolution ratio sets interface to set COMMAND moulds according to the resolution requirements of current liquid crystal module 7
Formula data buffer 4-1 cache size, and this resolution information is sent to data conversion module 4-5 simultaneously.
3) COMMAND mode datas buffer 4-1 caches the frame image data in the rgb video signal of reception.This
Place due to being input to COMMAND mode data buffers 4-1 first data it should be noted that be not necessarily a frame data
Frame head, therefore set frame section start testing mechanism to ensure the data write every time in COMMAND mode data buffers 4-1
It is the complete view data of a frame from frame head to postamble.Frame section start testing mechanism can do an enable, when frame head arrives this
The enable of individual mechanism is just effective, after a frame data are sent, and enables invalidating signal, and this mechanism also ensure that caching simultaneously
It is a frame signal to the data in COMMAND mode data buffers 4-1, and signal is from frame head to postamble.
, can be to an indication signal to COMMAND after a COMMAND mode data buffers 4-1 storages full frame signal
Control module 4-4, now COMMAND control modules 4-4 start since COMMAND mode data buffers 4-1 read data.
4) view data cached in COMMAND control modules 4-4 reading COMMAND mode data buffers 4-1 is concurrent
Data conversion module 4-5 is delivered to, view data is converted to data bus interface signal and be sent to and connect by data conversion module 4-5
Mouth switching switch 5, data bus interface signal is sent to bridging chip 6 through interface switching switch 5, and bridging chip 6 is total by data
Line interface signal, which is converted to MIPI signals, to be transmitted to liquid crystal module 7 and shows.COMMAND control modules 4-4 is by the data read
Send and holding state is in data conversion module 4-5, wait starts next time.Data conversion module 4-5 has three functions：
Function one is exactly that rgb signal is converted into the clock signal that bridging chip 6 needs, and signal sequence is as shown in Figure 2；Function two is logical
The image resolution ratio size that liquid crystal module resolution ratio sets interface synchronization and COMMAND mode data buffers 4-1 is crossed, according to setting
Put the picture for the pixel number for requiring to indicate a need for；Function three is to be input to bridge joint by the regulation of COMMAND control interfaces
The speed of the input data of chip 6, data bus interface signal as shown in Figure 5, bridging chip 6 can be in data bus interface
The rising edge of signal clock has detected whether enable signal, then gathered data when having enable signal, data bus interface signal
Frequency determines the aobvious figure speed of liquid crystal module 7.The bridging chip 6 of data bus interface signal is received by data bus interface
Signal is converted into MIPI signals, so as to reach a screen effect.
5) image detection module 4-2 receives the view data in rgb video signal, and in rgb video signal is detected
View data send when changing and cut figure instruction.
Image detection module 4-2 is detected in the rgb video signal to reception always, when the first two field picture is sent to figure
During as detection module 4-2, the buffer that some as far as possible many pixels are stored in inside image detection module 4-2 can be therefrom extracted
In, then the data since the second frame below can be contrasted with the first frame data of caching, until two frame signals are contrasted not
When consistent, it will be sent to figure command module 4-3, COMMAND mode data buffer 4-1 and COMMAND control module 4-4 is cut
The instruction of figure information is cut, at the same time, new frame signal information storage can also be arrived inner buffer by image detection module 4-2 itself
In device, then proceed to detect follow-up image.
When image detection module 4-2 detects that rgb video signal changes, and COMMAND control modules 4-4 is from user
The COMMAND control interfaces of setting receive local when cutting the enable signal and image location information of figure, image detection module 4-2
Send and cut figure instruction, the enable signal and image location information that locally cut figure are converted into local cut by COMMAND control modules 4-4
Figure configuration information is simultaneously sent to bridging chip 6, the configuration liquid crystal module 7 of bridging chip 6, treats COMMAND mode data buffers 4-1
During according to cutting the next two field picture of figure instruction buffer, COMMAND control modules 4-4 reads COMMAND moulds according to image location information
The part image data cached in formula data buffer 4-1, and send to data conversion module 4-5, then by data conversion module
View data is converted to data bus interface signal and transmitted to interface switching switch 5 by 4-5, and interface switching switch 5 will be received
Data bus interface signal send to bridging chip 6, the data bus interface signal of reception is converted into MIPI by bridging chip 6
Send to liquid crystal module 7 and show after signal.
6) COMMAND mode datas buffer 4-1 is according to the next two field picture for cutting figure instruction buffer rgb video signal.
COMMAND mode buffers 4-1, cut figure command module 4-3 and COMMAND control module 4-4 and receive image detection
What module 4-2 was sent cuts after the instruction of figure information, and COMMAND mode data buffers 4-1 can be again by a new frame image information
Storage, the mode of storage and the item that should be noted are in step 2) in done detailed description.COMMAND control module 4-4 meetings
Data link is broken, that is, disconnects the link between COMMAND mode data buffer 4-1 and data conversion module 4-5, then
Open and cut link between figure command module 4-3 and data conversion module 4-5, cutting figure command module 4-3 can will be stored good
Cut figure instruction bridging chip 6 is transferred to by data conversion module 4-5, after instruction is sent, COMMAND control modules
4-4 opens the link between COMMAND mode data buffer 4-1 and data conversion module 4-5.
7) repeat step 4) to step 6).
It the above is only the preferred embodiment of the present invention, it is noted that come for those skilled in the art
Say, under the premise without departing from the principles of the invention, can be devised by some improvement, these improvement also should be regarded as the guarantor of the present invention
Protect scope.
Claims (8)
1. a kind of method that both of which MIPI signals are realized by bridging chip, it is characterised in that：Comprise the following steps：
1) LVDS signals are converted into rgb video signal；
2) according to selection VIDEO patterns or COMMAND patterns is set, if 3) selection VIDEO patterns go to step, if selection
4) COMMAND patterns go to step；
3) rgb video signal of reception is converted into rgb interface signal by the rgb video signal according to VIDEO patterns；
4) rgb video signal of reception is converted into data bus interface by the rgb video signal according to COMMAND patterns
Data Bus Interface signals；Specific steps include：
4.1) the first frame image data in rgb video signal is cached；
4.2) view data of the caching is converted into data bus interface signal and transmitted to bridging chip (6), the bridge
Connect chip (6) by data bus interface signal be converted to MIPI signals transmit to liquid crystal module (7) show；
4.3) judge whether next frame image data in the rgb video signal is identical with former frame, when next two field picture number
According to not being simultaneously emitted by cutting figure instruction with former frame；
4.4) according to the next two field picture for cutting figure instruction buffer rgb video signal；
4.5) repeat step 4.2) to step 4.4)；
5) sent according to setting selection rgb interface signal or data bus interface signal to bridging chip (6), the bridge joint core
Rgb interface signal or data bus interface signal are converted into after MIPI signals by piece (6) to be sent to liquid crystal module (7) display.
2. the method according to claim 1 that both of which MIPI signals are realized by bridging chip, it is characterised in that：Institute
State step 1) before also include configuration bridging chip (6) and the step of liquid crystal module (7) to VIDEO patterns.
3. the method according to claim 1 that both of which MIPI signals are realized by bridging chip, it is characterised in that：Institute
State step 1) before also include configuration bridging chip (6) and the step of liquid crystal module (7) to COMMAND patterns.
4. the method according to claim 2 that both of which MIPI signals are realized by bridging chip, it is characterised in that：Institute
State step 3) specific steps include：
3.1) by the front two row data buffer storage in rgb video signal；
3.2) local pixel clock is produced；
3.3) local timing signals are produced；
3.4) with the local pixel clock as the local timing signal sampling of the system clock to input, while in institute
State the DE in local timing signals it is effective when read the caching data formation synchronizing signal；
3.5) synchronizing signal is converted into rgb interface signal.
5. the method according to claim 1 that both of which MIPI signals are realized by bridging chip, it is characterised in that：Institute
State step 4.1) in by the rgb video signal the first frame image data cache when set frame section start testing mechanism, inspection
Start recording data after frame head are measured, stop recording data when detecting next frame frame head.
6. a kind of device that both of which MIPI signals are realized by bridging chip, it is characterised in that：Turn RGB block including LVDS
(1), mode switch (2), VIDEO mode datas processing module (3), COMMAND mode datas processing module (4) and interface switching
Switch (5)；
The LVDS, which turns RGB block (1), to be used to LVDS vision signals being parsed into rgb video signal；
The mode switch (2) is used to set selection VIDEO patterns or COMMAND patterns according to upper strata, and rgb video is believed
Number transmit to VIDEO mode datas processing module (3) or COMMAND mode datas processing module (4)；
The VIDEO mode datas processing module (3) is used to the rgb video signal of reception is converted into RGB according to VIDEO patterns
Sent after interface signal to interface switching switch (5)；
The COMMAND mode datas processing module (4) is used to convert the rgb video signal of reception according to COMMAND patterns
To be sent after data bus interface (Data Bus Interface) signal to interface switching switch (5)；
The interface switching switch (5) is used to set selection VIDEO patterns or COMMAND patterns according to upper strata, and will receive
Rgb interface signal or data bus interface signal send to bridging chip (6), the bridging chip (6) is by the RGB of reception
Interface signal or data bus interface signal, which are converted into after MIPI signals, to be sent to liquid crystal module (7) display；
The COMMAND mode datas processing module (4) includes COMMAND mode datas buffer (4-1), image detection module
(4-2), cut figure command module (4-3), COMMAND control modules (4-4) and data conversion module (4-5)；
The COMMAND mode datas buffer (4-1) is used to receive rgb video signal and stores a frame image data；
Whether the view data and detection image that described image detection module (4-2) is used to receive in rgb video signal become
Change, and send when image changes and to cut figure instruction；
The figure command module (4-3) of cutting cuts unlatching COMMAND control modules after figure instruction for detecting；
The COMMAND control modules (4-4) are used for the view data for reading rgb signal in COMMAND mode data buffers
And send to data conversion module；
The data conversion module (4-5) is used to rgb video signal being converted into after data bus interface signal to send to interface
Switching switch (5).
7. the device according to claim 6 that both of which MIPI signals are realized by bridging chip, it is characterised in that：Institute
Stating VIDEO mode datas processing module (3) includes local clock module (3-1), local timing modules (3-2), local image
Cache module (3-3) picture signal synchronization module (3-4) and output interface module (3-5)；
When the local clock module (3-1) is used to produce local pixel according to the control instruction of local image control interface offer
Clock is sent to picture signal synchronization module (3-4)；
The local timing modules (3-2) are used to produce local timing signals (VS, HS, DE) and to be sent to picture signal same
Walk module (3-4)；
The local image buffer storage module (3-3) is used to cache two pixel columns to rgb video signal；
Described image signal synchronization module (3-4) is used for local to inputting as system clock with the local pixel clock of input
Timing signal samplings, while the DE in the local timing signals reads local image buffer storage module (3-3) when effective
Data, then export to form synchronizing signal to output interface module (3-5) with local pixel clock；
Synchronizing signal is converted into rgb interface signal and exported to interface switching switch (5) by the output interface module (3-5).
8. the device according to claim 7 that both of which MIPI signals are realized by bridging chip, it is characterised in that：Also
Including MIPI configuration modules unit (8), for configuring bridging chip (6) according to the order of upper strata instruction interface, and by described
Bridging chip (6) configuration liquid crystal module (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410414927.XA CN104202552B (en) | 2014-08-21 | 2014-08-21 | The method and apparatus that both of which MIPI signals are realized by bridging chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410414927.XA CN104202552B (en) | 2014-08-21 | 2014-08-21 | The method and apparatus that both of which MIPI signals are realized by bridging chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104202552A CN104202552A (en) | 2014-12-10 |
| CN104202552B true CN104202552B (en) | 2017-09-05 |
Family
ID=52087772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410414927.XA Active CN104202552B (en) | 2014-08-21 | 2014-08-21 | The method and apparatus that both of which MIPI signals are realized by bridging chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104202552B (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104469349B (en) * | 2014-12-11 | 2016-09-07 | 武汉精测电子技术股份有限公司 | A kind of method detecting the MIPI vision signal that video source produces |
| CN104615399B (en) * | 2015-02-09 | 2018-08-17 | 上海与德通讯技术有限公司 | The transmission method and electronic device of display data |
| CN104822041B (en) * | 2015-04-30 | 2017-12-05 | 武汉精测电子技术股份有限公司 | The method and apparatus that the VIDEO and COMMAND functions of MIPI signals are realized based on FPGA |
| CN104795039B (en) * | 2015-04-30 | 2017-03-22 | 武汉精测电子技术股份有限公司 | FPGA (field programmable gate array) based method and FPGA based device for adjusting MIPI (mobile industry processor interface) signal transmission |
| CN104796654B (en) * | 2015-04-30 | 2018-07-03 | 武汉精测电子集团股份有限公司 | The method and apparatus that 8LANE, 16LANE MIPI signals are realized based on FPGA |
| CN104780334B (en) * | 2015-04-30 | 2018-04-24 | 武汉精测电子集团股份有限公司 | Method and apparatus based on the FPGA MIPI LANE train of signalizations outputs realized |
| CN104952421B (en) * | 2015-07-13 | 2018-04-24 | 武汉精测电子集团股份有限公司 | A kind of method and system for generating the MIPI signals for being used for the detection of MIPI modules |
| CN107358899A (en) * | 2017-08-29 | 2017-11-17 | 深圳市佳彩光电科技有限公司 | A kind of the point screen device and method of the multiplexing based on LVDS transmission |
| CN108052478B (en) * | 2017-12-28 | 2020-01-21 | 苏州联视泰电子信息技术有限公司 | Bridging device based on FPGA |
| CN109819191B (en) * | 2019-01-17 | 2021-05-04 | 武汉精立电子技术有限公司 | MIPI C-PHY signal generator and signal generating method thereof |
| CN109817129A (en) * | 2019-01-28 | 2019-05-28 | 武汉精立电子技术有限公司 | A kind of liquid crystal module detection system and method realized based on Mipi CPHY interface |
| CN111625081A (en) * | 2019-02-28 | 2020-09-04 | 上海和辉光电有限公司 | Image data processing method and device |
| CN110865590A (en) * | 2019-12-09 | 2020-03-06 | 深圳市维超科技有限公司 | A 3D display control system |
| CN112365830B (en) * | 2020-11-13 | 2022-11-15 | 苏州华兴源创科技股份有限公司 | Signal driving board |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385850A (en) * | 2010-08-31 | 2012-03-21 | 中国长城计算机深圳股份有限公司 | Signal transformation circuit and digital signal display device |
| CN202230715U (en) * | 2011-09-29 | 2012-05-23 | 深圳市雅视科技有限公司 | Universal testing device for LCM (Liquid Crystal Module) |
| CN103475840A (en) * | 2013-09-25 | 2013-12-25 | 武汉精立电子技术有限公司 | Method for switching four-LINK LVDS video signals into MIPI video signals |
| CN103475842A (en) * | 2013-09-25 | 2013-12-25 | 武汉精立电子技术有限公司 | Method for converting LVDS video signals into MIPI video signals |
| CN103491336A (en) * | 2013-09-25 | 2014-01-01 | 武汉精立电子技术有限公司 | Method for converting single-LINK LVDS video signal into MIPI video signal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8145813B2 (en) * | 2008-10-24 | 2012-03-27 | Himax Display, Inc. | Electronic device utilizing connecting port for connecting connector to transmit/receive signals with customized format |
-
2014
- 2014-08-21 CN CN201410414927.XA patent/CN104202552B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385850A (en) * | 2010-08-31 | 2012-03-21 | 中国长城计算机深圳股份有限公司 | Signal transformation circuit and digital signal display device |
| CN202230715U (en) * | 2011-09-29 | 2012-05-23 | 深圳市雅视科技有限公司 | Universal testing device for LCM (Liquid Crystal Module) |
| CN103475840A (en) * | 2013-09-25 | 2013-12-25 | 武汉精立电子技术有限公司 | Method for switching four-LINK LVDS video signals into MIPI video signals |
| CN103475842A (en) * | 2013-09-25 | 2013-12-25 | 武汉精立电子技术有限公司 | Method for converting LVDS video signals into MIPI video signals |
| CN103491336A (en) * | 2013-09-25 | 2014-01-01 | 武汉精立电子技术有限公司 | Method for converting single-LINK LVDS video signal into MIPI video signal |
Non-Patent Citations (1)
| Title |
|---|
| 基于MIPI规范的LCD驱动接口设计;苏晓峰;《中国优秀硕士学位论文全文数据库》;20120615;正文第4.3.3节 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104202552A (en) | 2014-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104202552B (en) | The method and apparatus that both of which MIPI signals are realized by bridging chip | |
| CN104240659B (en) | The method and apparatus realizing COMMAND pattern MIPI signal by bridging chip | |
| US9940869B2 (en) | Internal clock signal control for display device, display driver and display device system | |
| JP4188588B2 (en) | Method and display system for updating an image frame on a screen | |
| CN101516015B (en) | Multi-path video data acquiring, processing and transmitting method | |
| CN103475840B (en) | Method for switching four-link LVDS video signals into MIPI video signals | |
| WO2020034893A1 (en) | Intelligent interaction system, writing track display method and device, tablet and medium | |
| JP2006276221A (en) | Display driver and electronic device | |
| CN102724357A (en) | Light emitting diode (LED) dot matrix display screen control method and system based on mobile terminal | |
| CN103247249B (en) | Display control circuit, display control method and display device | |
| CN105721818A (en) | Signal conversion method and device | |
| CN104780334A (en) | Method and device achieving MIPI LANE signal serial output on basis of FPGA | |
| CN104469349A (en) | Method for detecting MIPI video signals generated by video source | |
| CN102438117A (en) | Image data acquisition method for camera on handheld terminal and handheld terminal | |
| CN109788214A (en) | A kind of multi-channel video seamless switch-over system and method based on FPGA | |
| CN209373557U (en) | Intelligent interaction system and intelligent interaction panel | |
| CN107948546A (en) | A kind of low latency video mix device | |
| CN201788657U (en) | Liquid crystal display (LCD) controller based on Nios II soft-core central processing unit (CPU) | |
| CN104615386A (en) | Off-core cache device | |
| CN110008162A (en) | A kind of buffer interface circuit and the methods and applications based on the circuit transmission data | |
| CN109587421A (en) | A kind of HD-SDI/3G-SDI transmitting-receiving and real-time picture-in-picture switch output processing method | |
| CN112527227B (en) | Dynamic sleep of display panel | |
| CN108134912A (en) | A kind of video flow converting method | |
| CN100361523C (en) | A digital camera real-time acquisition system | |
| CN203522895U (en) | Binocular Video Splicing Device Based on SOPC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 430070 11 / F, building 1, 48 Shucheng Road (Beigang Industrial Park), Hongshan District, Wuhan City, Hubei Province Patentee after: WUHAN JINGCE ELECTRONIC GROUP Co.,Ltd. Address before: 430070, 4 floor, Hongshan Pioneer Center, 53 Nanhu Avenue, Hongshan District, Hubei, Wuhan Patentee before: WUHAN JINGCE ELECTRONIC GROUP Co.,Ltd. |