CN104218133B - Light emitting diode chip and manufacturing method thereof - Google Patents

Abstract

The invention discloses a light-emitting diode chip and a manufacturing method thereof, belonging to the field of light-emitting diodes. The light-emitting diode chip includes: a substrate, an N-type layer, multiple quantum wells, and a P-type layer that are sequentially covered on the substrate, and a discontinuous N-type etching layer is arranged on the N-type layer, the multiple quantum wells, and the P-type layer. Area, the N-type etching area includes etching planes and steps, the etching plane is on the N-type layer, and the steps are slopes passing through the N-type layer, multiple quantum wells and P-type layers in sequence; the LED chip also includes: a current blocking layer , N electrode and P electrode; the current blocking layer includes a first covering part and a second covering part, and the first covering part of the current blocking layer covers the unetched P between a plurality of discontinuous N-type etching regions. On the P-type layer and the step, the second covering part of the current blocking layer covers a continuous unetched area on the P-type layer; the N electrode covers the first covering part of the current blocking layer and the discontinuous N-type etched area the etching plane.

Description

A light-emitting diode chip and its manufacturing method

technical field

The present invention relates to the field of light emitting diodes (Light Emitting Diode, “LED” for short), in particular to a light emitting diode chip and a manufacturing method thereof.

Background technique

As a new type of light-emitting device, LED lighting has the advantages of energy saving, environmental protection, longevity and high efficiency compared with traditional electric lighting methods. It is recognized by various countries as the most promising high-efficiency lighting industry.

With the advancement of the market and technology, the luminous efficiency of LEDs continues to increase, but in order to continue to expand applications, the luminous efficiency of LEDs still needs to be further improved. As a semiconductor light-emitting device, LED must make electrodes on the surface to expand the current. The electrodes contain some light-absorbing materials, which are not absolutely transparent. Part of the light emitted by the semiconductor layer is absorbed when passing through the electrodes. The larger the scale of the electrodes, the more The more light absorbed, the less light reaches the outside,

At the same time, in order to improve the uniformity of current spreading, the electrodes of many light-emitting chips (especially high-power chips) are not single solder joints, but multiple linear electrodes drawn from the solder joints are made to guide the current to Flow in a predetermined direction, so as to achieve uniform distribution of injection current in the semiconductor layer. This technology improves the performance of the chip to a certain extent, but it also increases the proportion of light emitted inside the semiconductor chip that is absorbed. In order to reduce the problem of light being absorbed by the electrode, a current blocking layer of a certain width is usually made under the P electrode. It is used to avoid the light that is easily absorbed by the electrode due to the vertical injection of current generated directly under the electrode.

In the process of realizing the present invention, the inventor finds that there are at least the following problems in the prior art:

For the N electrode, because it grows on the N-type layer, during the chip manufacturing process, it is necessary to etch the light-emitting area of the area where the N electrode is made to form an N-type etched area similar to the shape of the electrode. The more electrodes , the more light-emitting area is etched away, the smaller the light-emitting area of the chip will be, thus affecting the luminous efficiency of the LED.

Contents of the invention

In order to solve the problem in the prior art that the light-emitting area in the area where the N-electrode is made needs to be etched away to affect the luminous efficiency of the LED when making the N-electrode, an embodiment of the present invention provides a light-emitting diode chip and a manufacturing method thereof. Described technical scheme is as follows:

On the one hand, an embodiment of the present invention provides a light-emitting diode chip, which includes: a substrate, an N-type layer covering the substrate in sequence, multiple quantum wells, and a P-type layer, and the N-type Layer, multiple quantum wells and P-type layer are provided with a plurality of discontinuous N-type etching regions, each of the N-type etching regions includes etching planes and steps, and the etching planes are located in the N-type layer above, the step is a slope passing through the N-type layer, the multiple quantum wells and the P-type layer in sequence;

The light emitting diode chip also includes: a current blocking layer, an N electrode and a P electrode;

The current blocking layer includes a first covering portion and a second covering portion, and the first covering portion of the current blocking layer covers the unetched P-type area between the plurality of discontinuous N-type etching regions. layer and the step, the second covering portion of the current blocking layer covers a continuous unetched region on the P-type layer;

The N electrode covers the first covering portion of the current blocking layer and the etching planes of the plurality of discontinuous N-type etching regions;

The P-electrode includes a first portion covering the surface of the P-type layer and a second portion covering the second covering portion of the current blocking layer, the first portion and the second portion being connected.

In an implementation manner of the embodiment of the present invention, the current blocking layer is a silicon dioxide layer or a silicon nitride layer.

In another implementation manner of the embodiment of the present invention, the light emitting diode chip further includes an indium tin oxide layer, and the indium tin oxide layer is disposed between the current blocking layer and the first part of the P electrode.

In another implementation manner of the embodiment of the present invention, the LED chip further includes a passivation layer disposed on the surface layer of the chip, the passivation layer covers the N electrode and the P electrode, and exposes the N electrode and the P electrode. electrode and part of the surface of the P-electrode.

On the other hand, an embodiment of the present invention also provides a method for manufacturing a light emitting diode chip, the method comprising:

Deposit N-type layer, multiple quantum wells and P-type layer sequentially on the sapphire substrate;

A plurality of discontinuous N-type etching regions are etched on the N-type layer, the multiple quantum wells and the P-type layer, each of the N-type etching regions includes an etching plane and a step, and the etching plane is in the On the N-type layer, the step is a slope passing through the N-type layer, the multiple quantum wells and the P-type layer in sequence;

growing a current blocking layer, the current blocking layer includes a first covering portion and a second covering portion, the first covering portion of the current blocking layer covers the gaps between the plurality of discontinuous N-type etched regions On the etched P-type layer and on the step, a second covering portion of the current blocking layer covers a continuous unetched region on the P-type layer;

growing a P electrode and an N electrode respectively, the N electrode covering the first covering portion of the current blocking layer and the etching planes of the plurality of discontinuous N-type etching regions, the P electrode including covering the A first part of the surface of the P-type layer and a second part covering the second covering part of the current blocking layer, the first part and the second part are connected.

In an implementation of an embodiment of the present invention, the etching a plurality of discontinuous N-type etching regions on the N-type layer, the multiple quantum wells and the P-type layer includes:

Spin-coat a layer of photoresist on the surface of the P-type layer, and use natural photolithography to form patterns on the surface;

Etching the pattern on the photoresist to obtain the N-type etched area;

Remove remaining photoresist.

In another implementation manner of the embodiment of the present invention, the growing current blocking layer includes:

Depositing a layer of silicide on the surface of the N-type etched region and the unetched P-type layer;

A layer of photoresist is spin-coated on the surface of the silicide, and a pattern is formed on the surface by natural photolithography;

Corroding or etching the pattern on the photoresist to remove the current blocking layer on the etching plane;

Remove remaining photoresist.

In another implementation manner of the embodiment of the present invention, the silicide is silicon dioxide or silicon nitride.

In another implementation manner of the embodiment of the present invention, the method further includes: growing an indium tin oxide layer between the current blocking layer and the first part of the P electrode.

In another implementation manner of the embodiment of the present invention, the method further includes: growing a passivation layer on the surface layer of the chip, the passivation layer covering the N electrode and the P electrode, and exposing the N electrode and the P electrode. Part of the surface of the P electrode.

The beneficial effects brought by the technical solution provided by the embodiments of the present invention are:

By setting a discontinuous N-type etching area on the N-type layer, multiple quantum wells and P-type layer, the N-type etching area includes an etching plane and steps, the etching plane is on the N-type layer, and the steps pass through the N-type layer in sequence. type layer, multiple quantum wells and slopes of the P-type layer, the first covering part of the current blocking layer covers the unetched P-type layer and steps between the discontinuous N-type etching regions, and the second covering part of the current blocking layer The first covering part covers a continuous unetched area on the P-type layer, and the N electrode covers the first covering part of the current blocking layer and the discontinuous N-type etching area; since the N-type etching area is discontinuous, Therefore, the N-type etching area required for making the N electrode is reduced, and a certain current blocking layer is made under the N electrode, and the effective light-emitting area of the chip is increased while maintaining the chip area and reliability, thereby improving the brightness of the chip.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic structural view of a light emitting diode chip provided by Embodiment 1 of the present invention;

Fig. 2 is a sectional view at A-A place in Fig. 1;

Fig. 3 is a sectional view at B-B place in Fig. 1;

FIG. 4 is a flow chart of a method for manufacturing a light-emitting diode chip provided by Embodiment 2 of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Embodiment one

A light-emitting diode chip according to an embodiment of the present invention, as shown in FIGS. 1-3 , the light-emitting diode chip includes:

The substrate 101, the N-type layer 102, the multiple quantum wells 103 and the P-type layer 104 covering the substrate 101 in turn, are provided with a plurality of discontinuous N-type layers 102, the multiple quantum wells 103 and the P-type layer 104. type etching region 108, each N-type etching region 108 includes an etching plane 1081 and a step 1082, the etching plane 1081 is on the N-type layer 102, and the step 1082 passes through the N-type layer 102, the multiple quantum well 103 and the P The slope of the type layer 104.

The LED chip also includes: a current blocking layer 105 , an N electrode 106 and a P electrode 107 .

The current blocking layer 105 includes a first covering portion and a second covering portion, and the first covering portion of the current blocking layer 105 covers the unetched P-type layer 104 and On the step 1082, the second covering part of the current blocking layer 105 covers a continuous unetched area on the P-type layer 104;

The N electrode 106 covers the first covering portion of the current blocking layer 105 and the etching planes of a plurality of discontinuous N-type etching regions 108;

The P electrode 107 includes a first portion covering the surface of the P-type layer 104 and a second portion covering the second covering portion of the current blocking layer 105 , the first portion and the second portion are connected.

In this embodiment, the plurality of discontinuous N-type etched regions 108 may be arranged in a straight line or irregularly. The shape of the etching plane 1081 of each N-type etching region 108 can be rectangular, circular or irregular. The N-electrode 106 may be strip-shaped, as shown in FIG. 1 , and its thickness may be fixed, that is, the thickness may not change along with its lengthwise extension, or it may not be fixed; of course, the N-electrode 106 may also be in other shapes.

In this embodiment, the current blocking layer 105 includes a first covering part and a second covering part, this design can save material and reduce cost. In other embodiments, the area covered by the current blocking layer 105 is not limited thereto, except for the surface of the P-type layer 104 under the etching plane 1081 and the first part of the P electrode 107, other areas can be provided with the current blocking layer 105, that is to say, Other covering parts may be provided on the surface of the P-type layer 104 . In this embodiment, the first part of the P electrode 107 is in the shape of a cylinder, and the second part is in the shape of a cuboid, the two are connected as one, and the surfaces are in the same plane. It is easy to understand that the shape of the P electrode 107 is not limited thereto.

In this embodiment, the current blocking layer 105 may be a silicon dioxide layer or a silicon nitride layer.

Further, the LED chip also includes:

Indium Tin Oxide (Indium Tin Oxides, “ITO” for short) layer 109 , the ITO layer 109 is disposed between the current blocking layer 105 and the first part of the P electrode 107 . As shown in FIG. 2 , the ITO layer 109 also includes a portion not covered by the P-electrode 107 . The ITO layer 109 enables the current injected into the light-emitting diode chip to spread quickly and uniformly, increasing the electronic activity, so as to achieve the purpose of improving the light conversion efficiency of the chip.

Further, the LED chip also includes:

The passivation layer is arranged on the surface layer of the chip, and the passivation layer covers the N electrode 106 and the P electrode 107 and exposes part of the surface of the N electrode 106 and the P electrode 107 . The passivation layer may also cover the portion of the ITO layer 109 not covered by the P electrode 107 . The passivation layer is used to protect the N electrode 106 , the P electrode 107 and the ITO layer 109 of the chip.

In the embodiment of the present invention, a discontinuous N-type etching region is provided on the N-type layer, the multiple quantum wells, and the P-type layer. The N-type etching region includes an etching plane and steps, the etching plane is on the N-type layer, and the steps are In order to pass through the slope of the N-type layer, the multiple quantum wells and the P-type layer in sequence, the first covering part of the current blocking layer covers the unetched P-type layer and steps between the discontinuous N-type etching regions, and the current blocking layer The second covering part of the layer covers a continuous unetched area on the P-type layer, and the N electrode covers the first covering part of the current blocking layer and the discontinuous N-type etching area; since the N-type etching area is Discontinuously, thus reducing the N-type etching area required to make the N electrode, and making a certain current blocking layer under the N electrode, while maintaining the chip area and reliability, the effective light-emitting area of the chip is increased, and then Increase chip brightness.

Embodiment two

A method for manufacturing a light-emitting diode chip according to an embodiment of the present invention, as shown in FIG. 4 , the method includes:

Step 201: sequentially depositing an N-type layer, multiple quantum wells and a P-type layer on a sapphire substrate.

Step 202: Etching a plurality of discontinuous N-type etching regions on the N-type layer, the multiple quantum wells and the P-type layer, each N-type etching region includes an etching plane and a step, and the etching plane is in the N-type layer On the top, the steps are slopes passing through the N-type layer, the multiple quantum wells and the P-type layer in sequence.

Specifically, etching discontinuous N-type etching regions on the N-type layer, the multiple quantum wells and the P-type layer can be achieved in the following manner:

Step 1: Spin-coat a layer of photoresist on the surface of the P-type layer, and use natural photolithography to form patterns on the surface.

Step 2: Etching the pattern on the photoresist to obtain a plurality of discontinuous N-type etching regions.

Step 3, removing the remaining photoresist.

Step 203: growing a current blocking layer. The current blocking layer includes a first covering portion and a second covering portion. The first covering portion of the current blocking layer covers the unetched areas between a plurality of discontinuous N-type etching regions. On the P-type layer and the step, the second covering portion of the current blocking layer covers a continuous unetched area on the P-type layer.

Specifically, step 203 can be implemented in the following manner:

Step 1, depositing a layer of silicide on the surface of the N-type etched region and the unetched P-type layer.

Step 2: Spin-coat a layer of photoresist on the surface of the silicide, and use natural photolithography to form patterns on the surface.

Step 3, corroding or etching the pattern on the photoresist to remove the current blocking layer on the etching plane.

Step 4, removing the remaining photoresist.

Wherein, the silicide may be silicon dioxide or silicon nitride, that is, the current blocking layer may be a silicon dioxide layer or a silicon nitride layer.

Step 204: growing the P electrode and the N electrode respectively, the N electrode covers the first covering part of the current blocking layer and the etching plane of a plurality of discontinuous N-type etching regions, and the P electrode includes the surface covering the P-type layer The first part of the current blocking layer and the second part covered on the second covering part of the current blocking layer, the first part and the second part are connected.

Further, the method further includes: growing an ITO layer between the current blocking layer and the first part of the P electrode. The ITO layer also includes a portion not covered by the P electrode. The ITO layer enables the current injected into the light-emitting diode chip to diffuse quickly and uniformly, increasing the electronic activity performance, so as to achieve the purpose of improving the light conversion efficiency of the chip.

Further, the method further includes: growing a passivation layer on the chip surface, the passivation layer covers the N electrode and the P electrode, and exposes part of the surface of the N electrode and the P electrode. The passivation layer can also cover the part of the above-mentioned ITO layer not covered by the P electrode. The passivation layer is used to protect the N electrode, P electrode and ITO layer of the chip.

In this embodiment, a plurality of discontinuous N-type etching regions may be arranged in a straight line or irregularly. The shape of the etching plane of each N-type etching region can be rectangular, circular or irregular. The N-electrode can be in the shape of a strip, and its thickness can be fixed, that is, the thickness does not change as it extends along the length direction, or it can be unfixed; of course, the N-electrode can also be in other shapes.

In this embodiment, the current blocking layer includes a first covering part and a second covering part, and this design can save materials and reduce costs. In other embodiments, the coverage area of the current blocking layer is not limited thereto, except for the surface of the P-type layer under the etching plane and the first part of the P electrode, other areas can be provided with a current blocking layer, that is to say, it can also be placed on the P-type layer. Other covering parts are arranged on the surface of the type layer. In this embodiment, the first part of the P electrode is in the shape of a cylinder, and the second part is in the shape of a cuboid, the two are connected as one, and the surfaces are in the same plane. It is easy to know that the shape of the P electrode is not limited to this.

In the embodiment of the present invention, a discontinuous N-type etching region is provided on the N-type layer, the multiple quantum wells, and the P-type layer. The N-type etching region includes an etching plane and steps, the etching plane is on the N-type layer, and the steps are In order to pass through the slope of the N-type layer, the multiple quantum wells and the P-type layer in sequence, the first covering part of the current blocking layer covers the unetched P-type layer and steps between the discontinuous N-type etching regions, and the current blocking layer The second covering part of the layer covers a continuous unetched area on the P-type layer, and the N electrode covers the first covering part of the current blocking layer and the discontinuous N-type etching area; since the N-type etching area is Discontinuously, thus reducing the N-type etching area required to make the N electrode, and making a certain current blocking layer under the N electrode, while maintaining the chip area and reliability, the effective light-emitting area of the chip is increased, and then Increase chip brightness.

The serial numbers of the above embodiments of the present invention are for description only, and do not represent the advantages and disadvantages of the embodiments.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (10)

1. A light-emitting diode chip, said light-emitting diode chip comprising: a substrate, an N-type layer, multiple quantum wells and a P-type layer covered on the substrate in turn, characterized in that said N-type layer, multiple quantum wells The quantum well and the P-type layer are provided with a plurality of discontinuous N-type etching regions, and each of the N-type etching regions includes an etching plane and a step, and the etching plane is on the N-type layer, so The step is a slope passing through the N-type layer, the multiple quantum wells and the P-type layer in sequence; The light emitting diode chip also includes: a current blocking layer, an N electrode and a P electrode; The current blocking layer includes a first covering portion and a second covering portion, and the first covering portion of the current blocking layer covers the unetched P-type area between the plurality of discontinuous N-type etching regions. layer and the step, the second covering portion of the current blocking layer covers a continuous unetched region on the P-type layer; The N electrode covers the first covering portion of the current blocking layer and the etching planes of the plurality of discontinuous N-type etching regions; The P-electrode includes a first portion covering the surface of the P-type layer and a second portion covering the second covering portion of the current blocking layer, the first portion and the second portion being connected. 2. The LED chip according to claim 1, wherein the current blocking layer is a silicon dioxide layer or a silicon nitride layer. 3. The light-emitting diode chip according to claim 1 or 2, wherein the light-emitting diode chip further comprises an indium tin oxide layer, and the indium tin oxide layer is arranged between the current blocking layer and the P electrode. between the first part. 4. The light-emitting diode chip according to claim 1 or 2, wherein the light-emitting diode chip further comprises a passivation layer arranged on the surface layer of the chip, and the passivation layer covers the N electrode and the P electrode , and expose part of the surface of the N electrode and the P electrode. 5. A method for manufacturing a light-emitting diode chip, characterized in that the method comprises: Deposit N-type layer, multiple quantum wells and P-type layer sequentially on the sapphire substrate; A plurality of discontinuous N-type etching regions are etched on the N-type layer, the multiple quantum wells and the P-type layer, each of the N-type etching regions includes an etching plane and a step, and the etching plane is in the On the N-type layer, the step is a slope passing through the N-type layer, the multiple quantum wells and the P-type layer in sequence; growing a current blocking layer, the current blocking layer includes a first covering portion and a second covering portion, the first covering portion of the current blocking layer covers the gaps between the plurality of discontinuous N-type etched regions On the etched P-type layer and on the step, a second covering portion of the current blocking layer covers a continuous unetched region on the P-type layer; growing a P electrode and an N electrode respectively, the N electrode covering the first covering portion of the current blocking layer and the etching planes of the plurality of discontinuous N-type etching regions, the P electrode including covering the A first part of the surface of the P-type layer and a second part covering the second covering part of the current blocking layer, the first part and the second part are connected. 6. The method according to claim 5, wherein said etching a plurality of discontinuous N-type etching regions on the N-type layer, the multiple quantum wells and the P-type layer comprises: A layer of photoresist is spin-coated on the surface of the P-type layer, and a pattern is formed on the surface by natural photolithography; Etching the pattern on the photoresist to obtain the N-type etched area; Remove remaining photoresist. 7. The method according to claim 5, wherein the growing current blocking layer comprises: Depositing a layer of silicide on the surface of the N-type etched region and the unetched P-type layer; A layer of photoresist is spin-coated on the surface of the silicide, and a pattern is formed on the surface by natural photolithography; Corroding or etching the pattern on the photoresist to remove the current blocking layer on the etching plane; Remove remaining photoresist. 8. The method of claim 7, wherein the silicide is silicon dioxide or silicon nitride. 9. The method according to any one of claims 5-8, further comprising: growing an indium tin oxide layer between the current blocking layer and the first part of the P-electrode. 10. The method according to any one of claims 5 to 8, further comprising: A passivation layer is grown on the chip surface, the passivation layer covers the N electrode and the P electrode, and exposes part of the surface of the N electrode and the P electrode.