CN104218152A - A kind of preparation method of organic thin film transistor - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
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Abstract
Description
技术领域 technical field
本发明涉及晶体管领域,具体涉及一种有机薄膜晶体管的制备方法。 The invention relates to the field of transistors, in particular to a preparation method of an organic thin film transistor.
背景技术 Background technique
随着信息技术的不断深入,电子产品已经进入人们生活工作中的每一个部分。传统的基于无机半导体材料的器件很难满足人们对于可便携、低成本、柔性的需求。而有机半导体材料制备的器件拥有材料来源广泛、制作工艺相对简单、制作成本较低、与柔性衬底具有良好的相容性等特点。这使得人们越来越关注基于有机聚合物半导体材料的有机微电子技术。 With the deepening of information technology, electronic products have entered every part of people's life and work. Traditional devices based on inorganic semiconductor materials are difficult to meet people's needs for portability, low cost, and flexibility. Devices made of organic semiconductor materials have the characteristics of wide material sources, relatively simple manufacturing process, low manufacturing cost, and good compatibility with flexible substrates. This has led to increasing interest in organic microelectronics based on organic polymer semiconductor materials.
有机薄膜晶体管通常包括栅电极,处于栅电极和半导体之间的绝缘层,由有机半导体材料制备而成处于源漏电极之间的半导体层,以及源电极和漏电极这几个部分。根据栅电极的特性和位置不同,有机薄膜晶体管可分为底栅薄膜晶体管(bottom-gate)、顶栅薄膜晶体管(top-gate)、侧栅薄膜晶体管(side-gate)以及液栅薄膜晶体管(liquid-gate)。目前最常见的有机薄膜晶体管是底栅构型的薄膜晶体管,主要因为半导体层的化学和物理性质一般不稳定,制备器件介电层时会对半导体层的形态和质量产生不良的影响,从而降低器件性能。所以半导体层的制备通常在介电层制备之后,即采用底栅器件构型。 An organic thin film transistor usually includes a gate electrode, an insulating layer between the gate electrode and the semiconductor, a semiconductor layer made of organic semiconductor material between the source and drain electrodes, and the source electrode and the drain electrode. According to the characteristics and positions of the gate electrodes, organic thin film transistors can be divided into bottom-gate thin film transistors (bottom-gate), top-gate thin film transistors (top-gate), side-gate thin film transistors (side-gate) and liquid gate thin film transistors ( liquid-gate). At present, the most common organic thin-film transistor is a bottom-gate thin-film transistor, mainly because the chemical and physical properties of the semiconductor layer are generally unstable, and the preparation of the device dielectric layer will have a negative impact on the shape and quality of the semiconductor layer, thereby reducing the device performance. Therefore, the semiconductor layer is usually prepared after the dielectric layer is prepared, that is, a bottom-gate device configuration is adopted.
根据源漏电极与半导体沉积顺序的不同,薄膜晶体管可分为顶接触结构和底接触结构。顶接触结构是在衬底表面先沉积半导体层,再在半导体表面沉积源漏电极,而底接触结构是源漏电极构建在介电层之上,然后在源漏电极上沉积半导体层。这两种结构的晶体管各有优缺点,顶接触结构的晶体管的源漏电极与半导体层的接触比底接触结构的要好,且半导体层受栅电极电场影响的面积大于源漏电极在底层的结构,导致期间具有较高的载流子迁移率。另外顶接触结构中有源层不受源漏电极的影响,可以在介电层表面上大面积的沉积,而且还可以通过物理或者化学方法对介电层表面进行功能化修饰,以改善半导体层薄膜的结构和形貌,以提高薄膜晶体管器件的载流子迁移率。但是这种结构在电极沉积过程中,电极材料会扩散到有源层中,导致晶体管器件关态电流增加,开关比下降,尤其对于窄沟道器件而言,这种现象更加明显。 According to the different deposition sequences of source and drain electrodes and semiconductors, thin film transistors can be divided into top contact structure and bottom contact structure. The top contact structure is to deposit a semiconductor layer on the substrate surface first, and then deposit the source and drain electrodes on the semiconductor surface, while the bottom contact structure is to build the source and drain electrodes on the dielectric layer, and then deposit the semiconductor layer on the source and drain electrodes. The transistors of these two structures have their own advantages and disadvantages. The contact between the source and drain electrodes of the transistor with the top contact structure and the semiconductor layer is better than that of the bottom contact structure, and the area of the semiconductor layer affected by the electric field of the gate electrode is larger than that of the source and drain electrodes at the bottom layer. , resulting in a higher carrier mobility during the period. In addition, the active layer in the top contact structure is not affected by the source and drain electrodes, and can be deposited on the surface of the dielectric layer in a large area, and the surface of the dielectric layer can also be functionally modified by physical or chemical methods to improve the semiconductor layer. Thin film structure and morphology to enhance carrier mobility in thin film transistor devices. However, during the electrode deposition process of this structure, the electrode material will diffuse into the active layer, resulting in an increase in the off-state current of the transistor device and a decrease in the switching ratio, especially for narrow channel devices, this phenomenon is more obvious.
有机薄膜晶体管的工作原理是利用了场效应来实现器件的工作。场效应是利用与半导体表面垂直的电场来调制半导体材料的电导率或者半导体材料中的电流的现象。当施加在栅电极上的栅压(Vg)为零时,由于半导体的本征电导率很低,即使在楼电极施加源漏电压(Vds),也几乎没有漏电流(Ids)通过,此时晶体管处在关闭状态,这种状态下晶体管的漏电流为关态电流(Ioff)。当栅电极施加一负压时,根据电容器效应,源电极端的空穴在栅电压作用下会从源电极注入半导体层,并在半导体层与介电层的界面积累起来。此时在源电极与漏电极之间施加一个负的电压,则在沟道区积累的空穴就会在源漏电压的驱动下迁移运动,形成电流,此时的器件处于开启状态。随着源漏电压的增加并达到一定值时,沟道区被夹断,由于夹断区的沟道电阻很大,因此增加的源漏电压几乎都施加于夹断区,而导电沟道两端的电压基本没有变化,进而沟道电流也不再随着源漏电压的增加而增加,沟道电流达到饱和。 The working principle of the organic thin film transistor is to use the field effect to realize the work of the device. The field effect is a phenomenon in which the electrical conductivity of a semiconductor material or the current flow in a semiconductor material is modulated by an electric field perpendicular to the semiconductor surface. When the gate voltage (Vg) applied to the gate electrode is zero, due to the low intrinsic conductivity of the semiconductor, even if the source-drain voltage (Vds) is applied to the gate electrode, there is almost no leakage current (Ids) passing through, at this time The transistor is in the off state, and the leakage current of the transistor in this state is the off-state current (Ioff). When a negative voltage is applied to the gate electrode, according to the capacitor effect, the holes at the source terminal will be injected into the semiconductor layer from the source electrode under the action of the gate voltage, and accumulate at the interface between the semiconductor layer and the dielectric layer. At this time, a negative voltage is applied between the source electrode and the drain electrode, and the holes accumulated in the channel region will migrate and move under the drive of the source-drain voltage to form a current, and the device is in an on state at this time. As the source-drain voltage increases and reaches a certain value, the channel region is pinched off. Since the channel resistance of the pinch-off region is very large, the increased source-drain voltage is almost all applied to the pinch-off region, and the two sides of the conductive channel The voltage at the terminal basically does not change, and the channel current no longer increases with the increase of the source-drain voltage, and the channel current reaches saturation.
自1986年第一次报道有机薄膜晶体管以来,该领域受到了越来越多的研究者的关注,并取得了重大突破。有机半导体材料性能逐年提高。由于近年来高迁移率有机半导体材料的合成、薄膜物理和器件构建工艺等方面研究的快速发展,有机薄膜晶体管的迁移率、开关电流比等性能,尤其是迁移率有大幅度提高,使得有机薄膜晶体管在实际的应用成为可能。 Since the first report of organic thin film transistors in 1986, more and more researchers have paid attention to this field, and significant breakthroughs have been made. The performance of organic semiconductor materials is improving year by year. Due to the rapid development of research on the synthesis of high-mobility organic semiconductor materials, thin-film physics, and device construction technology in recent years, the performance of organic thin-film transistors, such as mobility and on-off current ratio, especially the mobility has been greatly improved, making organic thin-film transistors Transistors become possible in practical applications.
发明内容 Contents of the invention
解决的技术问题:针对现有技术的不足,本发明的目的在于提供一种有机薄膜晶体管的制备方法,采用顶接触结构的薄膜晶体管,通过与微流控技术的结合,能够在保证顶接触结构薄膜晶体管的优势的前提下,有效的避免电极沉积时对于半导体材料表面的影响的缺点,从而制备出高性能的器件。 Technical problem to be solved: Aiming at the deficiencies in the prior art, the purpose of the present invention is to provide a method for preparing an organic thin film transistor. The thin film transistor adopting a top contact structure can be combined with microfluidic technology to ensure that the top contact structure On the premise of the advantages of thin film transistors, the shortcomings of the impact on the surface of semiconductor materials during electrode deposition can be effectively avoided, so as to prepare high-performance devices.
技术方案:为解决现有技术问题,本发明采取的技术方案为: Technical solution: In order to solve the problems of the prior art, the technical solution adopted by the present invention is:
一种有机薄膜晶体管的制备方法,包括以下步骤: A method for preparing an organic thin film transistor, comprising the steps of:
选衬底; Choose the substrate;
在所述衬底上制备栅电极层; preparing a gate electrode layer on the substrate;
在所述栅电极层上制备栅介电层; preparing a gate dielectric layer on the gate electrode layer;
在所述栅介电层上制备半导体活性层; preparing a semiconductor active layer on the gate dielectric layer;
在半导体活性层上制备带微通道凹槽的源漏微通道层; Prepare a source-drain microchannel layer with microchannel grooves on the semiconductor active layer;
在所述源漏微通道层上制备源电极和漏电极,所述源电极和漏电极之间的间距小于等于200μm,是将源漏微通道层的微通道凹槽上方凿孔,再用环氧树脂胶将孔与等直径的空心导管粘连成一体,最后在导管的一端注入材料,另一端加压抽取,最终在源漏微通道层上形成源电极和漏电极。 The source electrode and the drain electrode are prepared on the source-drain microchannel layer, the distance between the source electrode and the drain electrode is less than or equal to 200 μm, which is to drill a hole above the microchannel groove of the source-drain microchannel layer, and then use a ring Oxygen resin glues the hole and the hollow conduit of equal diameter into one body, and finally injects the material at one end of the conduit, and extracts it under pressure at the other end, and finally forms the source electrode and the drain electrode on the source-drain microchannel layer.
作为改进的是,在所述半导体活性层上制备界面修饰层。 As an improvement, an interface modification layer is prepared on the semiconductor active layer.
所述栅电极层的材料为银、金、铝、铜、聚3,4-乙撑二氧噻吩或聚苯乙烯磺酸盐中的一种;制备方法为真空热物理沉积、喷墨打印、旋涂、电子束沉积或溅射中的一种。 The material of the gate electrode layer is one of silver, gold, aluminum, copper, poly-3,4-ethylenedioxythiophene or polystyrene sulfonate; the preparation method is vacuum thermal physical deposition, inkjet printing, One of spin coating, electron beam deposition or sputtering.
所述栅介电层的材料为氧化硅、氮化硅、氧化铝、氧化钽、聚酰亚胺、聚乙烯吡硌烷酮或聚甲基丙稀酸甲酯中的一种;制备方法为低压化学气相沉积、喷墨打印、溅射、原子层沉积、电子束蒸发、离子辅助沉积或旋涂技术中的一种。 The material of the gate dielectric layer is one of silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, polyimide, polyvinylpyrrolidone or polymethyl methacrylate; the preparation method is One of low pressure chemical vapor deposition, inkjet printing, sputtering, atomic layer deposition, electron beam evaporation, ion assisted deposition or spin coating techniques.
所述半导体活性层的材料为聚3-已基噻吩P3HT、并五苯或钛青铜中的一种;制备方法为真空热蒸发、旋涂、喷墨打印或滴涂中的一种。 The material of the semiconductor active layer is one of poly-3-hexylthiophene P3HT, pentacene or titanium bronze; the preparation method is one of vacuum thermal evaporation, spin coating, inkjet printing or drop coating.
所述界面修饰层的材料为氧化钼MoO3;制备方法为真空热蒸发、旋涂或喷墨打印中的一种。 The material of the interface modification layer is molybdenum oxide MoO 3 ; the preparation method is one of vacuum thermal evaporation, spin coating or inkjet printing.
所述源漏微通道层的材料为聚酰胺、聚甲基丙烯酸甲酯、聚碳酸酯、聚对苯二甲酸乙二醇酯或聚二甲基硅氧烷中的一种;制备方法为塑法、热压法、LIGA 技术、激光刻蚀法或软光刻中的一种。 The material of the source-drain microchannel layer is one of polyamide, polymethyl methacrylate, polycarbonate, polyethylene terephthalate or polydimethylsiloxane; the preparation method is plastic One of the following methods, hot pressing, LIGA technology, laser lithography or soft lithography.
所述源漏微通道层与界面修饰层粘贴成一体后,在源漏微通道中制备源电极和漏电极。 After the source-drain microchannel layer and the interface modification layer are pasted together, a source electrode and a drain electrode are prepared in the source-drain microchannel.
所述源电极和漏电极的材料为导电银墨水、导电金墨水、铜墨水、石墨烯溶液或聚3,4-乙撑二氧噻吩中的一种。 The material of the source electrode and the drain electrode is one of conductive silver ink, conductive gold ink, copper ink, graphene solution or poly-3,4-ethylenedioxythiophene.
有益效果Beneficial effect
本发明提供的这种制备有机薄膜晶体管的方法,使用了传统的顶接触结构的有机薄膜晶体管,能够在保证顶接触结构薄膜晶体管接触电阻小于底接触结构的晶体管、顶接触结构的半导体层受栅电极电场影响面积大,具有比底接触结构的薄膜晶体管更高迁移率且顶接触结构中半导体层不受源漏电极的影响,可以在介电层表面大面积的沉积,可以通过物理或化学方法对介电层表面进行功能化修饰,以改善半导体层薄膜的结构和形貌,从而提高薄膜晶体管载流子迁移率的优势的前提下,有效的避免电极沉积时对于半导体材料表面的影响的缺点,从而制备出高性能的器件。 The method for preparing an organic thin film transistor provided by the present invention uses a traditional organic thin film transistor with a top contact structure, and can ensure that the contact resistance of a top contact structure thin film transistor is lower than that of a transistor with a bottom contact structure and a semiconductor layer with a top contact structure. The area affected by the electric field of the electrode is large, and it has a higher mobility than the thin film transistor with the bottom contact structure, and the semiconductor layer in the top contact structure is not affected by the source and drain electrodes, and can be deposited on a large area of the dielectric layer surface by physical or chemical methods Functional modification of the surface of the dielectric layer to improve the structure and morphology of the semiconductor layer film, thereby improving the carrier mobility of the thin film transistor, effectively avoiding the disadvantages of the impact on the surface of the semiconductor material during electrode deposition , so as to prepare high-performance devices.
附图说明 Description of drawings
图1 为源漏微通道层模型设计示意图的俯视图; Figure 1 is a top view of the design schematic diagram of the source-drain microchannel layer model;
图2 为源漏微通道层模型设计示意图的侧面图; Figure 2 is a side view of the design schematic diagram of the source-drain microchannel layer model;
图3 为有机薄膜晶体管的结构示意图,其中,1、衬底,2、栅电极层,3、栅介电层,4、半导体活性层,5、界面修饰层,6、微通道凹槽,7、源漏微通道层。 Fig. 3 is a structural schematic diagram of an organic thin film transistor, wherein, 1, substrate, 2, gate electrode layer, 3, gate dielectric layer, 4, semiconductor active layer, 5, interface modification layer, 6, microchannel groove, 7 , Source-drain microchannel layer.
具体实施方式 Detailed ways
下面的实施例可使本专业技术人员更全面地理解本发明,但不以任何方式限制本发明。 The following examples can enable those skilled in the art to understand the present invention more fully, but do not limit the present invention in any way.
本发明利用微流控技术,使用液体形态的导电材料通过制备好的微通道来代替原有的固态源漏电极,从而完成顶接触结构的有机薄膜晶体管,不仅简化了制备方法,降低了制备器件的成本,而且在保证顶接触结构有机薄膜晶体管原有的优势的前提下,很好的解决了对于顶接触结构有机薄膜晶体管普遍存在的缺陷,即由于沉积电极时对于半导体材料的影响的缺点,进一步提高了器件的性能。 The present invention utilizes microfluidic technology to replace the original solid-state source-drain electrodes with liquid-form conductive materials through prepared micro-channels, thereby completing an organic thin-film transistor with a top-contact structure, which not only simplifies the preparation method, but also reduces the cost of preparing devices. cost, and on the premise of ensuring the original advantages of top-contact organic thin-film transistors, it solves the common defects of top-contact organic thin-film transistors, that is, the shortcomings of the impact on semiconductor materials when depositing electrodes. The performance of the device is further improved.
如图1 所示,通过SolidWorks 软件设计所需的微通道模型,本图展现的是一个三通道的设计模型,由于通道的头尾需要滴加导电液体,所以设计的通道的头尾宽度需要至少大于1mm,以方便滴加导电液体。在模型的中间部分所示三个通道平行区域相距间隔为60um,左右两边的通道宽度分别为1mm,中间通道宽度为60um。根据不同的需要可以设计多条通道以实现列阵形式的有机薄膜晶体管的制备。完成通道模型的设计后,选用固化型聚合物——聚二甲基硅氧烷(PDMS)通过软光刻技术制作出柔性的具有具有通道的源漏微通道层,如图2所示。 As shown in Figure 1, the required microchannel model is designed through SolidWorks software. This figure shows a three-channel design model. Since conductive liquid needs to be added to the head and tail of the channel, the width of the head and tail of the designed channel needs to be at least Greater than 1mm, to facilitate the drop of conductive liquid. The distance between the three channel parallel regions shown in the middle part of the model is 60um, the width of the channels on the left and right sides is 1mm, and the width of the middle channel is 60um. According to different needs, multiple channels can be designed to realize the preparation of organic thin film transistors in the form of arrays. After completing the design of the channel model, the curable polymer polydimethylsiloxane (PDMS) is selected to fabricate a flexible source-drain microchannel layer with channels through soft lithography technology, as shown in Figure 2.
实施例1 Example 1
一种有机薄膜晶体管的制备方法,包括以下步骤: A method for preparing an organic thin film transistor, comprising the steps of:
选绝缘玻璃片作为衬底1;在其上通过喷墨打印技术制备栅电极层2,将银纳米墨水通过压电喷墨打印机在绝缘玻璃片上完成图形化的制备,打印好栅电极后,将绝缘玻璃片放在热台上200℃加温退火1小时制备出100nm厚的栅电极层2;通过压电喷墨打印技术,将PVP溶液打印在已制备好栅电极层2,打印完成后,将绝缘玻璃片放在热台上经过200℃的加温退火1小时制备出600nm厚的栅介电层3;通过真空热蒸发方法将钛青铜CuPc蒸镀在PVP栅介电层3上,形成60nm厚的半导体活性层4;通过真空热蒸发方法将三氧化钼蒸镀在钛青铜CuPc半导体活性层4上,形成40nm厚的界面修饰层5;将按照软件设计好的微通道模型经过软光刻技术,制备出具有微通道凹槽6的柔性PDMS源漏微通道层7,然后将PDMS具有微通道凹槽6的一面经过紫外臭氧处理10分钟后,盖在界面修饰层5上;在微通道凹槽6中通入导电银纳米粒子制备的银墨水,完成源电极和漏电极的制备。 An insulating glass sheet is selected as the substrate 1; a gate electrode layer 2 is prepared on it by inkjet printing technology, and the silver nano-ink is prepared on the insulating glass sheet through a piezoelectric inkjet printer to complete the patterning preparation. After the grid electrode is printed, the The insulating glass sheet is placed on a hot stage at 200°C and annealed for 1 hour to prepare a 100nm-thick gate electrode layer 2; through piezoelectric inkjet printing technology, the PVP solution is printed on the prepared gate electrode layer 2. After the printing is completed, Place the insulating glass sheet on a hot stage and heat and anneal at 200°C for 1 hour to prepare a gate dielectric layer 3 with a thickness of 600nm; evaporate titanium bronze CuPc on the PVP gate dielectric layer 3 by vacuum thermal evaporation to form 60nm thick semiconductor active layer 4; molybdenum trioxide is evaporated on the titanium bronze CuPc semiconductor active layer 4 by vacuum thermal evaporation to form a 40nm thick interface modification layer 5; the microchannel model designed according to the software is subjected to soft light Engraving technology, prepared a flexible PDMS source-drain microchannel layer 7 with microchannel grooves 6, and then treated the side of PDMS with microchannel grooves 6 for 10 minutes with ultraviolet and ozone, and then covered it on the interface modification layer 5; The silver ink prepared by conductive silver nanoparticles is passed into the channel groove 6 to complete the preparation of the source electrode and the drain electrode. the
实施例2 Example 2
一种有机薄膜晶体管的制备方法,包括以下步骤:: A method for preparing an organic thin film transistor, comprising the steps of:
选绝缘玻璃片作为衬底1;经过10分钟的UVO3处理后,将铝通过真空热蒸发方法在绝缘玻璃片上完成图形化的制备,形成100nm厚的铝栅电极层2;通过旋涂的方法,将PVP溶液旋涂在已制备好栅电极层2上,转速为4000RPM,时间为30S,再将绝缘玻璃片放在热台上经过200℃的加温退火1小时制备出600nm厚的栅介电层3;通过真空热蒸发方法将钛青铜CuPc蒸镀在PVP栅介电层3上,形成60nm厚的半导体活性层4;通过真空热蒸发方法将三氧化钼蒸镀在钛青铜CuPc半导体活性层上,形成40nm厚的界面修饰层5;将按照软件设计好的微通道模型经过软光刻技术,制备出具有微通道凹槽6的柔性PDMS源漏微通道层7,然后将PDMS具有微通道凹槽6的一面经过紫外臭氧处理10分钟后,盖在界面修饰层上;在微通道凹槽6中通入导电银纳米粒子制备的银墨水,完成源电极和漏电极的制备。 Select an insulating glass sheet as the substrate 1; after 10 minutes of UVO 3 treatment, the aluminum is patterned on the insulating glass sheet by vacuum thermal evaporation to form a 100nm thick aluminum gate electrode layer 2; by spin coating , Spin-coat the PVP solution on the prepared gate electrode layer 2 at a speed of 4000 RPM for 30 seconds, then place the insulating glass sheet on a hot stage and heat and anneal at 200°C for 1 hour to prepare a 600nm-thick gate dielectric. Electrical layer 3; titanium bronze CuPc is evaporated on the PVP gate dielectric layer 3 by vacuum thermal evaporation to form a 60nm thick semiconductor active layer 4; molybdenum trioxide is evaporated on the titanium bronze CuPc semiconductor active layer by vacuum thermal evaporation On the layer, a 40nm-thick interface modification layer 5 is formed; the microchannel model designed according to the software is processed by soft photolithography to prepare a flexible PDMS source-drain microchannel layer 7 with microchannel grooves 6, and then the PDMS with microchannel One side of the channel groove 6 was treated with ultraviolet and ozone for 10 minutes, and then covered on the interface modification layer; the silver ink prepared by conductive silver nanoparticles was passed into the microchannel groove 6 to complete the preparation of the source electrode and the drain electrode.
实施例3 Example 3
一种有机薄膜晶体管的制备方法,包括以下步骤: A method for preparing an organic thin film transistor, comprising the steps of:
选绝缘玻璃片作为衬底1;经过10分钟的UVO3处理后,将聚3,4-乙撑二氧噻吩溶液按照转速2000rpm,持续时间30s的条件下旋涂在衬底1上,形成200nm厚的聚3,4-乙撑二氧噻吩栅电极层2;通过旋涂的方法,将PVP溶液旋涂在已制备好栅电极层2上,转速为4000RPM,时间为30S,再将绝缘玻璃片放在热台上经过200℃的加温退火1小时制备出600nm厚的栅介电层3;通过压电喷墨打印技术将P3HT做为半导体活性材料制备在PVP栅介电层3上;选单个喷嘴,在35V电压、40μm点间距的条件下打印单层P3HT层,打印按照竖排进行,形成60nm厚的半导体活性层4,打印完成后在手套箱中的热台上,在氮气环境下按照70℃的温度退火1小时;通过真空热蒸发方法将三氧化钼蒸镀在P3HT半导体活性层4上,形成40nm厚的界面修饰层5;将按照软件设计好的微通道模型经过软光刻技术,制备出具有微通道凹槽6的柔性PDMS源漏微通道层7,然后将PDMS具有微通道凹槽6的一面经过紫外臭氧处理10分钟后,盖在界面修饰层5上;在微通道凹槽6中通入导金银纳米粒子制备的金墨水,完成源电极和漏电极的制备。 Select an insulating glass sheet as the substrate 1; after 10 minutes of UVO 3 treatment, spin-coat the poly-3,4-ethylenedioxythiophene solution on the substrate 1 at a speed of 2000rpm for 30s to form a 200nm Thick poly-3,4-ethylenedioxythiophene gate electrode layer 2; spin-coat the PVP solution on the prepared gate electrode layer 2 by spin-coating method, the rotation speed is 4000RPM, the time is 30S, and then the insulating glass The sheet is placed on a hot stage and heated and annealed at 200°C for 1 hour to prepare a gate dielectric layer 3 with a thickness of 600nm; P3HT is prepared as a semiconductor active material on the PVP gate dielectric layer 3 by piezoelectric inkjet printing technology; Select a single nozzle, print a single layer of P3HT layer under the conditions of 35V voltage and 40μm dot spacing, and print according to the vertical arrangement to form a 60nm thick semiconductor active layer 4. Annealing at a temperature of 70°C for 1 hour; molybdenum trioxide was vapor-deposited on the P3HT semiconductor active layer 4 by vacuum thermal evaporation to form a 40nm thick interface modification layer 5; the microchannel model designed according to the software was subjected to soft light Engraving technology, prepared a flexible PDMS source-drain microchannel layer 7 with microchannel grooves 6, and then treated the side of PDMS with microchannel grooves 6 for 10 minutes with ultraviolet and ozone, and then covered it on the interface modification layer 5; The gold ink prepared by conducting gold and silver nanoparticles is passed into the channel groove 6 to complete the preparation of the source electrode and the drain electrode.
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
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Application publication date: 20141217 |