CN104241386B - Power MOSFT (metal-oxide -semiconductor field effect transistor) device with low specific on-resistance and manufacturing method of power MOSFT device - Google Patents

Abstract

The invention relates to a power MOSFET with low characteristic on-resistance and a manufacturing method thereof. The element area includes first grooves and second grooves; The depth of the groove in the drift layer of the first conductivity type does not exceed the depth of the first trench in the drift layer of the first conductivity type; the first trench covered with the insulating oxide layer is filled with the first conductive polysilicon; The second trench of the insulating gate oxide layer is filled with second conductive polysilicon; the first conductive type implantation region is set on both sides outside the notch of the second trench; the notch of the second trench is covered with an insulating dielectric layer; the first The metal layer on the main surface is electrically connected to the injection region of the first conductivity type and the well layer of the second conductivity type under the first main surface at the same time. The invention has low on-resistance, small gate charging charge (Qg), simple manufacturing process and high reliability of the device.

Description

Power MOSFET device with low characteristic on-resistance and method of manufacturing the same

technical field

The invention relates to a power MOSFET and a manufacturing method thereof, in particular to a power MOSFET with low characteristic on-resistance and a manufacturing method thereof, belonging to the technical field of power semiconductor devices.

Background technique

The characteristic on-resistance (Rsp) is one of the most important indicators for evaluating the current conduction capability of a MOSFET device. Usually, the product of the characteristic on-resistance and the charge on the gate (Qg) or the charge on the gate-drain electrode (Qgd) (ie, Rsp *Qg or Rsp*Qgd) is used as the quality factor (FOM) of the device. The quality factor becomes the most direct and important technical indicator for judging the overall performance of a MOSFET product. The smaller the FOM, the lower the power loss of the device.

For 500V to 900V medium and high voltage MOSFET devices, the use of super junction technology (Super Junction) can effectively reduce the characteristic on-resistance of the device. The columnar region and the drift region form a P-N column pair that can deplete the withstand voltage horizontally, so that the resistivity of the drift region can be greatly reduced to reduce the characteristic on-resistance of the device under the condition of obtaining the same withstand voltage level. Super-junction power MOSFET devices have become the main device varieties in the 500V-900V voltage segment.

For medium and low voltage MOSFET devices within 200V, especially for low voltage MOSFET devices from 20V to 100V, since the proportion of the channel resistance of the device to the total on-resistance has increased significantly compared with that of medium and high voltage MOSFET devices, the traditional reduction The method of device characteristic on-resistance mainly revolves around how to increase the cell density of the device (Cell Density). It is reported that the smallest single cell pitch size is 0.6 μm. However, increasing the cell density can reduce the characteristic on-resistance , but at the same time it will greatly increase the gate-source charging charge (Qgs) and gate-drain charging charge (Qgd) of the device, which is not conducive to the application of the product in the high-frequency field, such as synchronous rectification.

In recent years, a new technology has been verified and promoted in the field of medium and low voltage MOSFET devices. This technology uses cells with a trench structure, and two parts of conductive polysilicon are arranged in the cell trenches. The two parts of conductive polysilicon are respectively The gate metal and the source metal of the device are connected, and are separated by an insulating oxide layer. The conductive polysilicon connected to the gate is located in the upper part of the trench, and the insulating gate oxide layer is between it and the side wall of the trench for forming The channel of the device, the conductive polysilicon connected to the source is located in the lower part of the trench, and there is a thicker insulating oxide layer between it and the sidewall and bottom of the trench, which is used for coupling in the drift region when the device is working with withstand voltage Charge, the coupled charge and the opposite type of doping impurities in the drift region are depleted to support the withstand voltage, similar to the super junction MOSFET device, the MOSFET device with this structure can greatly reduce the resistivity of the drift region, so as to obtain the same endurance The characteristic on-resistance of the device is reduced under the condition of voltage level. In the trench, the conductive polysilicon connected to the source can be completely located in the lower part of the trench, or partially located in the lower part of the trench, as shown in Figure 1 and Figure 2. In addition, because the lower part of the trench is filled with conductive polysilicon connected to the source, the overlapping area between the gate conductive polysilicon and the drift region connected to the drain is significantly reduced. Therefore, the Qgd of the MOSFET device is also Much smaller than the Qgd of common trench MOSFET devices.

However, although the structure of this low-voltage MOSFET device can effectively reduce the Rsp and Qgd of the device, it still has the following disadvantages:

1. Since the conductive polysilicon connected to the gate and the source is set in the cell trench at the same time, and is separated by a layer of insulating oxide layer, this structure device introduces this part of the gate-source capacitance ( Cgs), which increases the gate-source charging charge (Qgs) of the device, which is not conducive to reducing the driving loss and switching loss of the device.

2. Since the conductive polysilicon connected to the gate and the conductive polysilicon connected to the source in the cell trench are separated by an insulating oxide layer, the reliability of the isolation must be considered. In the actual manufacturing process, These two parts of conductive polysilicon need to undergo polycrystalline etching. It is difficult to make the appearance of polysilicon after etching smooth and tidy. There are usually some sharp corners or "V"-shaped shallow grooves. Therefore, after the growth of the insulating oxide layer It is also difficult to achieve a uniform and flat thickness, which brings a huge hidden danger to the reliability in the future. Facts have proved that this problem has become one of the main risk points of this type of structure.

3. Since two parts of conductive polysilicon isolated from each other are to be formed in the same trench, the process steps such as trench etching, thick oxide layer growth and corrosion, polysilicon deposition and etching often restrict each other. The window greatly increases the complexity of the process, which not only reduces the reliability of the product, but also increases the manufacturing cost.

4. Since the conductive polysilicon connected to the source is located in the lower half of the trench, and this part of the conductive polysilicon needs to be extracted and connected to the source, this structure also increases the design difficulty and window of the device, and will also increase to a certain extent Die area and manufacturing complexity of the device.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, and provide a power MOSFET device with low characteristic on-resistance and its manufacturing method, which has low on-resistance, small gate charging charge (Qg), and simple manufacturing process And the device has high reliability.

According to the technical solution provided by the present invention, the power MOSFET device with low characteristic on-resistance, on the top view plane of the MOSFET device, includes an element area and a terminal protection area located on the semiconductor substrate, and the element area is located on the semiconductor substrate The central area, the terminal protection area surrounds the surrounding element area; on the cross section of the MOSFET device, the semiconductor substrate has a first main surface and a second main surface corresponding to the first main surface, the first main surface and the second main surface The first conductivity type drift layer and the first conductivity type substrate layer located below the first conductivity type drift layer are included between the main surfaces, the first conductivity type substrate layer is adjacent to the first conductivity type drift layer, and the first conductivity type drift layer The surface of the first conductivity type substrate forms the first main surface, and the surface of the first conductivity type substrate forms the second main surface; a second conductivity type well layer is arranged on the upper part of the first conductivity type drift layer; its innovation lies in:

On the cross-section of the MOSFET device, the element region includes first trenches and second trenches; the first trenches and second trenches are alternately adjacent to each other, and the second trenches are in the drift layer of the first conductivity type The depth does not exceed the depth of the first trench in the drift layer of the first conductivity type;

On the cross-section of the MOSFET device, the first trench extends vertically downward from the first main surface of the semiconductor substrate, and is deep into the drift layer of the first conductivity type below the well layer of the second conductivity type; the inner wall of the first trench An insulating oxide layer is grown thereon, and the first trench covered with the insulating oxide layer is filled with first conductive polysilicon;

On the cross-section of the MOSFET device, the second trench extends vertically downward from the first main surface of the semiconductor substrate, and is deep into the drift layer of the first conductivity type below the well layer of the second conductivity type; the inner wall of the second trench An insulating gate oxide layer is grown on it, and the second trench covered with the insulating gate oxide layer is filled with second conductive polysilicon; implanted regions of the first conductivity type are provided on both sides outside the notch of the second trench, and the first conductive polysilicon The type injection region is in contact with the outer wall of the second trench; the notch of the second trench is covered with an insulating dielectric layer;

On the cross section of the MOSFET device, a first main surface metal layer is provided on the first main surface of the semiconductor substrate, and the first main surface metal layer is electrically connected to the first conductive polysilicon filled in the first trench, and the first main surface metal layer is electrically connected to the first conductive polysilicon filled in the first groove, A metal layer on the main surface is isolated from the second conductive polysilicon filled in the second trench through an insulating dielectric layer, and the metal layer on the first main surface is simultaneously connected to the implanted region of the first conductivity type and the well layer of the second conductivity type under the first main surface. electrical connection.

On the cross-section of the MOSFET device, the notch width of the first trench is greater than the notch width of the second trench; the distance between two adjacent first trenches is not greater than two adjacent second trenches The distance between slots.

The thickness of the insulating oxide layer in the first trench is greater than the thickness of the insulating gate oxide layer in the second trench.

The second main surface of the semiconductor substrate is covered with a second main surface metal layer, and the second main surface metal layer is electrically connected to the first conductivity type substrate layer.

A method for manufacturing a power MOSFET device with low characteristic on-resistance, the method for manufacturing the power MOSFET device comprises the steps of:

a. Provide a first conductivity type semiconductor substrate having two opposite main surfaces, the main surfaces include a first main surface and a second main surface corresponding to the first main surface, the first main surface and the second main surface including a substrate of the first conductivity type and a drift layer of the first conductivity type above the substrate of the first conductivity type;

b. A first hard mask layer is provided on the first main surface of the above-mentioned semiconductor substrate, and the first hard mask layer is selectively masked and etched to form a layer for etching on the first main surface of the semiconductor substrate. etching the first hard mask layer window to obtain the first trench;

c. Using the above-mentioned first hard mask layer window, the first main surface of the semiconductor substrate is etched by anisotropic dry method to obtain the required first groove in the semiconductor substrate, and the first groove is obtained from the semiconductor substrate. The first main surface of the substrate extends vertically downward, and the depth of the first groove does not exceed the thickness of the drift layer of the first conductivity type;

d. removing the first hard mask layer on the above-mentioned semiconductor substrate, and disposing a first insulating oxide layer body on the first main surface of the semiconductor substrate, the first insulating oxide layer body covering the first main surface of the semiconductor substrate, and the first insulating oxide layer body covers the inner wall of the first trench;

e. A first conductive polysilicon layer is disposed on the first main surface of the semiconductor substrate, the first conductive polysilicon layer is filled in the first trench and covers the first insulating oxide layer on the first main surface;

f. removing the first conductive polysilicon layer on the first main surface of the semiconductor substrate to obtain the first conductive polysilicon layer located in the first trench;

g. removing the first insulating oxide layer body on the first main surface of the semiconductor substrate to obtain the insulating oxide layer located in the first trench;

h. A second hard mask layer is provided on the first main surface of the above-mentioned semiconductor substrate, and the second hard mask layer is selectively masked and etched to form a etching the second hard mask layer window to obtain the second trench;

i. Using the second hard mask layer window, the first main surface of the semiconductor substrate is etched by anisotropic dry method to obtain the required second groove in the semiconductor substrate, and the second groove is formed from the semiconductor substrate The first main surface of the first groove extends vertically downward, and the depth of the second groove does not exceed the depth of the first groove;

j. Remove the second hard mask layer on the first main surface, and set a second insulating oxide layer body on the first main surface of the semiconductor substrate, and the insulating oxide layer body covers the first main surface of the semiconductor substrate , and cover the inner wall of the second groove;

k. A second conductive polysilicon layer is disposed on the first main surface of the above-mentioned semiconductor substrate, and the second conductive polysilicon layer covers the second insulating oxide layer body and fills in the second trench;

1. removing the second conductive polysilicon layer above the first main surface of the semiconductor substrate to obtain the second conductive polysilicon layer;

m. On the first main surface of the above-mentioned semiconductor substrate, self-aligned ions are implanted with impurity ions of the second conductivity type, and a well layer of the second conductivity type is formed on the upper part of the drift layer of the first conductivity type through high-temperature pushing junction, the second conductivity type The depth of the second conductivity type well layer in the first conductivity type drift layer is smaller than the depth of the second trench;

n. On the first main surface of the above-mentioned semiconductor substrate, perform photolithography of the source region, and implant high-concentration impurity ions of the first conductivity type, and form a first conductivity type implantation region by high-temperature pushing junction, and the first conductivity type The injection region is located outside the notch of the second groove, and the injection region of the first conductivity type is in contact with the outer wall of the second groove;

o. Arranging an insulating dielectric layer on the first main surface of the above-mentioned semiconductor substrate, and selectively etching the insulating dielectric layer to obtain an insulating dielectric layer covering the opening of the second trench; The second insulating oxide layer body on one main surface obtains an insulating gate oxide layer located in the second trench, and the insulating gate oxide layer is located between the second conductive polysilicon and the inner wall of the second trench;

p. Depositing a first main surface metal layer on the first main surface of the above-mentioned semiconductor substrate. The first conductive polysilicon is electrically connected;

q. Depositing a second main surface metal layer on the second main surface of the semiconductor substrate, where the second main surface metal layer is electrically connected to the first conductivity type substrate layer.

The thickness of the insulating oxide layer is 1000Å-10000Å.

The thickness of the insulating gate oxide layer is 100Å-150Å.

The first hard mask layer and the second hard mask layer are LPTEOS, thermally oxidized silicon dioxide plus chemical vapor deposition silicon dioxide or thermal silicon dioxide plus silicon nitride.

The insulating dielectric layer is silica glass (USG), borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG).

The notch width of the first groove is greater than the notch width of the second groove; the distance between two adjacent first grooves is not greater than the distance between two adjacent second grooves.

In both the "first conductivity type" and "second conductivity type", for N-type MOSFET devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type MOSFET devices, the first conductivity type The type referred to by the type and the second conductivity type is just opposite to the N-type semiconductor device.

Advantages of the present invention:

1. In the element area, it includes the first trench and the second trench, wherein the second trench contains the insulating gate oxide layer and the second conductive polysilicon connected to the gate electrode, and the function of the second trench is when the device is turned on. A conductive channel is formed, wherein the first trench includes a thicker insulating oxide layer and the first conductive polysilicon connected to the source electrode. The function of the first trench is to couple out and drift layer Carriers of the opposite type are doped to deplete the withstand voltage with the drift layer. Compared with the original structure where two parts of conductive polysilicon are arranged in one groove, by setting the first groove and the second groove, the overlapping part of the two parts of conductive polysilicon in the original structure is avoided, thereby eliminating this part The gate-source capacitance (Cgs) formed by the structure effectively reduces the switching loss and driving loss of the device.

2. Avoiding two parts of polysilicon in the same trench also solves the insulation isolation problem between the two parts of polysilicon in the original structure, greatly increasing the gate oxide withstand voltage quality of the device and the overall reliability of the device, making the product in progress The process window of gate oxide growth process, polysilicon deposition process and polysilicon etching process is larger, which obviously reduces manufacturing difficulty and cost.

3. Only the opening of the second trench is covered with an insulating dielectric layer, so when a covering metal layer is deposited on the first main surface of the element region, the metal layer can be directly electrically connected to the first conductive polysilicon in the first trench , instead of drawing out the first conductive polysilicon through other means, which can reduce the difficulty of layout design and increase the process window during manufacturing, which is more conducive to mass production of products.

Description of drawings

FIG. 1 is a schematic diagram of an implementation structure of an existing trench power MOSFET device.

FIG. 2 is a schematic diagram of another implementation structure of an existing trench power MOSFET device.

Fig. 3 is a top view of the power MOSFET device of the present invention.

Fig. 4 is a cross-sectional view of the power MOSFET element area of the present invention.

5 to 19 are cross-sectional views of specific implementation process steps of the power MOSFET device of the present invention, wherein

FIG. 5 is a cross-sectional view after obtaining the window of the first hard mask layer.

Fig. 6 is a cross-sectional view after obtaining the first trench.

Fig. 7 is a cross-sectional view after obtaining the first insulating oxide layer body.

Fig. 8 is a cross-sectional view after obtaining the first polysilicon layer.

FIG. 9 is a cross-sectional view after obtaining the first polysilicon.

Fig. 10 is a cross-sectional view after the insulating oxide layer is obtained.

FIG. 11 is a cross-sectional view after obtaining the window of the second hard mask layer.

Fig. 12 is a cross-sectional view after obtaining the second trench.

Fig. 13 is a cross-sectional view after obtaining the second polysilicon layer.

FIG. 14 is a cross-sectional view after obtaining the insulating gate oxide layer and the second polysilicon layer.

FIG. 15 is a cross-sectional view after obtaining the well region of the second conductivity type.

Fig. 16 is a cross-sectional view after obtaining the implantation region of the first conductivity type.

Fig. 17 is a cross-sectional view after obtaining an insulating dielectric layer.

Fig. 18 is a cross-sectional view after obtaining the metal layer on the first main surface.

Fig. 19 is a cross-sectional view after obtaining the second main surface metal layer.

Explanation of reference signs: 1-element area, 2-terminal protection area, 3-N-type drift layer, 4-N+substrate layer, 5-second main surface metal layer, 6-P-type well layer, 7-first trench Groove, 8-Second trench, 9-Insulation oxide layer, 10-First conductive polysilicon, 11-Insulation gate oxide layer, 12-Second conductive polysilicon, 13-N+ implantation region, 14-Insulation dielectric layer, 15- The first main surface metal layer, 16-the first hard mask layer, 17-the first hard mask layer window, 18-the first insulating oxide layer body, 19-the first polysilicon body, 20-the second hard mask Film layer, 21-second hard mask layer window, 22-second conductive polysilicon layer, 100-N type drift region, 101-N+ substrate region, 102-trench insulating oxide layer, 103-trench polysilicon, 104 -P-type well region, 105-N+ cell injection region, 106-trench insulating dielectric layer, 107-source metal, 108-source electrode, 109-gate electrode and 110-drain electrode.

detailed description

The present invention will be further described below in conjunction with specific drawings and embodiments.

As shown in Figure 1: It is the implementation structure diagram of the existing trench type power MOSFET device with low characteristic on-resistance, in which, on the cross section of the power MOSFET device, the element area of the power MOSFET device adopts a trench structure, and the cell The trench is located in the N-type drift region 100 , the depth of the cell trench is smaller than the thickness of the N-type drift region 100 , and the N-type drift region 100 is adjacent to the N+ substrate region 101 . A P-type well region 104 is provided in the upper part of the N-type drift region 100 , and the P-type well region 104 runs through the N-type drift region 100 . A trench insulating oxide layer 102 and a trench polysilicon 103 are arranged in the cell trench, and an N+ cell implantation region 105 is arranged outside the notch of the cell trench, and the N+ cell implantation region 105 is located in the P-type well region 104 , and the N+ cell implantation region 105 is in contact with the outer wall of the cell trench. The notch of the cell trench is provided with a trench insulating dielectric layer 106 , and the insulating dielectric layer 106 covers the notch of the cell trench and covers the N+ cell implantation regions 105 on both sides of the cell trench. A source metal 107 is provided above the N-type drift region 100 , and the source metal 107 is electrically connected to the P-type well region 104 and the N+ cell injection region 105 . A part of the trench polysilicon 103 in the cell trench can form a source electrode 108 through electrical connection with the source metal 103, and another part of the trench polysilicon 103 in the cell trench can form a gate electrode 109. In the N+ substrate region 101 The drain electrode 110 can be formed thereon. The conductive polysilicon used to form the source electrode 108 and the conductive polysilicon used to form the gate electrode 109 in the cell trench are insulated and isolated by a trench insulating oxide layer.

The structure in FIG. 2 is similar to that in FIG. 1 , except that the positions of the conductive polysilicon used to form the source electrode 108 and the conductive polysilicon used to form the gate electrode 109 in the cell trench are different. The disadvantages of the power MOSFETs with the implementation structures shown in Fig. 1 and Fig. 2 are as described above, and will not be repeated here.

As shown in Figure 3, Figure 4 and Figure 19, in order to make the on-resistance of the power MOSFET device low, the gate charging charge (Qg) is small, the manufacturing process is simple and the device has high reliability, an N-type power MOSFET device is taken as an example , the present invention includes an element area 1 and a terminal protection area 2 located on the semiconductor substrate on the top view plane of the MOSFET device, the element area 1 is located in the central area of the semiconductor substrate, and the terminal protection area 2 surrounds the element area 1; On the cross section of the MOSFET device, the semiconductor substrate has a first main surface and a second main surface corresponding to the first main surface, and an N-type drift layer 3 is included between the first main surface and the second main surface and is located on the The N-type substrate layer 4 below the N-type drift layer 3, the N-type substrate layer 4 is adjacent to the N-type drift layer 3, the surface of the N-type drift layer 3 forms the first main surface, and the surface of the N-type substrate 4 forms the second main surface. surface; a P-type well layer 6 is set in the upper part of the N drift layer 3;

On the cross section of the MOSFET device, the element region 1 includes first trenches 7 and second trenches 8; the first trenches 7 and the second trenches 8 are arranged alternately and adjacently, and the second trenches 8 are arranged in The depth in the N-type drift layer 3 does not exceed the depth of the first trench 7 in the N-type drift layer 3;

On the cross-section of the MOSFET device, the first groove 7 extends vertically downward from the first main surface of the semiconductor substrate, and is deep into the N-type drift layer 3 below the P-type well layer 6; the inner wall of the first groove 7 An insulating oxide layer 9 is grown thereon, and the first trench 7 covered with the insulating oxide layer 9 is filled with first conductive polysilicon 10;

On the cross-section of the MOSFET device, the second trench 8 extends vertically downward from the first main surface of the semiconductor substrate, and is deep into the N-type drift layer 3 below the P-type well layer 6; the inner wall of the second trench 8 An insulating gate oxide layer 11 is grown on it, and a second conductive polysilicon 12 is filled in the second trench 8 covered with the insulating gate oxide layer 11; N+ type implantation regions 13 are arranged on both sides outside the notch of the second trench 8 , the N+ implantation region 13 is in contact with the outer wall of the second trench 8; the notch of the second trench 8 is covered with an insulating dielectric layer 14;

On the cross section of the MOSFET device, a first main surface metal layer 15 is provided on the first main surface of the semiconductor substrate, and the first main surface metal layer 15 and the first conductive polysilicon 10 filled in the first trench 7 Electrically connected, the first main surface metal layer 15 is isolated from the second conductive polysilicon 12 filled in the second trench 8 through the insulating dielectric layer 14, and the first main surface metal layer 15 is simultaneously connected to the N+ implantation region 13 below the first main surface It is electrically connected with the P-type well layer 6 .

Specifically, the terminal protection area may adopt an existing common structure, as long as effective protection can be achieved. The depth of the second trench 8 in the N-type drift layer 3 does not exceed the depth of the first trench 7 in the N-type drift region 3 means that the depth of the second trench 8 in the N-type drift layer 3 is less than or equal to The depth of the first trench 7 in the N-type drift region 3 . Both the first trench 7 and the second trench 8 pass through the P-type well layer 6, and the bottom of the first trench 7 and the bottom of the second trench 8 are all located below the P-type well layer 6. Layer 6 runs through N-type drift region 3 located in element region 1 .

On the section of the MOSFET device, the notch width of the first trench 7 is greater than the notch width of the second trench 8; the distance between two adjacent first trenches 7 is not greater than two adjacent The distance between the second grooves 8 . The distance between two adjacent first grooves 7 is less than or equal to the distance between two adjacent second grooves 8 .

The thickness of the insulating oxide layer 9 in the first trench 7 is greater than the thickness of the insulating gate oxide layer 11 in the second trench 8 . The second main surface of the semiconductor substrate is covered with a second main surface metal layer 5 , and the second main surface metal layer 5 is electrically connected to the N-type substrate layer 4 .

As shown in Figures 5 to 19, the above-mentioned power MOSFET device with low characteristic on-resistance can be prepared by the following process, and the manufacturing method includes the following steps:

a. Provide an N-type semiconductor substrate with two opposite main surfaces, the main surface includes a first main surface and a second main surface corresponding to the first main surface, and the first main surface and the second main surface include An N-type substrate layer 4 and an N-type drift layer 3 located above the N-type substrate layer 4;

The material of the semiconductor substrate can be silicon or other semiconductor materials. The surface of the N-type drift layer 3 is used to form the first main surface of the semiconductor substrate, the surface of the N-type substrate layer 4 is used to form the second main surface of the semiconductor substrate, and the first main surface and the second main surface are oppositely distributed.

b. A first hard mask layer 16 is provided on the first main surface of the above-mentioned semiconductor substrate, and the first hard mask layer 16 is selectively masked and etched to form a Obtain the first hard mask layer window 17 of the first trench 7 by etching;

As shown in FIG. 5 , the first hard mask layer 16 is LPTEOS, thermally oxidized silicon dioxide plus chemical vapor deposited silicon dioxide, or thermal silicon dioxide plus silicon nitride. The first hard mask layer window 17 penetrates the first hard mask layer 16, and the first main surface of the semiconductor substrate can be exposed through the first hard mask layer window 17, and the first hard mask layer outside the first hard mask layer window 17 The mask layer 16 covers the first main surface of the semiconductor substrate, and can shield and protect the covered first main surface.

c. Using the above-mentioned first hard mask layer window 17, the first main surface of the semiconductor substrate is etched by anisotropic dry method to obtain the required first trench 7 in the semiconductor substrate, the first trench 7 extending vertically downward from the first main surface of the semiconductor substrate, and the depth of the first trench 7 does not exceed the thickness of the N-type drift layer 3;

As shown in FIG. 6, since the first main surface corresponding to the first hard mask layer window 17 is exposed, the first trench 7 can be obtained after anisotropic dry etching of the first main surface of the semiconductor substrate. , the notch width of the first trench 7 corresponds to the first hard mask layer window 17, the depth of the first trench 7 can be selected according to needs, but the depth of the first trench 7 cannot exceed the N-type drift layer 3 , that is, the bottom of the first trench 7 should be located in the N-type drift region 3 .

d. Remove the first hard mask layer 16 on the above-mentioned semiconductor substrate, and set a first insulating oxide layer body 18 on the first main surface of the semiconductor substrate, and the first insulating oxide layer body 18 covers the first surface of the semiconductor substrate. main surface, and the first insulating oxide layer body 18 covers the inner wall of the first trench 7;

As shown in FIG. 7 , the first hard mask layer 16 is etched and removed by using the existing common semiconductor process. After the first hard mask layer 16 is removed, the first hard mask layer 16 is grown on the first main surface of the semiconductor substrate. The insulating oxide layer body 18 and the first insulating oxide layer body 18 can generally be silicon dioxide, and the thickness of the first insulating oxide layer body 18 is 1000Ř10000Å. The first insulating oxide layer body 18 will grow and cover the first main surface and the inner wall of the first trench 7 at the same time, and the first insulating oxide layer body 18 located on the inner wall of the first trench 7 can be used to form the required insulation. Oxide layer 9.

e. A first conductive polysilicon layer 19 is provided on the first main surface of the above-mentioned semiconductor substrate, and the first conductive polysilicon layer 19 is filled in the first trench 7 and covers the first insulating oxide layer body on the first main surface 18 on;

As shown in FIG. 8, due to the existence of the first insulating oxide layer body 18, when depositing and filling conductive polysilicon, the first insulating oxide layer body 18 and the first trench 7 on the first main surface will inevitably obtain the first insulating oxide layer body 18. A conductive polysilicon layer 19 can be used to form the first conductive polysilicon layer 10 through the first conductive polysilicon layer 19 .

f. removing the first conductive polysilicon layer 19 on the first main surface of the semiconductor substrate to obtain the first conductive polysilicon layer 10 located in the first trench 7;

As shown in FIG. 9, the first conductive polysilicon layer 19 on the first insulating oxide layer body 18 is removed by dry etching, and the conductive polysilicon layer located in the first trench 7 is retained to obtain the conductive polysilicon layer located in the first trench 7. The first conductive polysilicon 10 .

g. removing the first insulating oxide layer body 18 on the first main surface of the semiconductor substrate to obtain the insulating oxide layer 9 located in the first trench 7;

As shown in FIG. 10, wet etching or dry etching is used to remove the first insulating oxide layer 18 on the first main surface, while retaining the first insulating oxide layer 18 on the inner wall of the first trench 7 to obtain coverage. The insulating oxide layer 9 on the inner wall of the first trench 7 has the same thickness as the first insulating oxide layer 18 .

h. A second hard mask layer 20 is provided on the first main surface of the above-mentioned semiconductor substrate, and the second hard mask layer 20 is selectively masked and etched to form a Obtain the second hard mask layer window 21 of the second trench 8 by etching;

As shown in FIG. 11, the window 21 of the second hard mask layer penetrates the second hard mask layer 20, and the material selection of the second hard mask layer 20 can be consistent with that of the first hard mask layer 16. Through the second hard mask layer The layer window 21 can expose a corresponding region of the first main surface.

i. Using the second hard mask layer window 21, the first main surface of the semiconductor substrate is etched by anisotropic dry method to obtain the required second trench 8 in the semiconductor substrate, the second trench 8 extending vertically downward from the first main surface of the semiconductor substrate, and the depth of the second trench 8 does not exceed the depth of the first trench 7;

As shown in Figure 12, the width of the notch of the second trench 8 corresponds to the window 21 of the second hard mask layer, and the depth of the second trench 8 does not exceed the depth of the first trench 7, that is, the second trench 8. The bottom of the groove is above the bottom of the first groove 7 , or the bottom of the second groove 8 is on the same level as the bottom of the first groove 7 . On the cross section, the first grooves 7 and the second grooves 8 are distributed alternately.

j. Remove the second hard mask layer 20 on the first main surface, and set a second insulating oxide layer body on the first main surface of the semiconductor substrate, and the second insulating oxide layer body covers the second insulating oxide layer body of the semiconductor substrate. a main surface, and cover the inner wall of the second groove 8;

The method for removing the second hard mask layer 20 is consistent with the method for removing the first hard mask layer 16. The second insulating oxide layer body is generally also a carbon dioxide layer, and the second insulating oxide layer body is mainly used to form an insulating gate oxide layer. 11. After forming the second insulating oxide layer body, the second insulating oxide layer body covers the first main surface, the first conductive polysilicon 10 , the insulating oxide layer 9 and the inner wall of the second trench 8 .

k. A second conductive polysilicon layer 22 is arranged on the first main surface of the above-mentioned semiconductor substrate, and the second conductive polysilicon layer 22 covers the second insulating oxide layer body and fills in the second trench 8;

As shown in Figure 13, the second conductive polysilicon layer 22 is mainly used to form the second conductive polysilicon 12 in the second trench 8; after depositing and filling the second conductive polysilicon layer 22 on the first main surface of the semiconductor substrate, the second The second conductive polysilicon layer 22 covers the second insulating oxide layer and fills the second trench 8 .

1. Removing the second conductive polysilicon layer 22 above the first main surface of the semiconductor substrate to obtain the second conductive polysilicon layer 12;

As shown in FIG. 14 , the second conductive polysilicon layer 22 on the second insulating oxide layer body is removed, and the conductive polysilicon in the second trench 8 remains, so as to obtain the second conductive polysilicon 12 in the second trench 8 .

m. On the first main surface of the above-mentioned semiconductor substrate, self-aligned ions are implanted with P-type impurity ions, and a P-type well layer 6 located on the upper part of the N-type drift layer 3 is formed by high-temperature push junction, and the P-type well layer 6 The depth of the N-type drift layer 3 is less than the depth of the second trench 8;

As shown in Figure 15, the depth of the P-type well layer 6 in the N-type drift layer 3 is smaller than the depth of the second trench 8, that is, it is ensured that the P-type well layer 6 is located above the bottom of the second trench 8, that is, it can be guaranteed The P-type well layer 6 is located above the bottom of the first trench 7 . After the P-type well layer 6 is formed, the P-type well layer 6 penetrates the N-type drift layer 3 , and in the cross section, the first trench 7 and the second trench 8 both pass through the P-type well layer 6 . In the embodiment of the present invention, the temperature of the high-temperature pushing junction is generally 900° C. to 1200° C.

n. On the first main surface of the above-mentioned semiconductor substrate, perform source region photolithography, and implant high-concentration N-type impurity ions, and form an N+ implantation region 13 by high-temperature pushing junction, and the N+ implantation region 13 is located in the second trench On the outside of the notch of the groove 8, the N+ implantation region 13 is in contact with the outer wall of the second groove 8;

As shown in FIG. 16, the concentration of the N+ implantation region 13 is higher than the concentration of the N-type drift layer 3, the N+ implantation region 13 is located in the P-type well layer 6, and the N+ implantation region 13 also extends vertically downward from the first main surface, And less than the thickness of the P-type well layer 6 , the N+ implantation region 13 is only in contact with the outer wall of the second trench 8 . In the embodiment of the present invention, the ion implantation concentration is generally 5E14-1E16, and the temperature is generally 800°C-1100°C.

o. Arranging an insulating dielectric layer on the first main surface of the above-mentioned semiconductor substrate, and selectively etching the insulating dielectric layer to obtain an insulating dielectric layer 14 covering the notch of the second trench 8; simultaneously removing the semiconductor The second insulating oxide layer body on the first main surface of the substrate, the insulating gate oxide layer 11 located in the second trench 8 is obtained, and the insulating gate oxide layer 11 is located between the second conductive polysilicon 12 and the inner wall of the second trench 8 between;

As shown in FIG. 17 , specifically, the thickness of the insulating gate oxide layer is 100Ř150Å. The insulating dielectric layer is silica glass (USG), borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG). Depositing the insulating dielectric layer body on the first main surface is mainly used to form the insulating dielectric layer 14 . When the insulating dielectric layer body is selectively etched, the insulating dielectric layer body above the second notch 8 and near both sides of the notch is reserved, and a contact hole can be formed when the insulating dielectric layer body is removed. At the same time as the dielectric layer body, the second insulating oxide layer body covering the top of the first conductive polysilicon 10 in the first trench 7 can be removed. The formed insulating dielectric layer 14 will cover part of the N+ implantation region 13 . In specific implementation, the second insulating oxide layer body can also be removed after removing the second conductive polysilicon layer 22 , and the specific process can be selected according to needs, and will not be repeated here.

p. Depositing a first main surface metal layer 15 on the first main surface of the above-mentioned semiconductor substrate, the first main surface metal layer 15 is simultaneously connected with the P-type well layer 6, the N+ implantation region 13 and the first trench 7 The first conductive polysilicon electrical 10 is connected;

As shown in Figure 18, metal material is deposited on the first main surface to obtain the first main surface metal layer 15, the first main surface metal layer 15 is filled in the above-mentioned contact hole, and covers the insulating dielectric layer 14, the first On the main surface, the first main surface metal layer 15 is simultaneously connected to the P-type well layer 6 , the N+ implantation region 13 and the first conductive polysilicon circuit 10 in the first trench 7 . The metal layer 15 on the first main surface can be made of commonly used metal materials.

q. Depositing a second main surface metal layer 5 on the second main surface of the semiconductor substrate, the second main surface metal layer 5 is electrically connected to the N-type substrate layer 4 .

As shown in FIG. 19 , after the second main surface metal layer 5 is obtained by depositing metal material on the second main surface, the second main surface metal layer 5 is electrically connected to the N-type substrate layer 4 and can be used to form a drain electrode.

The working mechanism of the MOSFET device of the present invention is: the insulating gate oxide layer 11 inside the second trench 8, the second conductive polysilicon 12, the P-type well layer 6 and the N+ implantation region 13 outside the second trench 8 jointly form the MOS of the device. structure, the second conductive polysilicon 12 leads to the gate electrode connected to the device at the edge of the element region 1, and the P-type well layer 6 and the N+ injection region 13 are connected to the first main surface metal layer above it and lead out as the source electrode of the device, and the second main surface of the device The surface metal layer 5 is drawn out as the drain electrode.

When the device is in the conduction state, the MOS structure provides a conduction channel controlled by the gate electrode and forms a path for current flow. The first main surface metal layer 15 above the P-type well layer 6 and the N+ implantation region 13 is also connected to the first conductive polysilicon 10 in the first trench 7, and the first conductive polysilicon 10 is connected to the first trench The thick insulating oxide layer 9 on the inner wall of 7 and the N-type drift layer 3 on the outside of the first trench 7 form a capacitive field plate structure. When the device works in the cut-off withstand voltage state, the drain electrode of the device will apply a positive Voltage, at this time, the capacitive field plate structure will couple positive charges in the surrounding N-type drift layer 3, and the positive charges will form a depletion layer with the electrons in the N-type drift layer 3, with the drain As the electrode voltage rises, the depletion layer continues to expand around. When the depletion layers between two adjacent first trenches 7 are in contact with each other, a withstand voltage layer that withstands the drain voltage of the device will be established, thereby The drain voltage of the device is supported, and the drain voltage of the device is borne by the depletion layer formed by the P-type well layer 6 and the N-type drift layer 3 before the above-mentioned depletion layers are contacted together.

Due to the introduction of the first trench 7 and the capacitive field plate structure formed by it, the device adds charge coupling out of the N-type drift layer 3 on the basis of the original P-well-N-type epitaxial layer withstand voltage structure. In the withstand voltage layer, the distribution of the electric field in the withstand voltage layer changes from the original triangular structure to the trapezoidal structure, and the withstand voltage capability of the device is greatly increased. On the other hand, if the original withstand voltage requirement of the device is to be maintained, then the N of the device The resistivity of the type drift layer 3 can be significantly reduced, thereby effectively reducing the on-resistance of the device.

In the embodiment of the present invention, the first trench 7 and the second trench 8 are independent of each other, so that there is no intersection between the second conductive polysilicon 12 connected to the gate and the first conductive polysilicon 10 connected to the source in the original structure. In this case, the device gate-source charge (Qgs) introduced by this part of the structure is removed, the gate charge charge (Qg) of the device is significantly reduced, and the switching characteristics of the device are improved; at the same time, two parts of conductive polysilicon are avoided. In the same trench, the insulation and isolation problem between the two parts of the polysilicon in the original structure is also solved, which greatly increases the gate oxide withstand voltage quality of the device and the overall reliability of the device, making the product process of gate oxide growth, polysilicon deposition The process window of the deposition process and the polysilicon etching process is larger, which effectively reduces the manufacturing cost of the device and improves the reliability of the device.

Claims (2)

1. a kind of power mosfet device with low specific on-resistance, in the top plan view of described mosfet device, bag Include the element region positioned at semiconductor substrate and terminal protection area, described element region is located at the center of semiconductor substrate, terminal is protected Shield area is around embracing element area；On the section of described mosfet device, semiconductor substrate have the first interarea and with described The second corresponding interarea of first interarea, includes the first conduction type drift layer and is located at institute between the first interarea and the second interarea State the first conductivity type substrate layer below the first conduction type drift layer, the first conductivity type substrate layer and the first conduction type Drift layer adjoins, and the surface of the first conduction type drift layer forms the first interarea, and the surface of the first conductivity type substrate forms the Two interareas；On the first conduction type drift in the layer top, the second conduction type well layer is set；It is characterized in that:

On the section of described mosfet device, described element region includes first groove and second groove；First groove and second Groove is alternately disposed adjacent, and it is conductive first that second groove is less than first groove in the first conduction type drift in the layer depth Type drift in the layer depth；

On the section of described mosfet device, first groove is extended vertically downward by the first interarea of semiconductor substrate, depth In the first conduction type drift layer to the second conduction type well layer；The grown on interior walls of first groove is coated with insulation oxygen Change layer, in the described first groove being coated with insulating oxide, be filled with the first conductive polycrystalline silicon；

On the section of described mosfet device, the first interarea that second groove has semiconductor substrate extends vertically downward, depth In the first conduction type drift layer to the second conduction type well layer；The grown on interior walls of second groove is coated with insulated gate Oxide layer, is filled with the second conductive polycrystalline silicon in the second groove being coated with insulation gate oxide；Outside second groove notch Both sides arrange the first conductivity type implanted region, the first conductivity type implanted region is contacted with the outer wall of second groove；Second ditch It is coated with insulating medium layer on the notch of groove；

On the section of described mosfet device, the first interarea of semiconductor substrate is provided with the first interarea metal level, described First interarea metal level is electrically connected with the first conductive polycrystalline silicon of filling in first groove, and the first interarea metal level is situated between by insulation Second conductive polycrystalline silicon isolation of filling in matter layer and second groove, the first interarea metal level simultaneously with the first interarea below the One conductivity type implanted region and the electrical connection of the second conduction type well layer；

On the section of described mosfet device, the width of rebate of described first groove is more than the width of rebate of second groove；Two The distance between individual adjacent first trenches are not more than the distance between two adjacent second grooves；

The thickness of the insulating oxide in described first groove is more than the thickness of second groove interior insulation gate oxide；

Second interarea metal level, the second interarea metal level and the first conductive-type are coated with the second interarea of described semiconductor substrate Type substrate layer electrically connects.

2. a kind of manufacture method of the power mosfet device with low specific on-resistance, is characterized in that, described power The manufacture method of mosfet device comprises the steps:

(a), provide there is the first conductive type semiconductor substrate of two opposing main faces, described interarea include the first interarea and Second interarea corresponding with described first interarea, includes the first conductivity type substrate and position between the first interarea and the second interarea The first conduction type drift layer above described first conductivity type substrate；

(b), the first hard mask layer is arranged on the first interarea of above-mentioned semiconductor substrate, optionally shelter and etch described One hard mask layer, to form the first hard mask layer obtaining first groove for etching above the first interarea of semiconductor substrate Window；

(c), utilize above-mentioned first hard mask layer window, by the first interarea of anisotropic dry etch semiconductor substrate, with Obtain required first groove in semiconductor substrate, described first groove is prolonged vertically downward from the first interarea of semiconductor substrate Stretch, and the depth of first groove is less than the thickness of the first conduction type drift layer；

(d), the first hard mask layer removing on above-mentioned semiconductor substrate, and arrange first on the first interarea of semiconductor substrate Insulating oxide body, described first insulating oxide body covers the first interarea of semiconductor substrate, and the first insulating oxide body Cover the inwall of first groove；

(e), the first conductive polycrystalline silicon floor, described first conductive polycrystalline silicon floor are arranged on the first interarea of above-mentioned semiconductor substrate It is filled in first groove and cover on the first insulating oxide body of the first interarea；

F (), the first conductive polycrystalline silicon floor removing on above-mentioned semiconductor substrate first interarea, to obtain in first groove First conductive polycrystalline silicon；

G (), the first insulating oxide body removing on above-mentioned semiconductor substrate first interarea, to obtain in first groove Insulating oxide；

(h), the second hard mask layer is arranged on the first interarea of above-mentioned semiconductor substrate, optionally shelter and etch described Two hard mask layers, to form the second hard mask layer obtaining second groove for etching above the first interarea of semiconductor substrate Window；

(i), utilize the second hard mask layer window, by the first interarea of anisotropic dry etch semiconductor substrate, with partly Required second groove is obtained, described second groove extends vertically downward from the first interarea of semiconductor substrate in conductor substrate, And the depth of second groove is less than the depth of first groove；

(j), the second hard mask layer removing on above-mentioned first interarea, and setting second is exhausted on the first interarea of semiconductor substrate Edge oxide layer body, described insulating oxide body covers the first interarea in semiconductor substrate, and covers the inwall in second groove；

(k), the second conductive polycrystalline silicon floor, described second conductive polycrystalline silicon floor are arranged on the first interarea of above-mentioned semiconductor substrate Cover in the second insulating oxide body and be filled in second groove；

L the second conductive polycrystalline silicon floor above (), above-mentioned semiconductor substrate first interarea of removal is conductive many positioned at second to obtain Crystal silicon；

(m), on the first interarea of above-mentioned semiconductor substrate, autoregistration ion implanting the second conductive type impurity ion, and lead to Cross high temperature knot and form the second conduction type well layer being located at the first conduction type drift layer top, described second conductive type of trap Layer the first conduction type drift layer depth be less than second groove depth；

(n), on the first interarea of above-mentioned semiconductor substrate, carry out source region photoetching, and inject the first conduction type of high concentration Foreign ion, and the first conductivity type implanted region is formed by high temperature knot, described first conductivity type implanted region is located at second The outside of groove notch, the first conductivity type implanted region is contacted with the outer wall of second groove；

(o), insulating medium layer body is set on the first interarea of above-mentioned semiconductor substrate, and optionally etches described insulation and be situated between Matter layer body, to obtain covering the insulating medium layer of second groove notch；Remove second on semiconductor substrate first interarea simultaneously Insulating oxide body, obtains the insulation gate oxide in second groove, and it is conductive many that described insulation gate oxide is located at second Between the inwall of crystal silicon and second groove；

(p), the first interarea metal level is deposited on the first interarea of above-mentioned semiconductor substrate, described first interarea metal level is simultaneously Electrically connect with the first conductive polycrystalline silicon in the second conduction type well layer, the first conductivity type implanted region and first groove；

(q), the second interarea metal level, the second interarea metal level and the first conductive-type are deposited on the second interarea of semiconductor substrate Type substrate layer electrically connects；

The thickness of described insulating oxide is 1000 à ~ 10000 à；

The thickness of described insulation gate oxide is 100 à ~ 150 à

Described first hard mask layer, the second hard mask layer are lpteos, thermal oxide silicon dioxide adds chemical vapor deposition titanium dioxide Silicon or thermal silicon dioxide add silicon nitride；

Described insulating medium layer is silica glass (usg), boron-phosphorosilicate glass (bpsg) or phosphorosilicate glass (psg)；

The width of rebate of described first groove is more than the width of rebate of second groove；The distance between two adjacent first trenches are no More than the distance between two adjacent second grooves.