CN104252425B - The management method and processor of a kind of instruction buffer - Google Patents

Abstract

Embodiments of the present invention provide an instruction cache management method and a processor, which can expand the instruction cache capacity of hardware threads, reduce the missing rate of instruction cache, and improve system performance in the actual computer field. The hardware thread identifier in the shared instruction cache of the processor is used to identify the hardware thread corresponding to the cache line in the shared instruction cache, and the private instruction cache is used to store the instruction cache line replaced from the shared instruction cache, and also includes the missing cache, When the hardware thread of the processor acquires instructions from the instruction cache, it simultaneously accesses the shared instruction cache in the instruction cache and the private instruction cache corresponding to the hardware thread, determines whether there are instructions in the shared instruction cache and the private instruction cache corresponding to the hardware thread, and According to the judgment result, the instruction is obtained from the shared instruction cache or the private instruction cache corresponding to the hardware thread. The embodiment of the present invention is used for managing the instruction cache of the processor.

Description

A kind of management method and processor of instruction cache

technical field

The invention relates to the field of computers, in particular to an instruction cache management method and a processor.

Background technique

CPU (Central Processing Unit, central processing unit) cache (Cache Memory) is a temporary storage located between the CPU and the memory, and its capacity is much smaller than that of the memory. CPU read speed.

In a multi-threaded processor, multiple hardware threads obtain instructions from the same I-Cache (instruction cache). When there is no instruction to be obtained in the I-Cache, while sending a missing request to the next-level Cache, Switching to other hardware threads to access the I-Cache continues to fetch instructions, reducing the pause of the pipeline caused by the lack of I-Cache and improving the efficiency of the pipeline. However, when the shared I-Cache resources assigned to each hardware thread are insufficient, the I-Cache miss rate increases, and the missing requests sent from the I-Cache to the next-level Cache will occur frequently, and instructions will be retrieved from the next-level Cache. When backfilling, when the thread data increases, the Cache line where the filled instruction is located will be immediately filled into the missing I-Cache and will not be used immediately, and the replaced Cache line may be used again instead.

In addition, when adjusting the scheduling strategy of Thread (thread) according to the Cache hit situation, it will try to ensure that the thread with a high hit rate of memory access instructions in the Cache is prioritized for a period of time, but for the shared I allocated to each hardware thread -The problem of insufficient Cache resources has not been improved.

Contents of the invention

Embodiments of the present invention provide an instruction cache management method and a processor, which can expand the instruction cache capacity of hardware threads, reduce the missing rate of the instruction cache, and improve system performance.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions

In the first aspect, a processor is provided, which is characterized in that it includes a program counter, a register file, an instruction prefetch unit, an instruction decoding unit, an instruction issuing unit, an address generation unit, an arithmetic logic unit, a shared floating point unit, and a data cache and the internal bus, also includes:

The shared instruction cache is used to store shared instructions of all hardware threads, including a tag storage array and a data storage array, the tag storage array is used to store tags, the data storage array includes stored instructions and hardware thread identifiers, and the hardware The thread identifier is used to identify the hardware thread corresponding to the cache line in the shared instruction cache;

A private instruction cache, configured to store instruction cache lines replaced from the shared instruction cache, where the private instruction cache corresponds to the hardware threads one by one;

The miss cache is used to save the cache line retrieved from the next-level cache of the shared instruction cache in the miss cache of the hardware thread when the fetched instruction does not exist in the shared instruction cache. When the hardware thread corresponding to the fetched instruction fetches an instruction, the cache line in the miss register is backfilled into the shared instruction cache, and the miss buffer corresponds to the hardware thread one by one.

In combination with the first aspect, in the first possible implementation manner of the first aspect, it also includes:

Tag comparison logic, used to compare the tag in the private instruction cache corresponding to the hardware thread with the physical address converted by the translation lookaside buffer when the hardware thread fetches instructions, and compare the private instruction cache with the tag The comparison logic is connected so that the hardware thread accesses the private instruction cache while accessing the shared instruction cache.

With reference to the first possible implementation manner of the first aspect, in the second possible implementation manner, the processor is a multi-threaded processor, the structure of the private instruction cache is a fully associative structure, and the fully associative The associative structure maps any instruction cache in the main memory to any instruction cache in the private instruction cache.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the shared instruction cache, the private instruction cache, and the miss cache are static memory chips or dynamic memory chips.

In a second aspect, a method for managing an instruction cache is provided, including:

When the hardware thread of the processor acquires the instruction from the instruction cache, simultaneously access the shared instruction cache in the instruction cache and the private instruction cache corresponding to the hardware thread;

Determining whether the instruction exists in the shared instruction cache and the private instruction cache corresponding to the hardware thread, and acquiring the instruction from the shared instruction cache or the private instruction cache corresponding to the hardware thread according to a judgment result.

With reference to the second aspect, in the first possible implementation manner of the second aspect, the shared instruction cache includes a tag storage array and a data storage array, the tag storage array is used to store tags, and the data storage array includes a storage An instruction and a hardware thread identifier, where the hardware thread identifier is used to identify the hardware thread corresponding to the cache line in the shared instruction cache;

The structure of the private instruction cache is a fully associative structure, and the fully associative structure maps any instruction cache in the private instruction cache to any instruction cache in the main memory, and the private instruction cache is connected to the hardware Threads correspond one-to-one.

With reference to the first possible implementation manner of the second aspect, in the second possible implementation manner, the determining whether the instruction exists in the shared instruction cache and the private instruction cache corresponding to the hardware thread, and according to the judgment As a result, obtaining the instruction from the shared instruction cache or the private instruction cache corresponding to the hardware thread includes:

If the instruction exists in both the shared instruction cache and the private instruction cache corresponding to the hardware thread, obtain the instruction from the shared instruction cache;

If the instruction exists in the shared instruction cache and the instruction does not exist in the private instruction cache corresponding to the hardware thread, then obtain the instruction from the shared instruction cache;

If the instruction exists in the private instruction cache corresponding to the hardware thread and the instruction does not exist in the shared instruction cache, acquire the instruction from the private instruction cache corresponding to the hardware thread.

With reference to the second possible implementation manner of the second aspect, in a third possible implementation manner, the method further includes:

If the instruction does not exist in the shared instruction cache and the private instruction cache, a cache miss request is sent to a next-level cache of the shared instruction cache through the hardware thread,

If the instruction exists in the next-level cache, the instruction is obtained from the next-level cache through the hardware thread, and the cache line where the instruction is located is stored in the miss corresponding to the hardware thread In the cache, when the hardware thread fetches an instruction, backfill the cache line into the shared instruction cache;

If the instruction does not exist in the next-level cache, send the missing request to the main memory through the hardware thread, obtain the instruction from the main memory, and store the cache line where the instruction is located In the missing cache corresponding to the hardware thread, when the hardware thread fetches an instruction, backfill the cache line into the shared instruction cache;

Wherein, the missing cache is in one-to-one correspondence with the hardware threads.

With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner, when backfilling the cache line into the shared instruction cache, if there is no idle resource in the shared instruction cache, Then replace the cache line with the first cache line in the shared instruction cache, backfill the cache line into the shared instruction cache, and at the same time, according to the hardware thread of the first hardware thread that acquires the first cache line Identifying, storing the first cache line in a private instruction cache corresponding to the first hardware thread;

Wherein, the first cache line is determined by a least recently used algorithm.

With reference to the fourth possible implementation of the second aspect, in the fifth possible implementation, when storing the replaced first cache line in the private instruction cache corresponding to the first hardware thread, if If there is no idle resource in the private instruction cache corresponding to the first hardware thread, then replace the first cache line with the second cache line in the private instruction cache corresponding to the first hardware thread, and replace the first cache line backfilling into the private instruction cache corresponding to the first hardware thread;

Wherein, the second cache line is determined by the least recently used algorithm.

Embodiments of the present invention provide a method for managing an instruction cache and a processor. The processor includes a program counter, a register file, an instruction prefetching unit, an instruction decoding unit, an instruction issuing unit, an address generation unit, an arithmetic logic unit, and a shared floating point Units, data caches, and internal buses, as well as shared instruction caches, private instruction caches, miss caches, and tag comparison logic. Among them, the shared instruction cache is used to store shared instructions of all hardware threads, including a tag storage array and a data storage array, the data storage array includes stored instructions and hardware thread identifiers, and the hardware thread identifier is used to identify cache lines in the shared instruction cache The corresponding hardware thread, the private instruction cache, is used to store the instruction cache line replaced from the shared instruction cache, the private instruction cache corresponds to the hardware thread one by one, and the tag comparison logic is used to check the hardware The tag in the private instruction cache corresponding to the thread is compared with the physical address converted by the translation lookaside buffer. The private instruction cache is connected to the tag comparison logic, so that the hardware thread accesses the private instruction cache while accessing the shared instruction cache. When the processor's When the hardware thread obtains instructions from the instruction cache, it simultaneously accesses the shared instruction cache in the instruction cache and the private instruction cache corresponding to the hardware thread, determines whether there is an instruction in the shared instruction cache and the private instruction cache corresponding to the hardware thread, and according to the judgment result from Obtaining instructions from the shared instruction cache or the private instruction cache corresponding to the hardware thread can expand the instruction cache capacity of the hardware thread, reduce the miss rate of the instruction cache, and improve system performance.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a processor provided by an embodiment of the present invention;

FIG. 2 is a schematic flowchart of a method for managing an instruction cache provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of simultaneously accessing a shared instruction cache and a private instruction cache provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of retrieving a cache line according to a cache miss request according to an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the design of modern multi-threaded processors, as the number of hardware threads increases, there will be insufficient shared resources for each hardware thread. For example, for the important shared resource of L1 (Level 1) Cache in Cache Even more so with resources. The instruction cache capacity of the L1Cache assigned to each hardware thread is too small, there will be misses in the L1, and the L1 miss rate will increase, resulting in increased communication between the L1Cache and the L2Cache and fetching instructions from the L2Cache, or fetching instructions from the main memory. Processor power consumption increases.

An embodiment of the present invention provides a processor 01, as shown in FIG. 1 , including a program counter 011, a register file 012, an instruction prefetching unit 013, an instruction decoding unit 014, an instruction transmitting unit 015, an address generation unit 016, and an arithmetic logic Unit 017, shared floating point unit 018, data cache 019, and internal bus, also include:

Shared instruction cache (I-Cache) 020, private instruction cache 021, missing cache (Miss Buffer) 022 and tag (Tag) comparison logic 023.

Wherein, the shared instruction cache 020 is used to store shared instructions of all hardware threads, including a tag storage array (Tag Array) 0201 and a data storage array (Data Array) 0202, the tag storage array 0201 is used to store tags, and the data storage array 0202 includes The stored instruction 02021 and hardware thread identifier (Thread ID) 02022, the hardware thread identifier 02022 is used to identify the hardware thread corresponding to the cache line in the shared instruction cache 020.

The private instruction cache 021 is used to store the instruction cache lines replaced from the shared instruction cache 020, and the private instruction cache 021 corresponds to hardware threads one by one.

The missing cache 022 is used for caching the cache line retrieved from the next-level cache of the shared instruction cache 020 in the missing cache of the hardware thread when the fetched instruction does not exist in the shared instruction cache 020. When the corresponding hardware thread fetches an instruction, the cache line in the missing cache 022 is backfilled into the shared instruction cache, and the missing cache 022 corresponds to the hardware thread one by one.

Tag comparison logic is used to compare the tag in the private instruction cache corresponding to the hardware thread with the PA (PhysisAdress) converted by the TLB (Translation Look-aside Buffers) when the hardware thread fetches instructions. The cache 021 is connected with tag comparison logic, so that hardware threads access the private instruction cache 021 while accessing the shared instruction cache 020 .

Among them, TLB or page table buffer, which stores some page table files (virtual address to physical address conversion table, can convert the virtual address of the fetched instruction into a physical address through TLB, and convert the physical address with the private instruction After the tag in the cache is compared, if the physical address is the same as the tag in the private instruction cache, the hardware thread accesses the private instruction cache while accessing the shared instruction cache.

For example, there are 16 PCs (Program Counter, program counter), which are PC0-PC15, and the number of logical processor cores (hardware threads) in one processor core is consistent with the number of PCs.

GRF (General Register File, register file), a logical processor core in a processor core corresponds to a GRF, and the number is consistent with the number of PCs.

Fetch (instruction prefetching unit) is used to obtain instructions, Decoder (instruction decoding unit) is used to decode instructions, Issue is an instruction emission unit, which is used to transmit instructions, and AGU (Address Generator Unit, address generation unit) is used to perform all The address calculation module generates an address for controlling access to memory. ALU (Arithmetic Logic Unit, arithmetic logic unit) is the execution unit of CPU (Central Processing Unit, central processing unit), which can be composed of "And Gate" (AND gate) and "Or Gate" (or gate). Shared Float Point Unit (Shared Float Point Unit) is a circuit unit specialized in floating-point arithmetic operations in the processor, the data cache (D-Cache) is used to store data, and the internal bus is used to connect various components in the processor.

For example, the processor 01 is a multi-threaded processor, and the structure of the private instruction cache 021 is a fully associative structure. The fully associative structure maps any instruction cache in the main memory to any instruction cache in the private instruction cache.

For example, the shared instruction cache 020 , the private instruction cache 021 and the miss cache 022 are static memory chips or dynamic memory chips.

For example, a Thread ID (hardware thread identification) can be added in the I-Cache Data Array (instruction cache data storage array), and the Thread ID is used to indicate which hardware thread the Cache Line is issued by. miss) request retrieved.

For example, when a hardware thread misses accessing the I-Cache of L1, that is, when there is no instruction in the I-Cache that the hardware thread wants to obtain, L1 sends a Cache Miss request to L2Cache, the next-level cache of L1. When there is an instruction to be obtained by the hardware thread, the hardware thread backfills the cache line (Cache Line) where the instruction is located in the L2Cache into the L1Cache, or when the hardware thread receives the returned Cache Line, it does not directly insert the The Cache Line is filled in the L1Cache, but the Cache Line is stored in the MissBuffer corresponding to the hardware thread, and the Cache Line is filled in the L1Cache until it is the turn of the hardware thread layer to fetch instructions.

In this way, when the hardware thread backfills the cache line where the instruction in the L2Cache is located into the L1Cache for replacement, the replaced Cache Line is not directly discarded, but can be replaced according to the Thread ID of the hardware thread corresponding to the replaced Cache Line. The removed Cache Line is filled into the private instruction cache corresponding to the hardware thread corresponding to the replaced Cache Line.

For example, the replacement may be caused by the absence of idle resources in the L1 Cache, and the replaced Cache Line may be obtained according to an LRU (Least Recently Used, least recently used) algorithm.

Among them, the LRU algorithm is to replace the instruction that has not been used for the longest time out of the cache once the instruction cache is missing. In other words, the cache first retains the most recently frequently used instructions.

For example, when a hardware thread fetches an instruction, it can simultaneously access the I-Cache and the private cache corresponding to the hardware thread.

If there is a fetched instruction in the I-Cache and the private Cache corresponding to the hardware thread does not have the fetched instruction, then obtain the fetched instruction from the I-Cache;

If there is no fetched instruction in the I-Cache and the private Cache corresponding to the hardware thread has the fetched instruction, then the fetched instruction exists from the private Cache corresponding to the hardware thread to obtain the fetched instruction;

If there are fetched instructions in the I-Cache and the private Cache corresponding to the hardware thread, the fetched instructions are obtained from the I-Cache;

If neither the I-Cache nor the private Cache corresponding to the hardware thread has the fetched instruction, the hardware thread sends a Cache Miss request to the next-level cache of the I-Cache to obtain the fetched instruction.

For example, according to the calling strategy of the hardware thread, when the next cycle is switched to another thread to fetch instructions, while accessing the shared instruction cache, the private Cache corresponding to the new hardware thread is connected to the Tag (tag) comparison logic, and the The Tag comparison logic read by the private Cache is compared with the PA (Physics Address, physical address) output by the TLB (Translation Look-aside Buffers, translation look-aside buffer) to generate a private Cache Miss signal and a private Cache data output. When the fetched instruction exists in the private Cache corresponding to the new hardware thread, the private Cache Miss signal indicates that the instruction exists, and the instruction is output.

Therefore, an embodiment of the present invention provides a processor, which includes a program counter, a register file, an instruction prefetch unit, an instruction decoding unit, an instruction issuing unit, an address generation unit, an arithmetic logic unit, a shared floating point unit, a data Cache and internal bus, including shared instruction cache, private instruction cache, missing cache and tag comparison logic, adding hardware thread identification in the data storage array of shared instruction cache, used to retrieve cache lines when the cache is missing. Which hardware thread sends a cache miss request to retrieve, when the shared instruction cache is replaced, the replaced cache line is stored in the private instruction cache corresponding to the corresponding hardware thread according to the hardware thread ID, and the missing cache is used for When the hardware thread receives the cache line returned by the cache miss request, it does not directly backfill the cache line into the shared instruction cache, but saves the cache line in the missing cache until it is the turn of the hardware thread to fetch the instruction, and the cache line is returned. Backfilling to the shared instruction cache reduces the probability of the instruction cache that is about to be accessed to the end of the cache line being replaced. In addition, the increased private instruction cache increases the cache capacity of each hardware thread and improves system performance.

Another embodiment of the present invention provides a method for managing an instruction cache, as shown in FIG. 2 , including:

101. When a hardware thread of a processor acquires an instruction from an instruction cache, the processor simultaneously accesses a shared instruction cache in the instruction cache and a private instruction cache corresponding to the hardware thread.

Exemplarily, the processor (Central Processing Unit, CPU) may be a multi-thread processor. A physical core can have multiple hardware threads, also known as logical cores or logical processors, but a hardware thread does not represent a physical core. Windows regards each hardware thread as a schedulable logical processor, each Logical processors can run code for software threads. The instruction cache may be a shared instruction cache (I-Cache) in the L1Cache in the processor and a private instruction cache of the hardware thread. Among them, L1Cache includes data cache (D-Cache) and instruction cache (I-Cache).

Specifically, a fully associative private Cache may be set in each hardware thread, that is, a private Cache corresponds to a hardware thread one by one. Wherein, the fully associative structure maps any instruction cache in the main memory to any instruction cache in the private instruction cache.

In addition, a Tag (label) comparison logic can also be added. When a hardware thread fetches an instruction, it actively connects the private Cache of the hardware thread with the Tag comparison logic. In this way, when a hardware thread fetches an instruction, it simultaneously accesses the I-Cache and the The private cache corresponding to the hardware thread.

102. The processor determines whether there is an instruction in the shared instruction cache and the private instruction cache corresponding to the hardware thread, and then enters step 103 or 104 or 105 or 106.

Exemplarily, when a hardware thread simultaneously accesses the I-Cache and the private Cache corresponding to the hardware thread, it is simultaneously judged whether there are fetched instructions in the I-Cache and the private Cache corresponding to the hardware thread.

If the multi-threaded processor has 32 hardware threads, the 32 hardware threads share a 64KB I-Cache, that is, the shared instruction cache capacity is 64KB. Each hardware thread contains a 32-way fully associative private Cache, which can store 32 replaced Cache Lines (cache lines). Each Cache Line contains 64Bytes. In this way, the capacity of each private Cache is 2KB.

When a 32-way Tag comparison logic is added, the hardware thread compares the 32-way Tag read by the hardware thread with the PA (Physics Address, physical address) output by the TLB while accessing the I-Cache shared instruction cache, and Generate private Cache Miss signal and private Cache data output. If the 32-way Tag is the same as the PA, the private Cache Miss signal indicates that the private Cache of the hardware thread has the fetched instruction, and the private Cache data is a valid instruction. As shown in Figure 3.

Among them, TLB or page table buffer, which stores some page table files (virtual address to physical address conversion table, can convert the virtual address of the fetched instruction into a physical address through TLB, and convert the physical address with the private instruction After the tag in the cache is compared, if the physical address is the same as the tag in the private instruction cache, the hardware thread accesses the private instruction cache while accessing the shared instruction cache.

103. If instructions exist in both the shared instruction cache and the private instruction cache corresponding to the hardware thread, the processor acquires the instruction from the shared instruction cache.

Exemplarily, when accessing the I-Cache and the private Cache at the same time, if the I-Cache and the private Cache both have fetched instructions, the instructions are fetched from the I-Cache.

104. If there is an instruction in the shared instruction cache and no instruction exists in the private instruction cache corresponding to the hardware thread, the processor acquires the instruction from the shared instruction cache.

Exemplarily, if the fetched instruction exists in the I-Cache, but the fetched instruction does not exist in the private Cache of the hardware thread, then the fetched instruction exists in the I-Cache.

105. If there is an instruction in the private instruction cache corresponding to the hardware thread and no instruction exists in the shared instruction cache, the processor acquires the instruction from the private instruction cache corresponding to the hardware thread.

Exemplarily, if there is a miss in the I-Cache, that is, there is no fetched instruction, and the fetched instruction exists in the private Cache corresponding to the hardware thread, the instruction is fetched from the private Cache corresponding to the hardware thread. In this way, by actively selecting the private Cache corresponding to the hardware thread to participate in Tag comparison, the Cache capacity assigned to each hardware thread can be expanded, and the hit rate of the instruction cache of the hardware thread can be increased.

106. If there is no instruction in both the shared instruction cache and the private instruction cache, the processor sends a cache miss request to a next-level cache of the shared instruction cache through a hardware thread.

Exemplarily, if neither the I-Cache nor the private Cache corresponding to the hardware thread has the instruction fetched, the hardware thread issues a Cache Miss (cache miss) to the next-level cache of the I-Cache.

For example, neither the L1Cache nor the private Cache corresponding to the hardware thread has the fetched instruction, and the hardware thread sends a Cache Miss to the L2Cache, which is the next level cache of the L1Cache, in order to obtain the fetched instruction from the L2Cache.

107. If there is an instruction in the next-level cache, the processor obtains the instruction from the next-level cache through the hardware thread, and stores the cache line where the instruction is located in the missing cache corresponding to the hardware thread. When the hardware thread fetches the instruction, Backfill the cache line into the shared instruction cache.

Exemplarily, when there is a fetched instruction in the L2Cache, the instruction is obtained from the L2Cache, and the Cache Line where the instruction is located is not directly backfilled into the L1Cache, but the Cache Line where the fetched instruction is located is stored in the hardware thread corresponding In the Miss Buffer (missing cache), until it is the turn of the hardware thread to fetch instructions, fill the Cache Line into the L1Cache.

Among them, the Miss Buffer corresponds to the hardware thread one by one, that is, each hardware thread has a Miss Buffer, and each hardware thread uses a Miss Buffer to cache the Cache Line returned by the Cache Miss request. This is because it is assumed that the Cache Line is backfilled When the L1Cache is replaced, the replaced Cache Line may be the Cache Line that is about to be accessed. The existence of the Miss Buffer optimizes the backfill timing of the Cache Line and reduces the chance that the Cache Line that will be accessed will be replaced by the cache. .

108. If there is no instruction in the next-level cache, the processor sends a miss request to the main memory through the hardware thread, obtains the instruction from the main memory, and stores the cache line where the instruction is located in the miss cache corresponding to the hardware thread. When a hardware thread fetches an instruction, it backfills the cache line into the shared instruction cache.

Exemplarily, if the fetched instruction does not exist in the L2Cache, the hardware thread sends a CacheMiss request to the main memory, so as to obtain the fetched instruction from the main memory. If the fetched instruction exists in the main memory, the fetched instruction is obtained, and the Cache Line where the fetched instruction is located is saved in the Miss Buffer corresponding to the hardware thread, until it is the turn of the hardware thread to fetch the instruction, the Cache Line is filled into the L1Cache.

It can also be that when the fetched instruction does not exist in the L2Cache, the hardware thread sends a Cache Miss request to the L3Cache. If there is a fetched instruction in the L3Cache, the fetched instruction is obtained, and if there is no fetched instruction in the L3Cache, it is sent to the main memory. Cache Miss request to get fetched instructions.

Among them, the exchange unit between the CPU and the Cache is a word. When the CPU wants to read a word in the main memory, the memory address issued by the word arrives at the Cache and the main memory at the same time. L1Cache, L2Cache or L3Cache can control the logical basis address in the Cache The tag part of the tag judges whether there is a word. If it hits, the CPU gets the word. If it misses, it needs to use the main memory read cycle to read it from the main memory and output it to the CPU. Even if the current CPU only reads one word, the Cache control The processor also copies a complete Cache line containing the word in the main memory to the Cache. This operation of transferring a line of data to the Cache is called Cache line filling.

In addition, when backfilling the cache line into the shared instruction cache, if there is no idle resource in the shared instruction cache, replace the cache line with the first cache line in the shared instruction cache, backfill the cache line into the shared instruction cache, and at the same time according to The hardware thread identifier of the first hardware thread of the first cache line is acquired, and the first cache line is stored in a private instruction cache corresponding to the first hardware thread. Wherein, the first cache line is determined by an LRU (Least Recently Used, least recently used) algorithm.

Exemplary, Thread ID (hardware thread identification) can be added in I-Cache Data Array (instruction cache data storage array), and this hardware thread identification is used to represent the Cache Miss request that a Cache Line is sent by which hardware thread retrieved. In this way, after setting a fully associative private Cache in each hardware thread, when the I-Cache is replaced, the replaced Cache Line is not directly discarded, but the replaced Cache Line can be filled in according to the ThreadID. Into the private Cache of the hardware thread identified by the Thread ID, this is because the replaced Cache Line may be accessed soon. As shown in Figure 4.

When storing the replaced first cache line in the private instruction cache corresponding to the acquired first hardware thread, if there is no idle resource in the private instruction cache corresponding to the first hardware thread, replace the first cache line with the first hardware thread The second cache line in the corresponding private instruction cache backfills the first cache line into the private instruction cache corresponding to the first hardware thread. Wherein, the second cache line is determined through the LRU algorithm.

Among them, the LRU algorithm is to replace the instruction that has not been used for the longest time out of the cache once the instruction cache is missing. In other words, the cache first retains the most recently frequently used instructions.

In this way, by increasing the private Cache, the instruction cache capacity allocated to each hardware thread is effectively expanded, the hit rate of the instruction cache of the hardware thread is increased, and the communication between the I-Cache and the next-level cache is reduced. At the same time, the added Miss Buffer optimizes the backfill timing of the Cache Line, reducing the chance of the Cache Line being accessed soon being replaced. The added Tag comparison logic makes it possible to access the shared instruction cache and the private instruction cache at the same time when accessing the I-Cache. Increased instruction cache hit ratio.

An embodiment of the present invention provides a method for managing an instruction cache. When a hardware thread of a processor acquires an instruction from the instruction cache, it simultaneously accesses the shared instruction cache in the instruction cache and the private instruction cache corresponding to the hardware thread to determine the shared instruction cache. Whether there is an instruction in the private instruction cache corresponding to the hardware thread, and according to the judgment result, the instruction is obtained from the shared instruction cache or the private instruction cache corresponding to the hardware thread. The next-level cache of the shared instruction cache sends a cache miss request, and stores the cache line where the instruction is located in the missing cache corresponding to the hardware thread. When the hardware thread fetches an instruction, the cache line is backfilled into the shared instruction cache. When backfilling a line into the shared instruction cache, if there is no idle resource in the shared instruction cache, replace the cache line with the first cache line in the shared instruction cache, backfill the cache line into the shared instruction cache, and at the same time obtain the first cache line The hardware thread identification of the first hardware thread, the first cache line is stored in the private instruction cache corresponding to the first hardware thread, which can expand the instruction cache capacity of the hardware thread, reduce the miss rate of the instruction cache, and improve system performance.

In the several embodiments provided in this application, it should be understood that the disclosed processor and method may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

In addition, in the devices and systems in various embodiments of the present invention, each functional unit may be integrated into one processing unit, each unit may be physically included separately, or two or more units may be integrated into one unit. Moreover, each of the above-mentioned units can be implemented in the form of hardware, or can be implemented in the form of hardware plus software functional units.

All or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium, and when the program is executed, the steps including the above-mentioned method embodiments are executed; The aforementioned storage media include: U disk, mobile hard disk, read only memory (Read Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), magnetic disk or optical disk, etc., which can store program codes. medium.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (9)

1. A processor, characterized in that it comprises a program counter, a register file, an instruction prefetch unit, an instruction decoding unit, an instruction emission unit, an address generation unit, an arithmetic logic unit, a shared floating-point unit, a data cache, and an internal bus , characterized in that it also includes: The shared instruction cache is used to store shared instructions of all hardware threads, including a tag storage array and a data storage array, the tag storage array is used to store tags, the data storage array includes stored instructions and hardware thread identifiers, and the hardware The thread identifier is used to identify the hardware thread corresponding to the cache line in the shared instruction cache; A private instruction cache, configured to store instruction cache lines replaced from the shared instruction cache, where the private instruction cache corresponds to the hardware threads one by one; The miss cache is used to save the cache line retrieved from the next-level cache of the shared instruction cache in the miss cache of the hardware thread when the fetched instruction does not exist in the shared instruction cache. When the hardware thread corresponding to the fetched instruction fetches an instruction, the cache line in the missing cache is backfilled into the shared instruction cache, and the missing cache corresponds to the hardware thread one by one. 2. The processor according to claim 1, further comprising: Tag comparison logic, used to compare the tag in the private instruction cache corresponding to the hardware thread with the physical address converted by the translation lookaside buffer when the hardware thread fetches instructions, and compare the private instruction cache with the tag Logically connected, so that the hardware thread accesses the private instruction cache while accessing the shared instruction cache. 3. The processor according to claim 2, wherein the processor is a multithreaded processor, and the structure of the private instruction cache is a fully associative structure, and the fully associative structure in the main memory Any piece of instruction cache maps any piece of instruction cache in the private instruction cache. 4. The processor according to claim 3, wherein the shared instruction cache, the private instruction cache and the miss cache are static memory chips or dynamic memory chips. 5. A method for managing an instruction cache, comprising: When the hardware thread of the processor acquires the instruction from the instruction cache, simultaneously access the shared instruction cache in the instruction cache and the private instruction cache corresponding to the hardware thread; Determine whether the instruction exists in the shared instruction cache and the private instruction cache corresponding to the hardware thread, and obtain the instruction from the shared instruction cache or the private instruction cache corresponding to the hardware thread according to the judgment result; Wherein, the shared instruction cache includes a tag storage array and a data storage array, the tag storage array is used to store tags, the data storage array includes stored instructions and a hardware thread ID, and the hardware thread ID is used to identify the The hardware thread corresponding to the cache line in the shared instruction cache; The structure of the private instruction cache is a fully associative structure, and the fully associative structure maps any instruction cache in the private instruction cache to any instruction cache in the main memory, and the private instruction cache is connected to the hardware Threads correspond one-to-one. 6. The method according to claim 5, wherein the determining whether the instruction exists in the shared instruction cache and the private instruction cache corresponding to the hardware thread, and selecting the instruction from the shared instruction cache or Obtaining the instruction from the private instruction cache corresponding to the hardware thread includes: If the instruction exists in both the shared instruction cache and the private instruction cache corresponding to the hardware thread, obtain the instruction from the shared instruction cache; If the instruction exists in the shared instruction cache and the instruction does not exist in the private instruction cache corresponding to the hardware thread, then obtain the instruction from the shared instruction cache; If the instruction exists in the private instruction cache corresponding to the hardware thread and the instruction does not exist in the shared instruction cache, acquire the instruction from the private instruction cache corresponding to the hardware thread. 7. The method according to claim 6, further comprising: If the instruction does not exist in the shared instruction cache and the private instruction cache, send a cache miss request to the next-level cache of the shared instruction cache through the hardware thread; If the instruction exists in the next-level cache, the instruction is obtained from the next-level cache through the hardware thread, and the cache line where the instruction is located is stored in the miss corresponding to the hardware thread In the cache, when the hardware thread fetches an instruction, backfill the cache line into the shared instruction cache; If the instruction does not exist in the next-level cache, send the missing request to the main memory through the hardware thread, obtain the instruction from the main memory, and store the cache line where the instruction is located In the missing cache corresponding to the hardware thread, when the hardware thread fetches an instruction, backfill the cache line into the shared instruction cache; Wherein, the missing cache is in one-to-one correspondence with the hardware threads. 8. The method according to claim 7, wherein when backfilling the cache line into the shared instruction cache, if there is no free resource in the shared instruction cache, then replacing the cache line with the The first cache line in the shared instruction cache, backfill the cache line into the shared instruction cache, and at the same time, according to the hardware thread identifier of the first hardware thread that acquires the first cache line, backfill the first cache line The row is stored in a private instruction cache corresponding to the first hardware thread; Wherein, the first cache line is determined by a least recently used algorithm. 9. The method according to claim 8, wherein when storing the replaced first cache line in the private instruction cache corresponding to the first hardware thread, if the first hardware thread corresponds to If there is no idle resource in the private instruction cache, replace the first cache line with the second cache line in the private instruction cache corresponding to the first hardware thread, and backfill the first cache line to the first hardware thread in the corresponding private instruction cache; Wherein, the second cache line is determined by the least recently used algorithm.