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CN104267218B - A kind of BGA package test jack for possessing pin test function - Google Patents

A kind of BGA package test jack for possessing pin test function Download PDF

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Publication number
CN104267218B
CN104267218B CN201410535754.7A CN201410535754A CN104267218B CN 104267218 B CN104267218 B CN 104267218B CN 201410535754 A CN201410535754 A CN 201410535754A CN 104267218 B CN104267218 B CN 104267218B
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China
Prior art keywords
pin
measured
substrate
slot
bga chip
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CN201410535754.7A
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CN104267218A (en
Inventor
杨阳
杨硕
周津
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Tianjin Jinhang Computing Technology Research Institute
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No 8357 Research Institute of Third Academy of CASIC
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Abstract

The invention discloses a kind of BGA package test jack for possessing pin test function, it is characterized in that the socket includes substrate, the PLD and pin test point buried in substrate, the substrate is integrated pcb board, cabling is provided with inside substrate, cabling is connected with the pin of PLD, the upper face center of substrate is provided with slot, slot point is provided with slot, the slot is used to insert bga chip to be measured, the spherical pin spacing conformance to specifications of the separation of the slot and bga chip to be measured, line number and columns that the number of lines and columns of the slot point are respectively encapsulated more than the spherical pin of bga chip to be measured;The bottom surface of the substrate is provided with substrate draw-foot, and the PLD is connected with the spherical pin of substrate draw-foot and bga chip to be measured;The pin test point is drawn by PLD, is evenly distributed on the top surface edge of substrate.

Description

A kind of BGA package test jack for possessing pin test function
Technical field
The present invention relates to a kind of test jack, specially a kind of BGA package test jack for possessing pin test function.
Background technology
The pin measurement of chip bga needs to account for before pcb board design, and needs to measure Each pin draw a test point, give over to pcb board test when use.If being designed without drawing test point in pcb board, that In system testing if there is problem, just the equipment such as oscillograph can not be used to measure.
The pin spacing specification of chip bga is limited, generally 1.27mm, 1mm, 0.8mm, 0.65mm, 0.5mm, Several specifications such as 0.45mm, 0.4mm, 0.3mm, but under same specification, the pin number of bga chip and distribution Dou Youhen great areas Not, the bga chip of many non-standard encapsulation can not be put into the bga socket of standard, it is necessary to special special format customized Socket, this testing cost that small-lot chips have been significantly greatly increased and cycle.
Traditional board level testing system must reserve the test point of special pin, once it is determined that can not change;If desired Retain to the power of test of all BGA pins, it is necessary to which all pins are all drawn into test point.
Therefore one kind is provided and can be used in non-standard encapsulation bga chip, and size is identical, power pins are distributed with ground pin The test jack that identical, the signal pins quantity bga chip different from distribution carries out pin test turns into the prior art urgently The problem of solution.
The content of the invention
In view of the shortcomings of the prior art, the technical problem that the present invention is intended to solve has been to provide one kind and has possessed pin test work( The BGA package test jack of energy, the socket can carry out power of tests to the whole pins of chip bga, and be applicable to mark The accurate bga chip with a range of off-gauge BGA package form.
The present invention solves the technical problem and a kind of possesses pin test function the technical scheme adopted is that providing BGA package test jack, it is characterised in that the socket includes the PLD buried in substrate, substrate and pin test Point, the substrate is that cabling is provided with inside integrated pcb board, substrate, and cabling is connected with the pin of PLD, substrate Upper face center, which is provided with slot, slot, is provided with slot point, and the slot is used to insert bga chip to be measured, the groove of the slot Spacing and the spherical pin spacing conformance to specifications of bga chip to be measured, the number of lines and columns of the slot point are respectively more than to be measured The line number and columns of the spherical pin encapsulation of bga chip;The bottom surface of the substrate is provided with substrate draw-foot, the programmable logic device Part is connected with the spherical pin of substrate draw-foot and bga chip to be measured;The pin test point is drawn by PLD, The even top surface edge for being distributed in substrate.
Compared with prior art, the present invention has online programming ability, can be by the ball being arbitrarily designated of bga chip to be measured Shape pin leads to pin test point, while can change tested spherical pin by programming, is tested by using a small amount of pin The test to the spherical pin of all bga chips to be measured can be achieved in point.The present invention also has good adaptability, between pin Away from identical, feelings of the row, column number no more than the row, column number of the slot point of slot in the present invention of the spherical pin of bga chip to be measured Under condition, it is possible to achieve the test to the bga chip of different number of pins types.
Brief description of the drawings
Fig. 1 possesses a kind of vertical section structure of embodiment of BGA package test jack of pin test function for the present invention Schematic diagram;
Fig. 2 possesses a kind of plan structure signal of embodiment of BGA package test jack of pin test function for the present invention Figure;
In figure, 1, substrate, 2, PLD, 3, pin test point, 4, substrate draw-foot, 5, bga chip to be measured.
Embodiment
The present invention is further discussed below with reference to embodiment and its accompanying drawing, specific embodiment is only to the further of the present invention Explain, protection scope of the present invention is not limited with this.
The present invention possess pin test function BGA package test jack (abbreviation socket, referring to Fig. 1-2) include substrate 1, The PLD 2 and pin test point 3 buried in substrate, the substrate 1 is to be set inside the pcb board of high integration, substrate 1 There is cabling, cabling is connected with the pin of PLD 2, the upper face center of substrate 1 is provided with slot, slot provided with slotting Groove point, the slot is used to insert bga chip 5 to be measured, state the spherical pin spacing of the separation of slot and bga chip to be measured with Specification is consistent, and the number of lines and columns of the slot point are respectively more than line number and columns that the spherical pin of bga chip to be measured is encapsulated; The bottom surface of the substrate 1 is provided with substrate draw-foot 4, the PLD 2 and substrate draw-foot 4 and the ball of bga chip to be measured 5 Shape pin carries out logic connection;The pin test point 3 is drawn by PLD 2, is evenly distributed on the upper table of substrate 1 Face edge.
The application method of socket of the present invention is:When needing to carry out functional test to bga chip to be measured, by BGA to be measured In the slot of the insertion substrate 1 of chip 5, and the socket is connected to test system using physical connection mode, according to system design, PLD 2 is programmed in advance, bga chip 5 to be measured is tested by being logically connected to default output pin On point 3;
In some the spherical pin signal for needing to measure bga chip 5 to be measured, it is necessary to be carried out to PLD 2 Programming, is connected to the reserved pin of BGA test jacks by PLD 2 by the spherical pin of bga chip to be measured and surveys In pilot 3, the just state of the measurable point;
When needing to change the type of bga chip 5 to be measured, it is only necessary to PLD 2 is programmed again, built Found the spherical pin of new bga chip to be measured 5 and the corresponding annexation of pin test point 3.
The quantity of pin test point 3 of the present invention is relevant with the quantity of requirement of system design and bga chip to be measured, pin test The quantity maximum of point 3 can be supported to test the pin of all bga chips.
The software flow that the present invention is realized is:1) it is the pin point of all bga chips to be measured 5 for being connected to substrate draw-foot 4 GPIO pin with PLD 2;2) it is to need to be connected to the pin assignment of the bga chip to be measured 5 of pin test point 3 Programmable logic device pin;3) in the internal logic of programmable logic device, the logical relation 1), 2) set up in two steps is entered Row connection;4) Pin locations that bga chip 5 to be measured leads to pin test point 3 are changed if desired, then returning to the, 2) step is again Set;5) the software programming for writing completion is entered in the program storage area of PLD.
The present invention possesses the BGA package test jack of pin test function, with online programming ability, can will be to be measured The spherical pin being arbitrarily designated of bga chip 5 leads to pin test point 3, possesses and is owned using a small amount of 3 pairs of pin test point The power of test of the spherical pin of bga chip 5 to be measured, and the spherical pin for being tested bga chip 5 can be changed by programming, And then the test of the spherical pin to all bga chips 5 to be measured can be easily carried out.The present invention has good adaptability, Identical in pin spacing, the line number and columns of the spherical pin of bga chip 5 to be measured are respectively no more than slot in slot in the present invention In the case of the line number and columns of point, it is possible to achieve the test to the bga chip of different number of pins types.
The present invention does not address part and is applied to prior art.

Claims (1)

1. a kind of BGA package test jack for possessing pin test function, it is characterised in that the socket in substrate, substrate including burying PLD and pin test point, the substrate is integrated pcb board, cabling is provided with inside substrate, cabling is with that can compile The pin of journey logical device is connected, and the upper face center of substrate, which is provided with slot, slot, is provided with slot point, and the slot is used to insert Put bga chip to be measured, the spherical pin spacing conformance to specifications of the separation of the slot and bga chip to be measured, the slot Line number and columns that the number of lines and columns of point are respectively encapsulated more than the spherical pin of bga chip to be measured;The bottom surface of the substrate is set There is substrate draw-foot, the PLD is connected with the spherical pin of substrate draw-foot and bga chip to be measured;The pin is surveyed Pilot is drawn by PLD, is evenly distributed on the top surface edge of substrate;
The application method of socket is:When needing to carry out functional test to bga chip to be measured, bga chip to be measured is inserted into base In the slot of plate, and the socket is connected to test system using physical connection mode, according to system design, in advance to programmable Logical device is programmed, by bga chip to be measured by being logically connected in default output pin test point;
, will in some the spherical pin signal for needing to measure bga chip to be measured, it is necessary to be programmed to PLD The spherical pin of bga chip to be measured is connected in the reserved pin test point of BGA test jacks by PLD, just The state of the measurable point;
When needing to change the type of bga chip to be measured, it is only necessary to PLD is programmed again, set up newly The corresponding annexation of the spherical pin of bga chip to be measured and pin test point.
CN201410535754.7A 2014-10-11 2014-10-11 A kind of BGA package test jack for possessing pin test function Active CN104267218B (en)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105067846A (en) * 2015-08-10 2015-11-18 深圳市共进电子股份有限公司 BGA package chip test clamp
CN105353175B (en) * 2015-11-22 2018-01-05 苏州光韵达光电科技有限公司 A kind of BGA package test jack
CN107976618B (en) * 2016-03-08 2020-02-07 宁波利特舜电气有限公司 Working method of BGA packaging test socket
CN106771405B (en) * 2017-01-06 2017-12-29 中国船舶重工集团公司第七0九研究所 A kind of spherical grid array integrated circuit interface adapter
US10789550B2 (en) * 2017-04-13 2020-09-29 Battelle Memorial Institute System and method for generating test vectors
CN109116061A (en) * 2018-09-10 2019-01-01 上海泽丰半导体科技有限公司 A kind of socket based on chip testing
CN114078566A (en) 2020-08-14 2022-02-22 长鑫存储技术有限公司 Test fixture

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US6300781B1 (en) * 1998-10-30 2001-10-09 St Assembly Test Services Pte Ltd Reliable method and apparatus for interfacing between a ball grid array handler and a ball grid array testing system
CN201600928U (en) * 2009-05-08 2010-10-06 黄建军 Chip test system and automatic test vector generator ATPG
CN203396792U (en) * 2013-08-08 2014-01-15 长春长光辰芯光电技术有限公司 Chip-packaging general test seat

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CN100373165C (en) * 2003-12-26 2008-03-05 技嘉科技股份有限公司 Ball grid array substrate detection device and construction method thereof
CN101063625B (en) * 2006-04-30 2010-08-11 中芯国际集成电路制造(上海)有限公司 BGA packaging retainer apparatus and method for testing BGA packaging
CN100578240C (en) * 2007-05-29 2010-01-06 北京中星微电子有限公司 A method for realizing chip testing
CN102621466B (en) * 2012-03-22 2015-02-11 上海华力微电子有限公司 Aging test board and method for manufacturing same
CN204154755U (en) * 2014-10-11 2015-02-11 中国航天科工集团第三研究院第八三五七研究所 A kind of BGA package test jack

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US6300781B1 (en) * 1998-10-30 2001-10-09 St Assembly Test Services Pte Ltd Reliable method and apparatus for interfacing between a ball grid array handler and a ball grid array testing system
CN201600928U (en) * 2009-05-08 2010-10-06 黄建军 Chip test system and automatic test vector generator ATPG
CN203396792U (en) * 2013-08-08 2014-01-15 长春长光辰芯光电技术有限公司 Chip-packaging general test seat

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Patentee before: NO.8357 Research Institute of the Third Academy of China Aerospace Science & Industry Corp.

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