CN104270885A - Plug-in frame with polymer matrix and method of manufacturing the same - Google Patents

Abstract

An array of chip sockets defined by an organic matrix frame surrounding sockets passing through the organic matrix frame and further comprising a grid of metal vias passing through the organic matrix frame. In one embodiment, a panel includes an array of chip sockets, each chip socket surrounded and defined by an organic matrix frame comprising a grid of copper vias passing through the organic matrix frame. The panel includes at least one area having sockets of a first set of form factors for receiving chips of a first type and a second area of sockets having sockets of a second set of form factors for receiving chips of a second type.

Description

Plug-in frame with polymer matrix and method of manufacturing the same

related application

This patent application is a continuation-in-part of US Patent Application Serial No. 14/249,282, filed April 9, 2014, entitled "Method of Manufacturing an Embedded Chip." The disclosure of US Patent Application No. 14/249,282 is incorporated herein by reference in its entirety.

technical field

The invention relates to chip packaging, in particular to an embedded chip.

Background technique

Consumer electronics, such as computers and telecommunications equipment, are becoming increasingly integrated, driven by the need to miniaturize increasingly complex electronic components. This has created a need for support structures such as IC substrates and IC packages to have a high density of multiple conductive layers and vias that are electrically isolated from each other by dielectric materials.

The overall requirements for this support structure are reliability and proper electrical performance, thinness, stiffness, flatness, good heat dissipation and competitive unit price.

Among the various ways to achieve these requirements, a widely practiced processing technique for forming interlayer interconnect vias is the use of laser drilling, which drills holes through the subsequently arranged dielectric substrate to the final metal layer, Subsequent filler metal, usually copper, is deposited therein by plating techniques. This approach to hole formation is sometimes referred to as "drill & fill", and the resulting vias can be referred to as "drill & fill vias".

The drill and fill via approach has several disadvantages. Since each via requires individual drilling, throughput is limited and the cost of manufacturing complex multi-via IC substrates and interposers becomes prohibitive. In large arrays, it is difficult to produce high-density and high-quality vias of different sizes and shapes that are closely adjacent to each other by the drill-and-fill method. In addition, laser drilled vias have rough sidewalls and inward taper through the thickness of the dielectric material. This taper reduces the effective diameter of the through hole. Especially in the case of extremely small via diameters, this can also have a negative effect on the electrical contacting of the preceding conductive metal layer, thus leading to reliability problems. Furthermore, when the dielectric being drilled is a composite material comprising glass or ceramic fibers in a polymer matrix, the sidewalls are particularly rough, and this roughness may cause additional stray inductance.

The filling process of the drilled vias is usually done by copper electroplating. Plated-fill drilling causes dimples, which are small pits at the ends of the vias. Alternatively, overflow may result when the via channel is filled with more copper than it can hold, creating a hemispherical upper surface that protrudes beyond the surrounding material. Both pits and overflows tend to create difficulties in subsequent stacking of vias on top of each other as required in the manufacture of high density substrates and interposers. In addition, it should be recognized that large via channels are difficult to fill uniformly, especially when they are located adjacent to smaller vias within the same interconnect layer of the package or IC substrate design.

Acceptable size ranges and reliability are improving over time. However, the disadvantages described above are inherent to the drill-and-fill technique and are expected to limit the range of possible via sizes. It should also be noted that laser drilling is the best way to create circular vias. While it is theoretically possible to fabricate slit-shaped via channels by laser milling, in practice the range of manufacturable geometries is limited, and the vias in a given support structure are usually cylindrical and substantially identical.

Manufacturing vias by drill and fill is expensive, and it is difficult to uniformly and consistently fill the via channels formed thereby with copper using a relatively cost-effective electroplating process.

Laser-drilled vias in composite dielectric materials are practically limited to a minimum diameter of 60× ^10-6 m, and even suffer from significant The tapered shape and the adverse effects of rough sidewalls.

In addition to the other limitations of laser drilling described above, another limitation of drill-and-fill technology is that it is difficult to form vias of different diameters in the same layer, because when drilling via channels of different sizes and then using metal When filling to make vias of different sizes, the filling rate of via channels is different. As a result, the typical problems of pits or overflows that are characteristic of drill-and-fill techniques are further exacerbated by the impossibility of simultaneous optimization of the deposition technique for different sized vias.

An alternative solution to overcome several of the shortcomings of the drill-and-fill approach is to utilize a technique also known as "pattern plating" to create vias by depositing copper or other metal deposits within a pattern formed in photoresist .

In pattern plating, a seed layer is deposited first. A layer of photoresist is then deposited thereon, subsequently patterned by exposure, and selectively removed to make trenches exposing the seed layer. Via posts are formed by depositing copper into the photoresist trenches. The remaining photoresist is then removed, the seed layer is etched away, and a dielectric material, typically a polymer-impregnated fiberglass mat, is laminated over and around it to surround the via post. Various techniques and processes can then be used to planarize the dielectric material, removing a portion of it to expose the ends of the via posts, allowing conductive grounding therefrom for building the next metal layer on top of. Subsequent metal conductor layers and via posts can be deposited thereon by repeating the process to build the desired multilayer structure.

In an alternative but closely related technique, hereinafter "panelplating", a continuous layer of metal or alloy is deposited onto a substrate. A layer of photoresist is deposited on the ends of the substrate and a pattern is developed in it. The developed photoresist pattern is stripped, selectively exposing the underlying metal, which can then be etched away. The undeveloped photoresist protects the underlying metal from being etched away and leaves a pattern of standing features and vias.

After stripping the undeveloped photoresist, a dielectric material, such as a polymer-impregnated fiberglass mat, can be laminated around and over the upstanding copper features and/or via posts. After planarization, subsequent metal conductor layers and via posts can be deposited thereon by repeating the process to build the desired multilayer structure.

The via layers formed by the pattern plating or panel plating methods described above are often referred to as copper "via posts" and feature layers.

It should be recognized that the overall driving force in the evolution of microelectronics involves making smaller, thinner, lighter and more powerful products with high reliability. Ultra-thin products cannot be achieved using thick and cored interconnects. To form higher density structures in interconnected IC substrates or "packages," more layers with even smaller connections are required.

If the plated laminate structure is deposited on a copper or other suitable sacrificial substrate, the substrate can be etched away, leaving a free-standing coreless laminate structure. Additional layers can be deposited on the sides that are pre-attached to the sacrificial substrate, enabling dual-layer layers that minimize warpage and aid in planarization.

A flexible technique for fabricating high-density interconnects is to build patterned or panel-plated multilayer structures consisting of metal vias or via post features in a dielectric matrix with a variety of geometries and morphologies. composition. The metal can be copper and the dielectric can be a membrane polymer or a fiber reinforced polymer, typically a polymer with a high glass transition temperature (T _g ) such as polyimide or epoxy, for example. These interconnects can be cored or coreless, and can include cavities for stacking components. They can have odd or even layers. Implementation techniques are described in prior patents issued to Amitec-Advanced Multilayer Interconnect Technologies Ltd.

For example, U.S. Patent 7,682,972 to Hurwitz et al., entitled "Advanced multilayer coreless support structures and method for their fabrication" describes a fabrication process involving A method for a free-standing film of an array of vias in a dielectric, said film being used as a precursor for the construction of superior electronic support structures, comprising the steps of: fabricating a conductive via film in a dielectric surrounding a sacrificial support, and incorporating said The membrane is separated from the sacrificial support to form a self-contained laminated array. Electronic substrates based on this freestanding film can be formed by thinning and planarizing the laminated array followed by termination of the vias. This publication is hereby incorporated by reference in its entirety.

US Patent No. 7,669,320 to Hurwitz et al., entitled "Coreless cavity substrates for chip packaging and their fabrication" describes a method for fabricating IC A method of a support for supporting a first IC chip in series with a second IC chip; the IC support comprising a stack of alternating layers of copper features and vias in an insulating surrounding material, The first IC chip can be bonded to the IC support, and the second IC chip can be bonded in a cavity inside the IC support, wherein the cavity is formed by etching away a copper pedestal and selectively Formed by etching away accumulated copper. This publication is hereby incorporated by reference in its entirety.

U.S. Patent No. 7,635,641 to Hurwitz et al., entitled "Integrated circuit support structures and their fabrication" describes a method of manufacturing electronic substrates comprising the following steps : (A) selecting a first base layer; (B) depositing an etch stop layer onto said first base layer; (C) constructing a first half-stack of alternating conducting and insulating layers, said conducting layer passing through interconnected through vias in the insulating layer; (D) applying a second base layer to the first half-stack; (E) applying a photoresist protective coating to the second base layer; (F) Etching away the first base layer; (G) removing the photoresist protective coating; (H) removing the first etch stop layer; (I) constructing a second layer of alternating conductive and insulating layers a half-stack, the conductive layers interconnected by vias penetrating the insulating layers; wherein the second half-stack has a substantially symmetrical configuration to the first half-stack; (J) applying insulating layers to the alternating conductive layers and on the second half-stack of insulating layers; (K) removing the second base layer, and, (L) by exposing via ends on the outer surface of the stack and applying terminations thereto to terminalize the substrate. This publication is hereby incorporated by reference in its entirety.

The via post technology described in US Pat. Nos. 7,682,972, 7,669,320, and 7,635,641 enables simultaneous plating of a large number of vias for mass production. As previously mentioned, existing drill-and-fill vias have an effective minimum diameter of about 60 microns. The difference is that the via post technology using photoresist and electroplating can achieve higher via density. It is possible to achieve via diameters as small as 30 micron diameter and to simultaneously fabricate vias of different geometries and shapes in the same layer.

Over time, it is expected that both drill-and-fill techniques and via post deposition will enable the fabrication of further miniaturized substrates with higher densities of vias and features. However, it is clear that the development of via post technology will continue to maintain competitiveness.

The substrate enables the chip to interface with other components. The chip must be bonded to the substrate in an assembly process that provides a reliable electrical connection, enabling electrical communication between the chip and the substrate.

Connecting to the outside world by embedding the chip in the interposer enables a reduced chip package, shortens connections to the outside world, provides cost savings by simplifying processing, ie eliminating the chip in the substrate assembly process, and potentially increases reliability.

Basically, the concept of embedded active components such as analog, digital and MEMS chips involves the construction of a chip support structure or substrate with vias around the chip.

One way to implement embedded chips is to fabricate a chip support structure on top of an array of chips on a wafer, where the circuitry of the support structure is larger than the size of the chip unit. This is known as Fan-Out Wafer Layer Packaging (FOWLP). While the size of silicon wafers is increasing, expensive material sets and manufacturing processes still limit the size to 12 inches in diameter, thereby limiting the number of FOWLP units that can be placed on a wafer. Despite the fact that 18-inch wafers are gaining traction, the required investment, material set and equipment are still unknown. The limitation on the number of chip support structures that can be processed at one time increases the unit cost resulting in FOWLP and makes it prohibitively expensive for markets requiring highly competitive prices such as wireless communications, home appliances, and automotive markets.

FOWLP also exhibits performance limitations due to the fact that the metal features placed on the silicon wafer as fan-out or fan-in circuits are limited to a thickness of a few microns. This poses the challenge of the resistance problem.

Another alternative manufacturing route involves partitioning the wafer to separate the chips and embedding the chips into panels made of dielectric layers and copper interconnects. One advantage of this alternative route is that panels can be very large with a very large number of chips embedded in a single process. For example, just as an example, a 12-inch wafer can handle 2,500 FOWLP chips with a size of 5mm×5mm at one time, and the panel currently used by the applicant, Zhuhai Yueya, is 25 inches×21 inches, which can realize one-time processing 10000 chips. Since the price of processing such panels is significantly lower than on-wafer processing, and since the throughput per panel is 4 times higher than on-wafer, the unit cost drops significantly, thereby opening new markets.

In both technologies, the industrially adopted line and track pitches have shrunk over time, from 15 microns to 10 microns for standard on-panel technology and from 5 microns to 2 microns for on-wafer technology.

The advantages of embedding are many, first-level assembly costs such as wire bonding, flip-chip or SMD (Surface Mount Device) soldering are eliminated. Electrical performance is improved due to the seamless connection of chip and substrate in a single product. The packaged die becomes thinner, giving an improved form factor, and the top surface of the embedded die package is freed for other applications including stacked die and PoP (package-on-package) technologies.

In both embedded chip technologies based on FOWLP and panels, chips are packaged in arrays (either on a wafer or on a panel) and, once fabricated, are separated by dicing.

Embodiments of the present invention address the manufacturing issues of embedded chip packages.

Embodiments of the present invention address the problem of polymer frames with chip sockets for packaging chips.

Contents of the invention

A first aspect relates to providing a chip socket array defined by a frame comprising a polymer matrix and an array of metal vias passing through the polymer matrix frame.

Typically, each chip socket is surrounded by a polymer matrix frame that includes copper vias through the frame.

Typically, the frame also includes glass fiber reinforcement within the polymer matrix.

In some implementations, the metal via is a via post.

In some embodiments, the width of each via is in the range of 25 microns to 500 microns.

In some embodiments, the grid of metal vias through the organic matrix framework includes multiple via layers.

In some embodiments, the frame surrounding at least one socket comprises a continuous coil of elongated via posts.

In some embodiments, the continuous coil of elongated via posts spans multiple layers.

In some embodiments, each via is cylindrical and has a diameter in the range of 25 microns to 500 microns.

In some embodiments, adjacent chip sockets have different outer dimensions.

In some embodiments, adjacent chip sockets have different sizes.

In some embodiments, adjacent chip sockets have different shapes.

A second aspect relates to a panel comprising an array of chip sockets each surrounded and defined by a polymer matrix frame comprising a grid of copper vias passing through the polymer matrix frame , wherein the panel includes at least one area having sockets of a first set of form factors for receiving chips of a first type, and a second area of sockets having sockets of a second set of form factors for receiving chips of a second type.

Optionally, at least one through hole is non-cylindrical.

Optionally, at least one through hole is elongated.

In some embodiments, the frame includes more than one via layer.

In some embodiments, the elongated vias are coils.

Optionally, at least one via is a coaxial via.

Optionally, the frame also includes glass fiber reinforcement within the polymer matrix.

Preferably, the frame further comprises woven fiberglass strands within a polymer matrix.

In some embodiments, the frame includes an array of two different sockets for receiving two different chips in adjacent sockets.

Optionally, said different sockets have different shapes.

Optionally, said different sockets have different sizes.

A fourth aspect relates to providing a method of manufacturing a chip socket array surrounded by an organic matrix framework, comprising: obtaining a sacrificial carrier; laying down a photoresist layer and patterning the photoresist layer to have a grid of copper vias; plating copper in the grid; laminating with a polymer dielectric; thinning and planarizing the polymer dielectric to expose the ends of the copper vias; removing the carrier; Mechanically fabricated chip sockets in dielectrics.

Typically, the support is a copper support, which can be removed by dissolving the copper.

Preferably, the method comprises applying an etch stop layer on the carrier prior to depositing the copper vias.

In one embodiment, the etch stop layer includes nickel.

Optionally, the planarized polymer dielectric with exposed copper via ends is protected with an etch stop material while the copper carrier is being etched away.

Optionally, the etch stop material is dry film photoresist.

In some embodiments, a copper seed layer is electroplated on the nickel.

In some embodiments, the copper seed layer is electroplated prior to depositing the nickel barrier layer.

In some embodiments, the grid is made by punching out the sockets and retaining the frame.

In some embodiments, the grid is manufactured by CNC (numerically controlled forming) machining out the sockets and retaining the frame.

An alternative method of fabricating a chip-socket array surrounded by an organic matrix frame comprising:

Obtain a sacrificial carrier;

Deploying a photoresist layer and patterning the photoresist layer to have a grid of copper vias and an array of chip sockets;

plating copper in the grid and the array;

Lamination with polymer dielectric;

thinning and planarizing the polymer dielectric to expose ends of copper vias and the array;

masking the ends of the copper vias;

dissolving the array; and

Remove the carrier.

In some embodiments, the via post is an elongated via post, and the chip socket includes a plurality of via posts separated by a feature layer.

Optionally, a plurality of elongated via posts provide at least one continuous coil surrounding at least one chip socket of said frame.

Preferably, at least one socket is surrounded by an organic frame and a multilayer metal structure embedded in said organic frame, said multilayer metal structure comprising a plurality of layers of via posts extending such that each pair of adjacent vias The pillar layers are separated by feature layers, and the multilayer metal structure includes continuous coils.

Description of drawings

For a better understanding of the invention and to illustrate embodiments of the invention, reference is made below to the accompanying drawings, purely by way of example.

When specific reference is made to the drawings, it must be emphasized that the particular drawings are by way of illustration only and are intended only to discuss preferred embodiments of the invention and are based on what is believed to be a description of the principles and conceptual aspects of the invention. The illustrations are presented for the sake of being useful and most understandable. In this regard, no attempt is made to illustrate structural details of the invention in more detail than is necessary for a fundamental understanding of the invention; descriptions made with reference to the accompanying drawings will enable those skilled in the art to appreciate how the invention may be practiced in its several forms . In the attached picture:

Figure 1 is a schematic illustration of a portion of a polymer or composite grid with chip sockets and through-holes surrounding the sockets;

FIG. 2 is a schematic diagram for manufacturing a panel with embedded chips surrounding through-holes, showing how a portion of the panel, such as a box, may have sockets for different types of chips;

Figure 3 is a schematic illustration of a portion of the polymer or composite frame of Figure 1 with a chip in each socket held in place by a polymer or composite material such as a molding compound, for example;

Fig. 4 is a schematic cross-sectional view of a part of the frame, showing an embedded chip held by a polymer material in each socket, and also showing through-holes and pads on both sides of the panel;

5 is a schematic cross-sectional view of a chip containing an embedded chip;

Figure 6 is a schematic cross-sectional view of a package containing a pair of dissimilar chips in adjacent sockets;

FIG. 7 is a schematic bottom view of the package shown in FIG. 5;

Figure 8 is a flow diagram illustrating a process for fabricating a polymer or composite panel including an array of through-holes;

Fig. 8 (a)～8 (n) is the schematic diagram of the intermediate structure obtained after each step of flowchart 8;

Figure 9 is a flow diagram illustrating how the drill and fill technique can be used to form plated-through vias and stamp to fabricate sockets;

Fig. 9 (a)-9 (e) is the schematic diagram of the intermediate structure that obtains after each step of flowchart 9; And

Fig. 10 is a schematic diagram of a frame with a three-layer coil embedded therein, consisting of elongated vias, illustrating the flexibility of the processing technique and how this technique can be used to fabricate embedded transformers, among others.

Detailed ways

In the following description, reference is made to support structures consisting of metal vias in a dielectric matrix, in particular copper via posts in a polymer matrix such as glass fiber reinforced polyimide, epoxy or BT (bismaleimide/triazine) or mixtures thereof.

Large panels that can be fabricated including very large array substrates with a large number of via posts are characteristic of Zhuhai Yueya (Access) photoresist and patterning or panel plating and lamination techniques, as in Hurwitz et al. described in US Pat. Such panels are substantially flat and substantially smooth.

It is another feature of the Zhuhai Access technology to make a via hole by electroplating using a photoresist and the via hole can be narrower than a via hole formed by a drill-and-fill technique. Currently, the narrowest drill-and-fill vias are about 60 microns. By using photoresist for electroplating, a resolution below 50 microns, even as small as 25 microns, can be obtained. Bonding ICs to such substrates is very challenging. One approach to flip-chip bonding is to provide copper pads that are flush with the dielectric surface. This approach is described in the inventor's US patent application USSN 13/912,652.

All methods of attaching the chip to the package are costly, as are wire bonding and flip chip techniques and broken connections can lead to failure.

Referring to FIG. 1 , a portion of an array 10 of chip sockets 12 is shown bounded by a frame 16 comprising a polymer matrix 16 and an array of metal vias 14 passing through the polymer matrix frame 16 .

Array 10 may be part of a panel comprising an array of chip sockets, each socket surrounded and defined by a polymer matrix frame comprising a grid of copper vias passing through the polymer matrix frame.

Thus, each chip socket 12 is surrounded by a polymer frame 18 with several copper through-holes passing through said frame 18, arranged around the socket 12'.

The frame 18 may be constructed of a polymer applied as a polymer sheet or may be constructed of a glass fiber reinforced polymer applied as a prepreg. Further details can be found below with reference to Figures 8 and 9, in which processing methods are discussed.

Referring to Fig. 2, the panel 20 of the applicant, namely Zhuhai Yueya Company, is usually divided into a 2×2 array of squares 21, 22, 23, 24 separated from each other by the main frame, the main frame is composed of horizontal frame bars 25, vertical frame bars 26 and outer frame 27 form. The block comprises the array of chip sockets 12 in FIG. 1 . Assuming a chip socket size of 5mm x 5mm and Zhuhai Yueya's panel size of 21 inches x 25 inches, this processing technology is capable of packaging 10,000 chips per panel. In contrast, fabrication of chip packages on 12 inch wafers (the largest currently in industry use) only enables processing of 2500 chips at a time, so economies of scale in fabrication on large panels will be realized.

However, panels suitable for this technology can vary in size. Typically, the panel size ranges from about 12 inches by 12 inches to about 24 inches by 30 inches. Some standard sizes in current applications are 20 inches by 16 inches, 20.3 inches by 16.5 inches, and 24.7 inches by 20.5 inches.

All squares of the panel 20 need not have chip sockets 12 of the same size. For example, in the schematic diagram of FIG. 2 , the chip socket 28 of the upper right block 22 is larger than the chip sockets 29 of the other blocks 21 , 23 , 24 . Furthermore, not only can one or more squares 22 be used in sockets of different sizes to accommodate chips of different sizes, but any sub-array of any size can be used to make any particular chip package, thus enabling high throughput, low process A small number of chip packages can be processed at the same time for a specific customer, or different packages can be manufactured for different customers. Accordingly, panel 20 may include at least one region 22 having sockets 28 of a first set of form factors for receiving one type of chip and a second area 22 having sockets 29 of a second set of form factors for receiving a second type of chip. Area 21.

As previously described with reference to FIG. 1, each chip socket 12 (28, 29 of FIG. 2) is surrounded by a polymer frame 18, and a socket 28 is provided in each square (21, 22, 23, 24 of FIG. 2). Array of (29).

Referring to FIG. 3 , a chip 35 may be provided in each socket 12 and the space around the chip 35 may be filled with a polymer 36 , which may or may not be the same polymer used to make the frame 16 . For example, it may be a molding compound. In some embodiments, the same polymer may be used for the filler polymer 36 and the matrix of the frame 16, but different reinforcing fibers may be used. For example, the frame may include reinforcing fibers, while the polymer 36 used to fill in the socket may be free of fibers.

Typically the chip size can be from about 1.5mm x 1.5mm up to about 31mm x 31mm, with the socket being slightly larger to have clearance when accommodating the desired chip. The thickness of the cardcage must be at least the depth of the chip, preferably 10 microns to 100 microns. Typically, the depth of the frame is the chip thickness plus 20 microns.

As a result of the chips 35 being embedded in the socket 12, each individual chip is surrounded by a frame 38 having through-holes 14 therethrough arranged around the edge of each chip.

Using Zhuhai Yueya's via post technology, pattern plating or panel plating, followed by selective etching, the via hole 14 can be fabricated as a via post, followed by a polymer film or a polymer matrix for added stability Preforms made of woven glass fiber strands are laminated with dielectric materials. In one embodiment, the dielectric material is Hitachi 705G. In another embodiment, MGC832 NXA NSFLCA is used. In a third embodiment, Sumitomo GT-K may be used. In another embodiment, Sumitomo LAZ-4785 series membranes are used. In another embodiment, the Sumitomo LAZ-6785 series is used. Alternative materials include Taiyo HBI and Zaristo-125.

Alternatively, the vias can be made using well-known drill-and-fill techniques. First, a polymer or fiber-reinforced polymer matrix is produced, and then, after curing, holes are drilled using mechanical or laser drilling methods. The drilled holes can then be filled with copper by electroplating.

There are many advantages to making vias using via posts rather than drill and fill techniques. In via post technology, via post technology is faster since all vias can be fabricated simultaneously, while drill and fill technology requires individual drilling. In addition, since the drilled via holes are all cylindrical, the via post can have any shape. In practice, all drilled and filled vias have the same diameter (within tolerances), while via posts can have different shapes and sizes. Also, for added strength, it is preferred that the polymer matrix is fiber reinforced, typically with woven strands of glass fibers. When the fibers in the polymer preform are laid onto the upstanding via posts and cured, the via posts are characterized by smooth and vertical sides. However, when drilling composite materials, the drilled and filled vias are often skewed; often have rough surfaces that cause stray inductance, which leads to noise.

Typically, vias 14 have a width in the range of 40 microns to 500 microns. If cylindrical, such as required for drill fill and such as is common in via posts, each via may have a diameter in the range of 25 microns to 500 microns.

Referring again to FIG. 3 , after fabricating the polymer matrix frame 16 with embedded through-holes, the socket 12 can be fabricated by CNC (numerically controlled molding) or stamping. As an alternative, using panel plating or pattern plating, sacrificial copper blocks can be deposited. If the copper via post 14 is selectively masked, eg, with photoresist, the copper block can be etched away to form the socket 12 .

Single and multiple chip packages, including multiple chip packages and building multilayer chip packages, such as package On-package "PoP" array.

Once the chips 35 are positioned in the socket 12, they may be held in place using a polymer 36, such as a molding compound, a dry film B-stage polymer, or a preform.

Referring to FIG. 4, copper wiring layers 42, 43 may be fabricated on one or both sides of the frame 40 in which the chip 35 is embedded. Typically, chip 35 is flip-chip and bonded to pads that fan out beyond the edge of chip 35 . With vias 14, pads 42 on the upper surface allow bonding to another chip layer for PoP (package-on-package) packaging or the like. In practice, it should be appreciated that the upper and lower pads 42, 43 enable the construction of additional via post and wiring feature layers to form more complex structures.

A cutting tool 45 is shown. It should be appreciated that the array of packaged chips 35 in panel 40 is readily diced into individual chips 48 as shown in FIG. 5 .

Referring to FIG. 6, in some embodiments, adjacent chip sockets may have different dimensions, including different sizes and/or different shapes. For example, a processor chip 35 may be disposed in one socket and join a memory chip 55 disposed in an adjacent socket. Thus, a package may include more than one chip, and may include different chips.

The pads 42, 43 may be bonded to the chip through a ball grid array BGA or a land grid array LGA. In the current state of the art, via posts can be about 130 microns long. When the chip 35, 55 is thicker than about 130 microns, it may be necessary to stack one via on top of the other. The technique of stacking vias is known and discussed in co-pending patent applications USSN 13/482,099 and USSN 13/483,185 by Hurwitz et al.

Referring to FIG. 7 , a chip package 48 including a chip 55 in a polymer frame 16 is shown from below such that the chip 55 is surrounded by the frame 16 and through-vias 14 are provided through the frame 16 around the periphery of the chip 55 . The chip is disposed in the socket and held in place by the second polymer 36 . For stability reasons, the frame 16 is usually manufactured from a fiber reinforced preform. The second polymer 36 can be a preform, a polymer film or a molding compound. Generally as shown, through-hole 14 is a simple cylindrical through-hole, but may have different shapes and sizes. Part of the ball grid array of solder balls 57 on chip 55 is connected to through vias 14 through pads 43 in a fan-out configuration. As shown, there may be additional solder balls bonded directly to the substrate below the chip. In some embodiments, at least one through via is coaxial for communication and data processing considerations. In other embodiments, at least one via is a transmission line. Techniques for machining coaxial vias are given, for example, in pending patent application USSN 13/483,185. Techniques for making transmission lines are provided, for example, in USSN 13/483,234.

In addition to providing contact to the chip stack, the through via 14 around the chip can be used to isolate the chip from its surroundings and provide Faraday shielding. This shielded via can be bonded to the pad to interconnect with the shielded via on the chip and provide shielding for the chip.

There may be more than one column of vias surrounding the chip, and the inner column of vias may be used for signal transfer, while the outer column of vias may be used for shielding. The outer columns of vias can be bonded to a solid copper block fabricated on the chip, which can thus be used as a heat sink to dissipate the heat generated by the chip. Different chips can be packaged in this way.

The embedded chip technology described herein using a frame with through vias is particularly suitable for analog processing because the contacts are short and have a relatively small number of contacts per chip.

It should be appreciated that this technique is not limited to packaging IC chips. In some embodiments, the chip includes elements selected from the group consisting of fuses, capacitors, inductors, and filters. Techniques for fabricating inductors and filters are described in co-pending US patent application USSN 13/962,316 by Hurwitz et al.

Referring to Figure 8 and Figures 8(a)-8(l), a method of fabricating a chip socket array surrounded by an organic matrix frame includes the following steps: obtaining a sacrificial carrier 80-8(a).

Optionally, a copper seed layer 82-8(b) is applied on the copper support. An etch stop layer 84 - 8 ( c ) is applied to the carrier, the etch stop layer 84 usually consisting of nickel and usually deposited by vapor phase methods such as sputtering. As an alternative, deposition can be performed by, for example, electroplating or electroless plating. Other candidate materials include tantalum, tungsten, titanium, titanium-tungsten alloys, tin, lead, tin-lead alloys, all of which can be sputtered, and tin and lead can also be electroplated or electroless plated, the barrier metal layer is usually 0.1 to 1 micron thick (each candidate barrier layer material can be removed later using suitable solvent or plasma etch conditions). After the barrier layer is applied, another copper seed layer 86-8(d) is applied. The copper seed layer is typically about 0.2 microns to 5 microns thick.

Steps 8(b)-8(d) are preferred to ensure good adhesion of the barrier layer to the substrate and good adhesion and growth of the vias, and to enable subsequent removal of the substrate by etching without damaging the vias. These steps are optional, and one or more of them may not be used, although for best results these steps are included.

Photoresist layer 88 is then applied - step 8(e), Figure 8(e), and photoresist layer 88 is patterned with a pattern of copper vias - 8(f). Copper is then plated in the pattern 90-8(g), followed by stripping of the photoresist 88-8(h). Upstanding copper vias 90-8(i) are laminated with polymer dielectric 92, which may be a fiber reinforced polymer matrix preform. The laminated via array is thinned and planarized to expose the ends of the copper vias - 8(j). Subsequently, the carrier is removed.

Optionally and preferably, the planarized polymer dielectric-8(k) with exposed copper via ends is protected by applying an etch stop material 94 such as photoresist or a dielectric film prior to etching away the copper carrier 80-8 (l). Typically, the carrier is a copper carrier 80, which can be removed by dissolving the copper. Ammonium hydroxide or copper chloride can be used to dissolve copper.

Next, the carrier layer - 8(m) can be etched away, and the etch protection layer 94 can be removed - step 8(n).

Although not described herein, it should be appreciated that upstanding copper vias can be fabricated by panel plating and selective etching to remove excess copper to leave vias. In fact, as an alternative, the socket can be made by selectively etching away part of the copper panel while masking the vias.

While via post technology is preferred, drill and fill technology can also be used. In another variant method, referring to FIG. 9 , a carrier- 9 ( a ) consisting of a copper clad laminate (CCL) is obtained. CCL has a thickness of 10 to hundreds of micrometers. Usually the thickness is 150 microns. A hole 102-9(b) is drilled through the CCL. The pores 102 may have a diameter of 10 to hundreds of microns. Typically, the pores are 150 microns in diameter.

Next, the vias are plated to form plated through holes 104 - 9 ( c ).

The copper clad laminate 100 is then ground or etched to remove the surface copper layers 106 , 108 , leaving a laminate 110 - 9 (d) with plated through holes (Pth), copper vias 104 .

Sockets 112 - 9 ( e ) for receiving chips are then fabricated on the entire laminate using numerically controlled forming (CNC) or stamping.

As previously mentioned, plated vias deposited in photoresist can be of arbitrary shape and size using the preferred via post technology. In addition, the frame may include more than 2 via layers separated by pads. Referring to FIG. 10 , this flexibility enables the embedding of a copper coil 200 , which typically includes a via post embedded in a dielectric frame 202 around a cavity 204 . By way of example only, coil 200 is shown with three layers of extended via posts 206 , 207 , 208 , which may be via posts deposited on a feature layer. Layers 206 , 207 , 208 are joined together by vertical elements 209 , 210 . The vertical elements 209, 210 may be via posts or feature layers or via posts on feature layers. Coil 200 may, for example, provide Faraday shielding for embedded chips. A transformer can be manufactured if an iron core is deposited in a socket 204 with a frame 202 comprising coils. Thus, the polymer frame with copper vias of the present invention enables fabrication of a full range of frames with copper vias therein for embedding a variety of components.

In practice, copper via coil 200 typically includes elongated via posts joined together by feature layers or elongated feature layers connected by via posts. In general, if via post layers alternate with feature layers, the coil must be built layer by layer.

It will be appreciated by those skilled in the art that the present invention is not limited to the embodiments particularly shown and described hereinabove. The scope of the present invention is limited only by the appended claims and includes combinations and sub-combinations of various technical features described above as well as variations and modifications thereof that can be imagined by those skilled in the art after reading the foregoing.

In the claims, the term "comprising" and its conjugations such as "comprises", "comprising", etc. mean the inclusion of listed elements, but usually does not exclude other elements.

Claims (28)

1. a chip carrier socket array, described chip carrier socket array limit by organic substrate framework, described organic substrate framework surrounds the socket through described organic substrate framework, and described chip carrier socket array also comprises the metal throuth hole grid through described organic substrate framework.

2. chip carrier socket array as claimed in claim 1, wherein each chip carrier socket surround by organic substrate framework, described organic substrate framework comprises the copper vias through described framework.

3. chip carrier socket array as claimed in claim 1, wherein said organic substrate framework also comprises glass fiber bundle.

4. chip carrier socket array as claimed in claim 1, wherein said copper vias is through hole post.

5. chip carrier socket array as claimed in claim 1, wherein the width of each through hole is in the scope of 25 microns to 500 microns.

6. chip carrier socket array as claimed in claim 1, wherein each through hole is columniform and has the diameter in the scope of 25 microns to 500 microns.

7. chip carrier socket array as claimed in claim 1, the framework wherein surrounding at least one socket comprises through hole post alternately and characteristic layer, and comprises at least one through hole post layer and a characteristic layer.

8. chip carrier socket array as claimed in claim 1, the metal throuth hole grid wherein through described organic substrate framework comprises multiple via layer.

9. chip carrier socket array as claimed in claim 7, the framework wherein surrounding at least one socket comprises the continuous coil of through hole post alternately and characteristic layer, and described continuous coil crosses at least one through hole post layer and a characteristic layer.

10. chip carrier socket array as claimed in claim 7, wherein said through hole post comprises elongated through hole post.

11. chip carrier socket arrays as claimed in claim 9, the continuous coil that wherein slightness hole post is formed crosses over multiple through hole post layer.

12. chip carrier socket arrays as claimed in claim 1, comprise the adjacent chips socket with different overall dimension.

13. chip carrier socket arrays as claimed in claim 12, comprise the adjacent chips socket with different size.

14. chip carrier socket arrays as claimed in claim 12, comprise and have difform adjacent chips socket.

15. 1 kinds of panels comprising chip carrier socket array, each chip carrier socket surround by organic substrate framework and limit, described organic substrate framework comprises the copper vias grid through described organic substrate framework, wherein said panel comprises at least one region of the socket of the first group of overall dimension had for receiving first kind chip, and has the second area of socket of second group of overall dimension for receiving Second Type chip.

16. 1 kinds of methods manufacturing the chip carrier socket array surrounded by organic substrate framework, comprising:

Obtain sacrificial carrier;

Lay photoresist layer and described photoresist layer pattern is turned to and there is copper vias grid;

Plated copper in described grid;

Use polymer dielectric layer pressure;

Thinning and planarization is carried out to expose the end of copper vias to described polymeric dielectric;

Remove described carrier; And

Machine-building chip carrier socket in described polymeric dielectric.

17. methods as claimed in claim 16, wherein said carrier is copper carrier, and it is by being removed copper dissolution.

18. methods as claimed in claim 16, before being also included in the described copper vias of deposition, apply etch stop layer on the carrier.

19. methods as claimed in claim 16, wherein said etch stop layer comprises nickel.

20. methods as claimed in claim 16, wherein while etching away copper carrier, utilize the protection of etching barrier material to have the planarizing polymer dielectric of the copper vias column end of exposure.

21. methods as claimed in claim 20, wherein said etching barrier material is photoresist.

22. method as claimed in claim 18, wherein electro-coppering Seed Layer on described nickel.

23. methods as claimed in claim 18, wherein before nickel deposited barrier layer, electro-coppering Seed Layer.

24. methods as claimed in claim 16, wherein by be selected from by stamp out socket and retain formed framework or shaping by numerical control in one carry out grid described in machine-building.

25. 1 kinds of methods manufacturing the chip carrier socket array surrounded by organic substrate framework, comprising:

Obtain sacrificial carrier;

Lay photoresist layer and described photoresist layer pattern is turned to and there is copper vias post grid and chip carrier socket array;

Plated copper in described grid;

Use polymer dielectric layer pressure;

Thinning and planarization is carried out to expose the end of copper vias and described array to described polymeric dielectric;

Cover the end of described copper vias post;

Dissolve described array; And

Remove described carrier.

26. methods as claimed in claim 25, wherein said through hole post is elongated through hole post, and at least one chip carrier socket had the organic substrate framework of embedded metal structure surround, described embedded metal structure comprises at least one elongated through hole post and at least one characteristic layer.

27. methods as claimed in claim 25, wherein said elongated through hole post and characteristic layer comprise continuous coil.

28. methods as claimed in claim 25, wherein at least one socket by organic frame and be embedded in multi-layer metal structure in described organic frame surround, described multi-layer metal structure comprises the through hole post layer of multiple extension, every a pair adjacent through hole post layer is separated by characteristic layer, and described multi-layer metal structure comprise continuous coil.