CN104299581B - Display and grid drive circuit thereof - Google Patents

Abstract

The invention discloses a display and a gate driving circuit thereof. The gate drive circuit includes a logic control circuit and M latch circuits. where M is an integer greater than 1. The logic control circuit is coupled to the M scan lines of the display and is used to change the voltage level of one of the M scan lines from the first voltage level to the second voltage level based on the digital signal and the clock signal. bit, and make the voltage levels of other scan lines among the M scan lines be the first voltage level. Each latch circuit is coupled to the logic control circuit and a corresponding scan line among the M scan lines, and is used to latch the corresponding scan line when the voltage level of the corresponding scan line is at the first voltage level. The voltage level of the scan line.

Description

Display and its gate drive circuit

technical field

The present invention relates to a display and its gate driving circuit, in particular to a display with multiple latch circuits and its gate driving circuit.

Background technique

Liquid crystal displays (LCDs) have been developed for many years. The development of early LCD TVs focused on light weight and small size, and successfully replaced bulky and bulky cathode image tube displays (cathode raytube displays). In recent years, with the development of memory in pixel (MIP) technology, the function of only changing any part of the image data has been paid more and more attention. In addition, the shift register (shift register) in the traditional gate driver is limited by the signal transmission from the first stage, so it is not suitable for the products of memory pixel (MIP) technology. Therefore, it is generally replaced by a decoder circuit, so that only any part of the picture data can be changed and power consumption can be reduced.

Please refer to FIG. 1 , which is a circuit diagram of a conventional decoding circuit 10 for a gate driver. The decoding circuit 10 has a plurality of output terminals O ₁ to O ₇ , and each of the output terminals O ₁ to O ₇ is coupled to a corresponding scan line in the display. The decoding circuit 10 will make one of the output terminals O ₁ to O ₇ output a gate high potential according to the digital signal comprising three bits A ₀ , A ₁ and A ₂ , and make the other output terminals be gate high. Very low potential. The decoding circuit 10 includes a plurality of inverters 12 for respectively inverting the three bits A ₀ , A ₁ and A ₂ and outputting them. The decoding circuit 10 further includes a plurality of AND gates 14, coupled to the input end of the decoding circuit 10 and the inverter 12, for comparing the bits A ₀ , A ₁ and A ₂ and the bits A ₀ , A ₁ and A ₂ The inverse phase element of the circuit is operated to output the high potential of the gate to the scanning line to be driven.

However, conventional decoding circuits use a large number of logic gates, and the number of transistors required will increase significantly with the increase of display resolution. Furthermore, every time the resolution of the display is doubled, each circuit of the gate driver of the display for controlling the voltage level of the scan line needs to add an AND gate (AND), and each AND gate will Six transistors are used. Taking the decoding circuit 10 of FIG. 1 as an example, when its resolution is multiplied, that is, when it is increased from eight output terminals to sixteen output terminals, each of the original output terminals O ₁ to O ₇ must be additionally In addition to setting one more AND gate, each of the newly added eight output terminals must also be provided with three AND gates. In other words, when the decoding circuit 10 increases from eight output terminals to sixteen output terminals, at least 192 (ie (8x1+8x3)x6) transistors need to be added. Therefore, as far as the existing decoding circuit is concerned, the number of transistors required is quite large.

Contents of the invention

An embodiment of the invention provides a gate driving circuit. The gate driving circuit includes a logic control circuit and M latch circuits. The logic control circuit is coupled to the M scanning lines, and is used to change the voltage level of one of the M scanning lines from the first voltage level to the second voltage level according to the digital signal and the clock signal, And make the voltage levels of other scan lines in the above M scan lines be the first voltage level. Wherein M is an integer greater than 1. Each latch circuit is coupled to the logic control circuit and a corresponding scan line among the M scan lines, and is used to latch the corresponding scan line when the voltage level of the corresponding scan line is at the first voltage level. The voltage level of the scan line.

An embodiment of the invention provides a display. The display includes a plurality of data lines, a plurality of scanning lines, a plurality of pixels, at least one source driving circuit and the aforementioned gate driving circuit. Wherein, each pixel is coupled to a corresponding data line and a corresponding scan line. The at least one source driver circuit is coupled to the plurality of data lines for transmitting data signals to the pixels through the plurality of data lines.

Description of drawings

Figure 1 is a circuit diagram of an existing decoding circuit for a gate driver.

FIG. 2 is a schematic diagram of a display according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of pixels of the display shown in FIG. 2 .

FIG. 4 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.

FIG. 5 is a timing diagram of the gate driving circuit of FIG. 4 .

FIG. 6 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.

FIG. 7 is a timing diagram of the gate driving circuit of FIG. 6 .

8 to 11 are circuit diagrams of latch circuits according to different embodiments of the present invention.

Among them, reference signs:

10 decoding circuit

12, 142, 162 inverters

14 AND gate

16 pixels

18 memory cells

100 monitors

110 pixel array

120 source drive circuit

130 gate drive circuit

130A, 130B gate drive circuit

140A, 140B logic control circuit

144 inputs

150 switch modules

152 First stage circuit

154 Second stage circuit

156 Tertiary circuits

160, 160A, 160B, 160C, 160D Latch Circuits

C1 capacitor

CK clock signal

/CK Inverted signal of clock signal CK

C _P pixel capacitance

A ₀ , A ₁ , A ₂ , D0, D1, D2 bits

/D0, /D1, /D2 Inverted phase elements

D _P pixel data

G ₁ to G _M , G _y scan lines

IN input terminal

N1 second switch

N2, N3, N4, N5, N6 switches

O ₁ to O ₇ outputs

P1 first switch

P2, P3, P4, P5, P6 switches

Q pixel switch

R resistance

S ₁ to S _P , S _x data line

T clock period

t1, t2, t3, t4, t5, t6 periods

V _COM common electrode

VGL first voltage level; gate low potential

VGH second voltage level; gate high potential

detailed description

First of all, it should be understood that the gate driving circuit disclosed in the present invention is not only suitable for general liquid crystal displays, but also suitable for displays using memory in pixel (MIP) technology. Please refer to Figure 2 and Figure 3. FIG. 2 is a schematic diagram of a display 100 according to an embodiment of the present invention, and FIG. 3 is a schematic diagram of a pixel 16 of the display 100 of FIG. 2 . The display 100 includes a plurality of data lines S ₁ to S _P , a plurality of scan lines G ₁ to G _M , a pixel array 110 , at least one source driver circuit 120 and a gate driver circuit 130 , and the pixel array 110 includes a plurality of pixels 16 . Wherein, both P and M are integers greater than 1. In this embodiment, the display 100 adopts memory pixel (MIP) technology, and each pixel 16 has a memory unit 18 and a pixel capacitor C _P . The memory unit 18 is coupled to the pixel capacitor C _P for receiving pixel data D _P from one of the data lines S _x of the plurality of data lines S ₁ to _{SP and storing the received pixel data D P .} In this way, the pixel 16 can switch the polarity of the pixel capacitor C _P according to the pixel data D _P stored in the memory unit 18 . Therefore, when the gray scale to be displayed by the pixel 16 remains unchanged, the pixel 16 does not need to receive new pixel data D _P from the source driver circuit 120 , but can adjust the pixel capacitance C according to the pixel data D _P stored in the memory unit 18 _P performs polarity inversion.

Please refer to FIG. 4 and FIG. 5 , FIG. 4 is a circuit diagram of a gate driving circuit 130A according to an embodiment of the present invention, and FIG. 5 is a timing diagram of the gate driving circuit 130A in FIG. 4 . The gate driving circuit 130A includes a logic control circuit 140A and M latch circuits 160 . Wherein, M is an integer greater than 1, and in this embodiment, M=8. It should be understood that in other embodiments of the present invention, M may be other positive integers greater than 1, and its magnitude depends on the number of scan lines of the display to be driven. In addition, the logic control circuit 140A is coupled to the scan lines G ₁ to G ₈ , and is used to make the scan lines G ₁ to G ₈ according to the clock signal CK and the digital signal including three bits D0, D1 and D2. The voltage level of one of the scanning lines is changed from the first voltage level VGL to the second voltage level VGH, and the voltage levels of the other scanning lines _G1 to _G8 are the first voltage level VGL . For example, when the bits D0, D1, and D2 are "0", "0", and "0" respectively, the voltage level of the scan line G1 will change from the _first voltage level VGL to the second voltage level VGH, and the voltage levels of the other scanning lines G2 to _G8 will be the first voltage level VGL; and for example, when the bits D0, D1 and D2 are " ₁ ", "0", and "0" respectively , the voltage level of the scanning line G1 will change from the _first voltage level VGL to the second voltage level VGH, and the voltage levels _of the other scanning lines _G1 , G3 to _G8 will be the first voltage level VGL; for another example, when the bits D0, D1 and D2 are “0”, “1” and “0” respectively, the voltage level _of the scanning line G3 will be changed from the first voltage level VGL to the second voltage level VGH, and the voltage levels of the other scan lines G ₁ , G ₂ , G ₄ to G ₈ are the first voltage level VGL; and so on. The different combinations of the values of the bits D0, D1 and D2 and the corresponding driven scan lines can refer to the following Table 1.

D0 D1 D2 The voltage level is converted to the scan line of VGH 0 0 0 G ₁ 0 0 1 _G2 0 1 0 G ₃ 0 1 1 G ₄ 1 0 0 G ₅ 1 0 1 G ₆ 1 1 0 G ₇ 1 1 1 G ₈

Table 1

In this embodiment, the first voltage level VGL is the gate low potential, and the second voltage level VGH is the gate high potential, but the invention is not limited thereto. In addition, each latch circuit 160 of the gate driving circuit 130A is coupled to the logic control circuit 140A and a corresponding scan line among the scan lines _G1 to _G8 , for when the voltage level of the corresponding scan line is at the first When a voltage level VGL is reached, the voltage level of the corresponding scanning line is latched, so as to avoid unintended changes to the pixel ₁₆ due to unexpected changes in the voltage levels of the scanning lines _G1 to G8. drive. The operation of the latch circuit 160 will be further described below.

In this embodiment, the clock signal CK rises from the first voltage level VGL to the second voltage level VGH in each clock cycle T, and then drops from the second voltage level VGH to the first voltage level. VGL. In addition, the value of bit D0 is switched every other clock cycle T (from "0" to "1", or from "1" to "0"), and the value of bit D1 is switched every two clock cycles. The pulse period T (ie 2T) is switched once, and the value of the bit D2 is switched every four clock periods T (ie 4T). According to the waveform in FIG. 5 , the voltage level of the bit D0 will switch from the first voltage level VGL to the second voltage level VGH every other clock period T, or switch from the second voltage level VGH to the second voltage level VGH. The first voltage level VGL; the voltage level of the bit D1 will switch from the first voltage level VGL to the second voltage level VGH every two clock cycles T (ie 2T), or from the second voltage level The bit VGH is switched to the first voltage level VGL; and the voltage level of the bit D2 is switched from the first voltage level VGL to the second voltage level VGH every four clock cycles T (ie 4T), or Switch from the second voltage level VGH to the first voltage level VGL. _In this way, the voltage levels of the scan lines _G1 to G8 can be sequentially raised to the second voltage level VGH. Therefore, the gate driving circuit 130A can generate scan line signals with the same timing as the conventional gate driver with a shift register, so the gate driving circuit 130A is suitable for driving a general liquid crystal display. In addition, by controlling the values of the three bits D0, D1 and D2, the voltage level of a specific scan line among the scan lines _G1 to _G8 can be set to the second voltage level VGH, so as to couple Here, the pixels 16 of a specific scanning line are driven, so the gate driving circuit 130A is also suitable for driving a display using memory pixel (MIP) technology.

Please refer to FIG. 4 again. In this embodiment, the logic control circuit 140A is controlled by a digital signal including three bits D0, D1 and D2, and the logic control circuit 140A includes a first-stage circuit 152 and a second-stage circuit 154. and the third-stage circuit 156 have a total of three stages of circuits. Wherein, the first stage circuit 152, the second stage circuit 154 and the third stage circuit 156 each include a plurality of switch modules 150, and the switch modules 150 of each stage circuit are controlled by one of the three bits D0, D1, D2 Corresponding bit. In detail, the two switch modules 150 included in the first stage circuit 152 are controlled by the bit D2, the four switch modules 150 included in the second stage circuit 154 are controlled by the bit D1, and the third stage circuit 154 The included eight switch modules 150 are controlled by bit D2. Wherein, the second stage circuit 154 is coupled between the first stage circuit 152 and the third stage circuit 156 . In addition, the clock signal CK is input to the logic control circuit 140A by the input terminal 144 of the logic control circuit 140A, and each switch module 150 of the first stage circuit 152 is coupled to the input terminal 144 and four switch modules of the second stage circuit 154 Two switch modules 150 in 150. Each switch module 150 of the second stage circuit 154 is coupled to one switch module 150 of the two switch modules 150 of the first stage circuit 152 and four switch modules 150 of the eight switch modules 150 of the third stage circuit 156 .

In an embodiment of the present invention, the first-stage circuit 152, the second-stage circuit 154, and the third-stage circuit 156 may each include an inverter 142 for inverting the corresponding bits received by the circuits of each stage, so as to Outputs the inverse of the corresponding bit. In detail, the inverter 142 of the first-stage circuit 152 is used to invert the bit D2 to output the inverted phase element of the bit D2; the inverter 142 of the second-stage circuit 154 is used to invert the bit D1 inverting to output the inverse of the bit D1; and the inverter 142 of the third stage circuit 156 is used to invert the inversion of the bit D0 to output the inverse of the bit D0. In addition, each switch module 150 may include a first switch P1 and a second switch N1, and the first switch P1 and the second switch N1 are controlled by a corresponding bit and the inverse of the corresponding bit in the digital signal . Specifically, the first switch P1 and the second switch N1 of each switch module 150 of the first stage circuit 152 are respectively controlled by the bit D2 and the opposite phase element of the bit D2; each of the second stage circuit 154 The first switch P1 and the second switch N1 of the switch module 150 are respectively controlled by the bit D1 and the opposite phase element of the bit D1; the first switch P1 and the second switch of each switch module 150 of the third stage circuit 156 N1 is controlled by the bit D0 and the inverse bit of the bit D0 respectively. In this embodiment, the first switch P1 is a P-type transistor (eg, a P-type thin film transistor), and the second switch N1 is an N-type transistor (eg, an N-type thin film transistor).

According to the above-mentioned circuit structure and control method of the logic control circuit 140A, every time the resolution of the display is doubled, each circuit of the logic control circuit 140A for controlling the voltage level of the scanning line only needs to add a switch module 150 . Therefore, compared with each AND gate 14 of the existing decoding circuit 10 needing to use six transistors, each switch module 150 of the logic control circuit 140A only needs to use two transistors, so the wiring method of the logic control circuit 140A It is simpler and requires less wiring area.

Please refer to FIG. 6 and FIG. 7 , FIG. 6 is a circuit diagram of a gate driving circuit 130B according to another embodiment of the present invention, and FIG. 7 is a timing diagram of the gate driving circuit 130B in FIG. 6 . The gate driving circuit 130B includes a logic control circuit 140B and M latch circuits 160 . Wherein, M is an integer greater than 1, and in this embodiment, M=8. It should be understood that M can be other positive integers greater than 1, and its size depends on the number of scan lines of the display to be driven. Similar to the logic control circuit 140A, the logic control circuit 140B is also coupled to the scan lines G ₁ to G ₈ , and is used to control the scan lines according to the clock signal CK and the digital signal including three bits D0, D1 and D2 _The voltage level of one of the scanning lines _G1 to G8 is changed from the first voltage level VGL to the second voltage level VGH, and the voltage level of the other scanning lines _G1 to _G8 is the first voltage level VGL. For example, when the bits D0, D1, and D2 are "0", "0", and "0" respectively, the voltage level of the scan line G1 will change from the _first voltage level VGL to the second voltage level VGH, and the voltage levels of the other scan lines G2 to _G8 are the first voltage level _VGL . Please refer to Figure 7 and Figure 5 at the same time. In this embodiment, the timing diagram of the gate driving circuit 130B is exactly the same as that of the gate driving circuit 130A. In other words, according to the clock signal CK and according to the digital signal including three bits D0, D1 and D2, the gate driving circuit 130B can sequentially raise the voltage levels of the scanning lines _G1 to _G8 to the second voltage level. Bit VGH. In addition, by controlling the values of the three bits D0, D1 and D2, the gate driving circuit 130B can set the voltage level of a specific scanning line among the scanning lines _G1 to _G8 as the second voltage level. VGH is used to drive the pixel 16 coupled to the specific scan line, so the gate driving circuit 130B is also suitable for driving a display using memory pixel (MIP) technology. Therefore, the scan lines driven by the gate driving circuit 130B and the corresponding values of the bits D0 , D1 and D2 can also refer to the above-mentioned Table 1 . In addition, the function of the latch circuit 160 in the gate driving circuit 130B is the same as that in the gate driving circuit 130A, and the operation of the latch circuit 160 will be described in the following description.

Please refer to FIG. 6 again. In this embodiment, the logic control circuit 140B is controlled by a digital signal including three bits D0, D1 and D2, and each of the scan lines _G1 to _G8 is coupled to The three switch modules 150 of the logic control circuit 140B, and each switch module 150 of the three switch modules 150 is respectively controlled by a different bit of the digital signal. When the voltage level of any scan line changes from the first voltage level VGL to the second voltage level VGH, the three switch modules 150 coupled to the scan line are all turned on, so that the clock signal CK passes through The three switch modules 150 coupled to the scan line transmit to the scan line. For example, the three switch modules 150 coupled to the scan line _G1 are respectively controlled by the bits D0, D1 and D2. When the bits D0, D1, and D2 are all "0", the three switch modules 150 coupled to the scan line _G1 will be turned on, and the pulse signal CK will pass through the three switch modules coupled to the scan line _G1 . 150 is transmitted to scan line G ₁ . In addition, in other embodiments of the present invention, the three bits D0, D1, and D2 are inverted first, so as to generate the inverted bits /D0, /D1, and /D2 of the bits D0, D1, and D2. Each switch module 150 may include a first switch P1 and a second switch N1, and the first switch P1 and the second switch N1 are controlled by a corresponding bit and an inverse bit of the corresponding bit in the digital signal.

According to the circuit structure and control method of the logic control circuit 140B in FIG. 6, every time the resolution of the display is doubled, each circuit of the logic control circuit 140B for controlling the voltage level of the scanning line only needs to add a switch module. 150. Therefore, compared with the need to use six transistors for each AND gate 14 of the existing decoding circuit 10, each switch module 150 of the logic control circuit 140B only needs to use two transistors, so the wiring method of the logic control circuit 140B It is simpler and requires less wiring area.

The operation of the above-mentioned latch circuit 160 will be described below with multiple embodiments. Please refer to FIG. 8 , which is a circuit diagram of a latch circuit 160A according to an embodiment of the present invention. The input terminal IN of the latch circuit 160A is coupled to the logic control circuit 140A or 140B, and the output terminal of the latch circuit 160A is coupled to one scan line G _y among the multiple scan lines G ₁ to G _M of the display 100, where y is an integer, and 1≦y≦M. The latch circuit 160A includes a capacitor C1 and two switches P2 and N2. In this embodiment, the switches P2 and N2 may be P-type transistors (eg, P-type thin film transistors) and N-type transistors (eg, N-type thin film transistors), respectively. For the sake of illustration, it is assumed here that the scan line G _y is the first scan line G ₁ , that is, y=1. Please refer to Figure 8, and refer to Table 1 and Figure 5 or Figure 7 at the same time. During the period t1, since the bits D0, D1 and D2 are all "0", the clock signal CK is input to the latch circuit 160A through the input terminal IN. At this moment, because the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, so that both ends of the capacitor C1 are biased by the first voltage level VGL.

During the period t2, since the bits D0, D1 and D2 are all "0", the clock signal CK is input to the latch circuit 160A through the input terminal IN. In addition, because the voltage level of the clock signal CK is the second voltage level VGH, the switches P2 and N2 are turned off. At this time, the voltage level of the scan line _G1 is the second voltage level VGH, and the capacitor C1 is charged because both ends of the capacitor C1 are respectively biased by the first voltage level VGL and the second voltage level VGH.

During the period t3 , since the bits D0 , D1 and D2 are all “0”, the clock signal CK is input to the latch circuit 160A through the input terminal IN. At this time, because the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, and the capacitor C1 is discharged because both ends of the capacitor are biased by the first voltage level VGL. .

During the period t4, because the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch circuit through the input terminal IN 160A. At this time, because the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, so that the scanning line _G1 is biased by the first voltage level VGL, and the scanning line G The voltage level of ₁ is latched at the first voltage level VGL.

During the period t5, because the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch circuit through the input terminal IN 160A. At this time, because the voltage level of the clock signal CK is the second voltage level VGH, the switches P2 and N2 are turned off, and the scanning line _G1 is in a floating state.

During the period t6, because the bit D0 is "1", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot be input to the latch circuit through the input terminal IN 160A. At this time, because the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, so that the scanning line _G1 is biased by the first voltage level VGL, and the scanning line G The voltage level of ₁ is latched at the first voltage level VGL.

Please refer to FIG. 9 , which is a circuit diagram of a latch circuit 160B according to another embodiment of the present invention. The input terminal IN of the latch circuit 160B is coupled to the logic control circuit 140A or 140B, and the output terminal of the latch circuit 160B is coupled to one scan line G _y among the plurality of scan lines G ₁ to G _M of the display 100 . The latch circuit 160B includes a resistor R, one end of the resistor R is coupled to the scan line G _y , and the other end of the resistor R is biased by the first voltage level VGL. The resistor R has a very large resistance value (generally between 400KΩ~600KΩ), so the clock signal CK is input to the latch circuit 160B through the input terminal IN, and the voltage level of the clock signal CK is the second voltage level VGH , the voltage level of the scan line G _y will be converted to the second voltage level VGH, and at the same time, the current flowing through the resistor R will not be too large. In addition, when the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the scan line Gy is biased by the first voltage level _VGL through the resistor R, so that the scan line at this time The voltage level of G _y is latched at the first voltage level VGL.

Please refer to FIG. 10 , which is a circuit diagram of a latch circuit 160C according to yet another embodiment of the present invention. The input terminal IN of the latch circuit 160C is coupled to the logic control circuit 140A or 140B, and the output terminal of the latch circuit 160C is coupled to one scan line G _y among the multiple scan lines G ₁ to G _M of the display 100 . The latch circuit 160C includes a capacitor C1, an inverter 162, switches P2, P3, N2 and N3. In this embodiment, the switches P2 and P3 are P-type transistors (eg, P-type thin film transistors), and the switches N2 and N3 are N-type transistors (eg, N-type thin film transistors). When the clock signal CK is input to the latch circuit 160B through the input terminal IN, and the voltage level of the clock signal CK is the second voltage level _VGH , the voltage level of the scanning line Gy will be converted to the second voltage level. VGH. When the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the voltage level of the scanning line Gy drops to the first voltage level _VGL due to the discharge of the capacitor C1, and the switch P3 is turned on, so that the scan line G _y is biased by the first voltage level VGL. At this time, the inverter 162 outputs a high potential, so that the switch N3 is also turned on. In addition, when the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on. Therefore, when the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, the voltage level of the scan line Gy will be latched at the first voltage level _VGL .

Please refer to FIG. 11 , which is a circuit diagram of a latch circuit 160D according to an embodiment of the present invention. The input terminal IN of the latch circuit 160D is coupled to the logic control circuit 140A or 140B, and the output terminal of the latch circuit 160D is coupled to one scan line G _y among the multiple scan lines G ₁ to G _M of the display 100, where y is an integer, and 1≦y≦M. The latch circuit 160D includes a capacitor C1, three inverters 162, 164 and 166, and a plurality of switches P2 to P6 and N2 to N6. In this embodiment, the switches P2 to P6 are P-type transistors (eg, P-type thin film transistors), and the switches N2 to N6 are N-type transistors (eg, N-type thin film transistors). For the sake of illustration, it is assumed here that the scan line G _y is the first scan line G ₁ , that is, y=1. Please refer to Figure 11, and refer to Table 1 and Figure 5 or Figure 7 at the same time. During the period t1, since the bits D0, D1 and D2 are all “0” and /D0 is “1”, the clock signal CK is input to the latch circuit 160A from the input terminal IN, and the switches P3 and N4 are turned on. is turned on, and switches P5 and N6 are turned off. At this time, because the voltage level of the clock signal CK is the first voltage level VGL, the switches P2, N2, and P4 are turned on, and the switch N3 is turned off, so that both ends of the capacitor C1 are subjected to the first voltage level VGL. and the voltage level of the input terminal of the inverter 164 is the second voltage level VGH due to the turning on of the switches P3 and P4, which causes the switch P6 to turn on and the switch N5 to turn off. Since the switches P2 and N2 are turned on, the voltage level of the input terminal of the inverter 164 is the second voltage level VGH, and because the voltage level of the clock signal CK is the first voltage level VGL, the input of the scan line G _y The voltage level of the terminal is the first voltage level VGL.

During the period t2, since the bits D0, D1 and D2 are all "0" and /D0 is "1", the clock signal CK is input to the latch circuit 160A from the input terminal IN, and the switches P3 and N4 are turned on. is turned on, and switches P5 and N6 are turned off. At this time, because the voltage level of the clock signal CK is the second voltage level VGH, the switches P2, N2, and P4 are turned off, and the switch N3 is turned on, so that both ends of the capacitor C1 are respectively subjected to the second voltage level. VGH is charged with the bias voltage of the first voltage level VGL, and the voltage level of the input terminal of the inverter 164 is the first voltage level VGL due to the opening of the switches N3 and N4, and causes the switch N5 to be turned on and the switch P6 to be turned off . Since the voltage level of the input terminal of the inverter 164 is the first voltage level _VGL , the voltage level of the input terminal of the scan line Gy is the second voltage level VGH.

During the period t3, since the bits D0, D1 and D2 are all "0" and /D0 is "1", the clock signal CK is input to the latch circuit 160A from the input terminal IN, and the switches P3 and N4 are turned on. is turned on, and switches P5 and N6 are turned off. At this time, because the voltage level of the clock signal CK is the first voltage level VGL, the switches P2, N2, and P4 are turned on, and the switch N3 is turned off, so that both ends of the capacitor C1 are subjected to the first voltage level. The bias voltage of VGL is discharged, and the voltage level of the input terminal of the inverter 164 is the second voltage level VGH due to the turn-on of the switches P3 and P4, which results in the turn-on of the switch P6 and the turn-off of the switch N5. Since the switches P2 and N2 are turned on, the voltage level of the input terminal of the inverter 164 is the second voltage level VGH, and because the voltage level of the clock signal CK is the first voltage level VGL, the input of the scan line G _y The voltage level of the terminal is the first voltage level VGL.

During the period t4, because the bit D0 is "1" and /D0 is "0", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot pass through the input The terminal IN is input to the latch circuit 160D. In addition, since /D0 is "0", the switches P5 and N6 are turned on, and the switches P3 and N4 are turned off. In addition, due to the effect of the capacitor C1, the voltage level of the input terminal IN is maintained at the first voltage level VGL, so that the switch P4 is turned on and the switch N3 is turned off. At this time, because the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned on, so that the scanning line _G1 is biased by the first voltage level VGL, and the switch P6 is turned on. And the switch N5 is closed. Because the switches P5 and P6 are turned on, the input terminal of the inverter 164 is biased by the second voltage level VGH, so that the output of the inverter 164 is at the _first voltage level VGL, so the voltage of the scan line G1 is at the same level as The bit is latched at the first voltage level VGL.

During the period t5, because the bit D0 is "1" and /D0 is "0", the electrical connection between the input terminal IN and the logic control circuit 140A or 140B is cut off, so that the clock signal CK cannot pass through the input The terminal IN is input to the latch circuit 160D. In addition, since /D0 is "0", the switches P5 and N6 are turned on, and the switches P3 and N4 are turned off. In addition, due to the effect of the capacitor C1, the voltage level of the input terminal IN is maintained at the first voltage level VGL, so that the switch P4 is turned on and the switch N3 is turned off. At this time, because the voltage level of the clock signal CK is the first voltage level VGL, the switches P2 and N2 are turned off, which causes the switch P6 to be turned on and the switch N5 to be turned off. Because the switches P5 and P6 are turned on, the input terminal of the inverter 164 is biased by the second voltage level VGH, so that the output of the inverter 164 is at the _first voltage level VGL, so the voltage of the scan line G1 is at the same level as The bit is latched at the first voltage level VGL.

During the period t6, because the bit D0 is "1", /D0 is "0", and the voltage level of the clock signal CK is the first voltage level VGL, the operation mode of the latch circuit 160D at this time is the same as that of the period t6. During the same operation, the voltage level of the scan line G1 is latched at the _first voltage level VGL.

Since the latch circuits 160A to 160B will latch the voltage level of the scan line G _y when the voltage level of the scan line G _y is at the first voltage level _VGL , it is possible to avoid The voltage level of the pixel 16 has an unexpected change, and the pixel 16 is driven in an unexpected way. Therefore, the image quality of the display 100 can be further ensured.

In summary, since the display and its gate drive circuit of the present invention adopt a new circuit architecture, when the resolution of the display is doubled, each gate drive circuit is used to control the voltage level of the scanning line The circuit requires only two more transistors. Therefore, compared with the need to use six transistors for each AND gate (AND) of the existing decoding circuit, the wiring method of the logic control circuit of the gate drive circuit of the present invention is simpler, and the required wiring area is also reduced. smaller. In addition, since the latch circuit of the gate driving circuit of the present invention latches the voltage level of the scan line when the voltage level of the scan line is at the first voltage level, it can avoid Bits produce unexpected changes, so that the quality of the display is guaranteed.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the protection scope of the claims of the present invention shall fall within the scope of the present invention.

Claims (8)

1. A gate drive circuit, characterized in that, comprising: A logic control circuit, coupled to the M scanning lines, is used to change the voltage level of one of the scanning lines from a first voltage level to a first voltage level according to a digital signal and a clock signal two voltage levels, and make the voltage levels of other scan lines in the scan lines be the first voltage level, wherein M is an integer greater than 1; and M latch circuits, each latch circuit is coupled to the logic control circuit and a corresponding scan line among the scan lines, and is used for making the voltage level of the corresponding scan line be at the first voltage level When the bit is set, the voltage level of the corresponding scan line is latched; The digital signal is an N-bit digital signal, N is an integer greater than 1, and each scanning line is coupled to N switch modules of the logic control circuit, and the N switch modules are controlled by different bit; The clock signal is input to the logic control circuit from an input terminal of the logic control circuit, and when the voltage level of any scan line changes from the first voltage level to the second voltage level, any The N switch modules coupled to one scan line are all turned on, so that the clock signal is transmitted to any scan line through the N switch modules coupled to any one scan line. 2. The gate drive circuit according to claim 1, wherein each switch module comprises a first switch and a second switch, and the first switch and the second switch of each switch module are controlled by A corresponding bit and an inverse of the corresponding bit in the digital signal. 3. The gate drive circuit according to claim 1, wherein each latch circuit comprises: a switch element, coupled to a corresponding scan line and a system voltage, and controlled by the clock signal; and A capacitor is coupled between the corresponding scan line and a bias voltage. 4. The gate driving circuit as claimed in claim 1, wherein each latch circuit comprises a resistor coupled between a corresponding scan line and a bias voltage. 5. A display, characterized in that it comprises: Multiple data lines; Multiple scan lines; a plurality of pixels, each of which is coupled to a corresponding data line and a corresponding scan line; at least one source driver circuit, coupled to the data lines, for transmitting data signals to the pixels through the data lines; and The gate drive circuit as claimed in claim 1. 6. The display device according to claim 5, wherein each of the pixels has a memory unit and a pixel capacitor, and the memory unit is coupled to the pixel capacitor for data from one of the data lines The line receives a pixel data and stores the pixel data, so as to convert the polarity of the pixel capacitance according to the pixel data stored in the memory unit. 7. A gate drive circuit, characterized in that it comprises: A logic control circuit, coupled to the M scanning lines, is used to change the voltage level of one of the scanning lines from a first voltage level to a first voltage level according to a digital signal and a clock signal two voltage levels, and make the voltage levels of other scan lines in the scan lines be the first voltage level, wherein M is an integer greater than 1; and M latch circuits, each latch circuit is coupled to the logic control circuit and a corresponding scan line among the scan lines, and is used for making the voltage level of the corresponding scan line be at the first voltage level When the bit is set, the voltage level of the corresponding scan line is latched; The digital signal is an N-bit digital signal, and N is an integer greater than 1. The logic control circuit includes N-level circuits, wherein each of the N-level circuits includes a plurality of switch modules, and each The switching modules of the stage circuit are controlled by a corresponding bit in the digital signal. 8. The gate driving circuit according to claim 7, wherein the clock signal is input to the logic control circuit by an input end of the logic control circuit; Wherein the first-level circuit in the N-level circuit includes two switch modules, the second-level circuit in the N-level circuit includes four switch modules, the third-level circuit in the N-level circuit includes eight switch modules, and The second-level circuit is coupled between the first-level circuit and the third-level circuit; Wherein each switch module of the first stage circuit is coupled to the input terminal of the logic control circuit and two switch modules among the four switch modules of the second stage circuit; Each switch module of the second stage circuit is coupled to one switch module of the two switch modules of the first stage circuit and four switch modules of the eight switch modules of the third stage circuit.