CN104318958A - Method for replacing an integrated circuit memory device in an application - Google Patents

Abstract

The invention discloses a method for replacing an integrated circuit memory device in an application, which comprises the following steps: providing a system configured to be compatible with a first integrated circuit memory device type having a first memory device identification code; providing a second integrated circuit memory device type without the first memory device identification code; configuring the second IC memory device type to have the at least part of the first memory device identification code; and integrating the second integrated circuit memory device type with the system. The disclosed storage device identification code is programmable. In some embodiments, a plurality of device identification codes are stored in the integrated circuit, and a plurality of device identification selection codes are also stored in the integrated circuit.

Description

Method for replacing an integrated circuit memory device in an application

This application is a divisional application, the application number of the parent application: 201110072510.6, the application date: March 17, 2011, and the name: integrated circuit storage device and its replacement and manufacturing method.

technical field

The present invention relates to a programmable identification code for an integrated circuit device, in particular an integrated circuit memory device, a method of replacing an integrated circuit memory device in an application, and a method of manufacturing the integrated circuit memory device.

Background technique

Each memory device has an identification code that represents a memory type, density, manufacturer, or even other important parameters that need to be known by the system. Typically, these IDs are stored by the antifuse and cannot be changed. If the storage device is replaced by another supplier or another type, the system or controller may fail due to the ID of the old storage expected to be replaced. This creates an obstacle to replacing the current memory with a different provider and/or other type. For example, it is very costly and time consuming to update the hardware or software of a system or controller to have new recognition capabilities.

Contents of the invention

In view of this, an object of the present invention is to provide an integrated circuit storage device. The integrated circuit storage device includes an integrated circuit substrate, a plurality of application storage units on the integrated circuit substrate, a plurality of device identification nonvolatile storage units on the integrated circuit substrate, a plurality of device identification selection nonvolatile The storage unit is on the integrated circuit substrate and the control circuit.

a control circuit which (i) operates on the plurality of device identification codes identifying the non-volatile memory cells, the plurality of device identification codes comprising a plurality of bits identifying the type of the integrated circuit memory device, (ii) Perform programming, erasing and reading operations of the plurality of selection data identifying selected non-volatile memory cells, the selection data being distinguished from the plurality of device identification codes.

In one embodiment, the control circuit reads a device identification code from the plurality of identified non-volatile storage units in response to a device identification code read command, and the device identification code selects a non-volatile device through the plurality of identifications The selection data for the memory cell is distinguished from other device identification codes identifying the non-volatile memory cells in the plurality.

In one embodiment, the type of the integrated circuit storage device is identified by a device identification code of the plurality of device identification codes, the plurality of device identification codes including a manufacturer identification code of the integrated circuit storage device.

In one embodiment, the type of the integrated circuit memory device is identified by a device identifier of the plurality of device identifiers, the plurality of device identifiers including manufacturing data of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit storage device is distinguished by a device identification code of the plurality of device identification codes, and the plurality of device identification codes include product specification data of the integrated circuit storage device.

Another object of the present invention is to provide a method for replacing an integrated circuit memory device in an application, comprising:

providing a system configured to be compatible with a first integrated circuit memory device type having a first memory device identification code;

providing a second integrated circuit memory device type that does not have the first memory device identification code;

configuring the second integrated circuit memory device type with the at least a portion of the first memory device identification code; and

The second integrated circuit memory device type is integrated with the system.

In one embodiment, the configuration includes:

programming a plurality of device-identifying non-volatile memory cells in the second integrated circuit memory device type with the at least a portion of the first memory device identification code, thereby reading the device identification in the second integrated circuit memory device type During code operation, the at least part of the first storage device identification code is read from the plurality of device identification non-volatile storage units.

In one embodiment, the configuration includes:

programming a plurality of device-identifying selected non-volatile memory cells in the second integrated circuit memory device type with selection data to distinguish the at least some of the memory device identification codes in the second integrated circuit memory device type The first storage device identification code of the second integrated circuit storage device type, such that when operating to read the device identification code in the second integrated circuit storage device type, the at least part of the first storage device is read from the plurality of device identification non-volatile memory cells. Device ID.

In one embodiment, the configuration includes:

programming a plurality of device-identifying non-volatile memory cells in the second integrated circuit memory device type with the at least a portion of the first memory device identification code, thereby reading the device identification in the second integrated circuit memory device type During code operation, non-volatile memory units are identified from the plurality of devices in response to the at least a portion of the first memory device identification code to the system.

In one embodiment, the configuration includes:

programming a plurality of device-identifying selected non-volatile memory cells in the second integrated circuit memory device type with selection data to distinguish the at least some of the memory device identification codes in the second integrated circuit memory device type the first storage device identification code of the second integrated circuit storage device type such that when operating to read the device identification code in the second integrated circuit storage device type, non-volatile memory cells are identified from the plurality of devices responsive to at least a portion of the first storage device identification code to the system.

In one embodiment, prior to the configuration, the memory device ID read operation in the second integrated circuit memory device type cannot respond to the at least part of the first memory device identity code.

In one embodiment, prior to the configuration, the second integrated circuit memory device type without the first memory device identification code is not compatible with the system.

In one embodiment, after the configuration, the memory device ID read operation in the second integrated circuit memory device type may be responsive to the at least part of the first memory device ID.

In one embodiment, after the configuration, the second integrated circuit memory device type without the first memory device ID is compatible with the system.

In one embodiment, the first device identification code includes a manufacturer identification code of the integrated circuit memory device.

In one embodiment, the first device identification code includes manufacturing data of the integrated circuit memory device.

In one embodiment, the first device identification code includes product specification data of the integrated circuit memory device.

Another object of the present invention is to provide a method of manufacturing an integrated circuit memory device, comprising:

providing an integrated circuit substrate;

providing a plurality of application memory cells on the integrated circuit substrate;

providing a plurality of device-identified non-volatile memory cells on the integrated circuit substrate;

providing a plurality of device identification select non-volatile memory cells on the integrated circuit substrate; and

providing control circuitry that (i) operates on the plurality of device identification codes identifying non-volatile memory cells, the plurality of device identification codes comprising a plurality of bits identifying the type of memory device of the integrated circuit, (ii) Perform programming, erasing and reading operations of the plurality of selection data identifying selected non-volatile memory cells, the selection data being distinguished from the plurality of device identification codes.

In one embodiment, the control circuit reads a device identification code from the plurality of identified non-volatile storage units in response to a device identification code read command, and the device identification code selects a non-volatile device through the plurality of identifications The selection data for the memory cell is distinguished from other device identification codes identifying the non-volatile memory cells in the plurality.

In one embodiment, the type of the integrated circuit storage device is identified by a device identification code of the plurality of device identification codes, the plurality of device identification codes including a manufacturer identification code of the integrated circuit storage device.

In one embodiment, the type of the integrated circuit memory device is identified by a device identifier of the plurality of device identifiers, the plurality of device identifiers including manufacturing data of the integrated circuit memory device.

In one embodiment, the type of the integrated circuit storage device is distinguished by a device identification code of the plurality of device identification codes, and the plurality of device identification codes include product specification data of the integrated circuit storage device.

In various embodiments, these storage units may be non-volatile and/or volatile.

Description of drawings

The present invention is defined by the scope of the claims. These and other objects, features, and embodiments are described in conjunction with the drawings in the following descriptions, in which:

1A and 1B show a schematic diagram of a typical memory ID circuit implementation.

2A and 2B show schematic diagrams and flowcharts, respectively, of many different embodiments.

3A and 3B show schematic diagrams of other embodiments.

FIG. 4 shows a flow chart of how to extract and update the selection bit of the storage device ID.

FIG. 5 shows a flow chart of how to re-fetch and update the selection bit of the storage device ID.

FIG. 6 shows an example of the application of the variable storage device identification selection code and the variable storage device identification code.

FIG. 7 shows a simplified schematic diagram of an integrated circuit according to an embodiment of the invention.

[Description of main component symbols]

750: integrated circuit

700: Non-volatile storage unit with application data

752: Non-volatile storage unit with device identification code

754: Non-volatile memory location with select data

701: column decoder

702: word line

703: row decoder

704: bit line

705, 707: bus

706: Sense Amplifier/Data Input Structure

709: Program, Erase, and Read Adjustment Bias State Mechanism

708: Bias adjustment supply voltage

711: Data input line

715: data output line

Detailed ways

A non-volatile storage unit (such as a flash memory device) can not lose the stored data even when there is no power supply. Various embodiments use non-volatile memory cells to store identification codes and can be updated by programming or erasing such array data. In this case, the memory ID is programmable and can be flexibly adjusted for different systems expecting different memory IDs. Otherwise, different systems would require disruptive and costly changes to accommodate a desired new ID for a different storage device.

1A and 1B show a schematic diagram of a typical memory ID circuit implementation. In FIG. 1A , an identified storage unit repeatedly appears in an array structure, and data is output in byte mode or character mode. A more detailed schematic diagram of the identified memory cell is shown in FIG. 1B and includes a connection relying on a metal layer and a transistor that pulls down the output bit line BL to ground through an NMOS transistor, or alternatively through a P-type metal The oxide semiconductor transistor weakly pulls up the output bit line BL to maintain the supply voltage (Vdd). Therefore, the identification code of a storage device can be changed by modifying the metal layer of the storage device. However, such an implementation is less flexible because it requires changing the mask of the metal layer for different memory device IDs, and the memory device ID must be determined during manufacture (so it cannot be modified after manufacture ID of this storage device).

2A and 2B show schematic diagrams and flowcharts, respectively, of many different embodiments. In FIG. 2A, each memory device ID bit has a pull-down NMOS transistor connected to it in series, whereas each NMOS transistor for a particular bit position in the series is the same specific bit position selected by a different memory device identification code. selected. The upper column of NMOS transistors reads all bit positions of ID0, and the lower column of NMOS transistors reads all bit positions of ID1. For example, the leftmost NMOS transistor in the series corresponds to output ID bit ID7, and within the series, the higher NMOS transistor is selected by bit position ID7 of ID ID0, and this is higher The low NMOS transistor is selected by bit position ID7 of another memory device ID ID1. The point between the upper NMOS transistor and the lower NMOS transistor is represented in various embodiments, and the circuit can be customized to have a specific number of memory device IDs, such as a different number of columns. Additionally, the circuit can also be customized to have a specific number of bit positions within each storage device ID, such as a different number of rows.

The different storage device ID selections are stored in a non-volatile memory and fetched into a register at power-on read. For a particular bit position, if any storage device ID (eg, ID0 or ID1 ) is logic high, then the pull-down transistor path for that bit position is turned on. In this case, the integrated circuit can output a selected one of the multiple storage device IDs according to one or more storage device ID selection bits stored in one or more non-volatile memory units. FIG. 2B shows a flowchart of the process of extracting the storage device identification selection code, and then extracting the storage device identification code selected by the storage device identification selection code when the power is turned on for reading. After step 11 of power-on reading, step 13 extracts the storage device identification selection code from the non-volatile storage unit. In step 15, use the storage device identification selection code to select one of the multiple storage device identification codes. Then, in step 17, the selected storage device identification selection code is output.

3A and 3B show schematic diagrams of other embodiments. FIG. 3A is a structure of a storage device ID register array. The buffers of different storage device identification codes are enabled by different enable signals (EN#), and output to the data bus ID0~ID7, while the registers of other storage device identification codes remain closed because they do not receive the enabling signals . 3B shows a schematic diagram of an example cell identification register, which has a "Load (extract)" signal to latch the memory device identification code read from the non-volatile memory cell and the enable signal "EN" to set this latch The lock is activated. Since the SDI is stored and retrieved from the non-volatile memory unit, the SDI can be modified by programming or erasing the memory unit.

FIG. 4 shows a flow chart of how to extract and update the selection bit of the storage device ID. In step 21, a memory device identification selection code to be programmed is issued. The operation of programming the memory device to recognize the selection code begins at step 23 . During the verification process at step 25, it is determined whether programming succeeded or failed. If it is judged to be a programming failure, it will be determined in step 27 whether the maximum number of programming attempts has been reached. If the maximum number of programming attempts has not been reached, go back to step 23 and perform the programming operation again. If the maximum number of programming attempts has been reached, then at step 29 it is determined that the programming operation has failed. If it is determined in step 25 that the programming is successful, the algorithm will continue to step 31 for power-on reading. The storage device identification selection code is extracted into the non-volatile storage unit in step 33 . After having the storage device identification selection code, a storage device identification code is selected in step 35 . This storage device identification code identified by the storage device identification selection code is then output at step 37 .

FIG. 5 shows a flow chart of how to re-fetch and update the selection bit of the storage device ID. In step 41, a selection code identifying the memory device to be programmed is issued. The operation of programming the memory device to recognize the selection code begins at step 43 . During the verification process at step 45, it is determined whether the programming succeeded or failed. If it is judged to be a programming failure, it will be determined in step 47 whether the maximum number of programming attempts has been reached. If the maximum number of programming attempts has not been reached, go back to step 43 and perform the programming operation again. If the maximum number of programming attempts has been reached, then at step 49 it is determined that the programming operation has failed. If it is judged in step 45 that the programming is successful, the algorithm will continue to step 51 for power-on reading. The storage device identification selection code is extracted into the non-volatile storage unit in step 53 . This storage device identification code is then output at step 55 .

FIG. 6 shows an example of the application of the variable storage device identification selection code and the variable storage device identification code. At step 61 a system configured to be compatible with a first integrated circuit memory device type having a first memory device identification code is provided. An example of this compatibility is that the system interrogates a first integrated circuit memory device type, and after receiving a first memory device ID from the first integrated circuit memory device type, the system operates normally. At step 63 a second integrated circuit memory device type without the first memory device identification code is provided. At this time, the system is not configured to be compatible with the second integrated circuit memory device type because the second integrated circuit memory device type does not have the first memory device ID. Despite the lack of compatibility, the system may still be compatible with a second IC memory device type. For example, the system can be configured to interrupt normal operation if the system does not get the first storage device ID as expected when interrogating the second integrated circuit storage device type. Without the presently described techniques, such a system would have to be modified and updated to accept a different memory device ID associated with a second integrated circuit memory device type. At step 65, the second integrated circuit memory device type is configured to have at least a portion of the first memory device ID, at least the portion of the first memory device ID that the system is expected to continue to operate normally. Such a configuration is referred to as updating the VDI option code and/or the VDI of the second IC memory device type. At step 67, the second integrated circuit memory device type is integrated with the system. Such integration may occur before or after configuration of the second integrated circuit memory device type.

FIG. 7 shows a simplified schematic diagram of an integrated circuit according to an embodiment of the invention. Wherein the integrated circuit 750 includes a non-volatile storage unit 700 with application data, a non-volatile storage unit 752 with a device identification code, and a non-volatile storage unit 754 with selection data, implemented in one or in multiple storage arrays. A column decoder 701 is coupled to a plurality of word lines 702 arranged along the column direction of the memory array. The row decoder 703 is coupled to a plurality of bit lines 704 arranged along the row direction of the memory array to read and program data from the memory cells of the array. Addresses are provided by bus 705 to row decoder 703 and column decoder 701 . The sense amplifier and data input structures in block 706 are coupled to row decoder 703 via data bus 707 . Data is provided to the data input line 711 by the input/output port on the integrated circuit 750 , or input to the data input structure in block 706 by other internal/external data sources of the integrated circuit 750 . The controller used in this embodiment uses the bias adjustment state mechanism 709, and controls the application of the bias adjustment supply voltage generated or provided by the voltage supply source or block 708, such as reading, erasing, Program, Erase Verify, and Program Verify Voltages. The controller can be implemented using special purpose logic circuitry, as is well known to those skilled in the art. In an alternative embodiment, the controller includes a general purpose processor that can be used on the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic and a general purpose processor.

Different embodiments use different forms of storage device parameters such as ID, type, density, size, and so on.

The PID method and apparatus according to the embodiments of the present invention are not limited to applications in memory, and can be applied to other circuits that provide data with flexible content.

In addition to non-volatile memory, the present invention can also be used in devices with fuses or metal layer selection connection types. The storage element can be any type of medium such as a memory cell, a fuse, or a metal layer selection connection.

Although the present invention has been described with reference to the embodiments, the inventive concept is not limited by the detailed description. Alternatives and modifications have been suggested in the preceding description, and other alternatives and modifications will occur to those skilled in the art. In particular, all combinations of components that are substantially the same as those of the present invention to achieve substantially the same results as the present invention do not depart from the scope of the present invention. Accordingly, all such alternatives and modifications are intended to come within the scope of the invention as defined by the scope of the appended claims and their equivalents.

Claims (8)

1. A method of replacing an integrated circuit memory device in an application, comprising: providing a system configured to be compatible with a first integrated circuit memory device type having a first memory device identification code; providing a second integrated circuit memory device type that does not have the first memory device identification code; configuring the second integrated circuit memory device type with the at least a portion of the first memory device identification code; and The second integrated circuit memory device type is integrated with the system. 2. The method of claim 1, wherein the configuring comprises: programming a plurality of device-identifying non-volatile memory cells in the second integrated circuit memory device type with the at least a portion of the first memory device identification code, thereby reading the device identification in the second integrated circuit memory device type During code operation, the at least part of the first storage device identification code is read from the plurality of device identification non-volatile storage units. 3. The method of claim 1, wherein the configuring comprises: programming a plurality of device-identifying selected non-volatile memory cells in the second integrated circuit memory device type with selection data to distinguish the at least some of the memory device identification codes in the second integrated circuit memory device type The first storage device identification code of the second integrated circuit storage device type, such that when operating to read the device identification code in the second integrated circuit storage device type, the at least part of the first storage device is read from the plurality of device identification non-volatile memory cells. Device ID. 4. The method of claim 1 , wherein prior to the configuring, a DID read operation in the second IC memory device type fails to respond to the at least part of the first DID . 5. The method of claim 1, wherein prior to the configuration, the second integrated circuit memory device type without the first memory device ID is not compatible with the system. 6. The method of claim 1 , wherein after the configuration, a memory device ID read operation in the second integrated circuit memory device type is capable of responding to the at least part of the first memory device ID . 7. The method of claim 1, wherein after the configuration, the second integrated circuit memory device type without the first memory device ID is compatible with the system. 8. The method of claim 1, wherein the first device identification code comprises at least one of a manufacturer identification code, manufacturing data, and product specification data of the integrated circuit storage device.