CN104319287A - Trench gate type semiconductor device structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a trench gate type semiconductor device structure. The trench gate type semiconductor device structure comprises a substrate, at least two parallel trench gate structures, a polycrystalline silicon bridge connecting the trench gate structures in parallel, an insulating layer covering the trench gate structures and the polycrystalline silicon bridge, at least one contact hole formed in the upper portion of the polycrystalline silicon bridge and penetrates through the insulating layer and a grid metal layer arranged on the surface of the insulating layer. The contact holes are filled with the grid metal layer which makes ohmic contact with the polycrystalline silicon bridge, the polycrystalline silicon bridge is close to the first ends of the trench gate structures, the distance between the outer side of the polycrystalline silicon bridge and the first ends of the trench gate structures is L, and L is larger than 0. The polycrystalline silicon bridge avoids the tail ends of the trench gate structures, the connection mode can effectively lower the probability that gate oxide layers at the tail ends of the trench gate structures are broken down, and reliability of the device is improved.

Description

A trench gate type semiconductor device structure and manufacturing method thereof

technical field

The invention belongs to the field of semiconductor devices, and relates to a trench gate type semiconductor device structure and a manufacturing method thereof.

Background technique

Power transistors, such as trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), have an insulated gate located in a trench or cavity with source and drain regions separated by a doped body region. The gate is typically insulated with a dielectric layer lining the trench walls, and conductive source terminals are deposited or formed over the source and doped body regions. When the gate is properly biased, a conductive channel is created in the doped body region to allow drain-source current to flow from the drain region through the conductive channel to the source region. Two desirable properties of trench-gate and other similar transistors are relatively low overall resistance and relatively high Unclamped Inductive Switching (UIS) properties.

IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) is a voltage-controlled MOS/BJT composite device. In terms of structure, the structure of IGBT is very similar to that of VDMOS, except that the N+ substrate of VDMOS is adjusted to P+ substrate, but the conductance modulation effect introduced overcomes the contradiction between the inherent on-resistance and breakdown voltage of VDMOS itself, so that IGBT At the same time, it has the main advantages of bipolar power transistors and power MOSFETs: high input impedance, low input drive power, low conduction voltage, large current capacity, and fast switching speed. In the mid-1990s, a new concept was proposed, that is, the IGBT uses a U-shaped trench gate structure, which uses the silicon dry etching technology borrowed from the large-scale integration process. In the trench gate IGBT, the gate voltage forms an electron accumulation layer in the drift region, which enhances electron injection in the PIN diode and increases the carrier concentration on the surface. However, the "T"-shaped conductive path of the MOS structure in the original IGBT is shortened to two parallel vertical conductive paths, and the channel changes from horizontal to vertical, resulting in a decrease in cell area, thereby increasing the channel area per unit device area. , thereby reducing the channel resistance; and the groove gate eliminates the JFET effect, and there will be no current "bottleneck" area. Therefore, compared with the planar gate IGBT, the trench gate IGBT can greatly reduce the on-state voltage drop, thereby achieving a better compromise between the on-state voltage drop and the turn-off energy. In addition, relative to the PNP transistor current, the increase in the proportion of the PIN diode current can effectively suppress the latching effect, so the trench gate IGBT has a larger SOA safe operating area than the planar gate IGBT.

Multiple trench gate structures in semiconductor devices generally need to be drawn out in parallel. The usual practice is to connect the ends of multiple trench gate structures. However, in this connection method, the ends of the trench gates, especially at the sharp corners The gate oxide layer is prone to breakdown, resulting in degraded device performance.

Therefore, it is necessary to provide a new trench-gate semiconductor device structure and its manufacturing method to solve the above problems.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a trench gate semiconductor device structure and its manufacturing method, which is used to solve the problem that the connection method of polysilicon covering the end of the trench gate in the prior art is likely to cause trenches The breakdown of the gate oxide layer at the gate terminal leads to the problem of device performance degradation.

In order to achieve the above object and other related objects, the present invention provides a trench gate semiconductor device structure, including:

Substrate;

At least two trench gate structures, the trench gate structures are formed in the substrate and extend from the front to the back of the substrate; the trench gate structures are arranged in parallel with each other;

a polysilicon bridge formed on the surface of the substrate and in contact with the trench gate structures, connecting each trench gate structure in parallel;

an insulating layer covering the trench gate structure and the polysilicon bridge;

at least one contact hole, the contact hole is located above the polysilicon bridge and penetrates through the insulating layer;

a gate metal layer formed on the surface of the insulating layer and filled in the contact hole, and in ohmic contact with the polysilicon bridge;

The polysilicon bridge is close to the first end of the trench gate structure, and the distance between the outside of the polysilicon bridge and the first end of the trench gate structure is L, wherein L>0.

Optionally, the value range of L is 0.1-5 μm.

Optionally, the contact hole is located between two adjacent trench gate structures.

Optionally, the polysilicon bridge is straight, zigzag or curved.

Optionally, the polysilicon bridge is vertically connected to the trench gate structure.

Optionally, the trench gate semiconductor device structure is a power field effect transistor or an insulated gate bipolar transistor.

Optionally, the power field effect transistor includes a drain region, a drift region, a channel region and a source region in sequence from bottom to top, and the trench gate structure extends downward from the surface of the source region into the drift region .

Optionally, the IGBT sequentially includes a collector metal, a collector layer, and a drift region from bottom to top; the trench gate structure is formed in the drift region; There is a base area, the base area is located between two adjacent trench gate structures, an emitter area is formed on both sides of the upper part of the base area; an ohmic contact with the base area and the emitter area is formed above the base area emitter metal.

The present invention also provides a method for manufacturing a trench gate semiconductor device structure, comprising the following steps:

providing a substrate in which at least two parallel trenches are formed;

forming a gate oxide layer on the inner surface of the trench;

Depositing a polysilicon layer, the polysilicon layer is filled in the trench and covers the substrate;

Etching the polysilicon layer to form a polysilicon bridge, and removing the redundant polysilicon layer outside the trench; the polysilicon bridge is located on the surface of the substrate and is in contact with the trench gate structure, and each trench gate structure is connected in parallel ; The polysilicon bridge is close to the first end of the trench gate structure, and the distance between the outside of the polysilicon bridge and the first end of the trench gate structure is L, wherein L>0;

forming an insulating layer covering the polysilicon bridge and the first end of the trench gate structure on the substrate, and forming at least one contact hole in the insulating layer; the contact hole is located above the polysilicon bridge and penetrating through the insulating layer;

A gate metal layer is deposited on the surface of the insulating layer, and the gate metal layer is filled in the contact hole and is in ohmic contact with the polysilicon bridge.

Optionally, the value range of L is 0.1-5 μm.

As mentioned above, the trench gate semiconductor device structure and its manufacturing method of the present invention have the following beneficial effects: the trench gate semiconductor device structure of the present invention comprises at least two trench gate structures arranged parallel to each other, and each trench gate The structure is connected in parallel through a polysilicon bridge, and the polysilicon bridge is close to the first end of the trench gate structure, the distance between the outside of the polysilicon bridge and the first end of the trench gate structure is L>0, and the gate metal A layer fills the contact hole in the insulating layer in ohmic contact with the polysilicon bridge. Since the polysilicon bridge avoids the end of the trench gate structure, this connection method can effectively reduce the probability of breakdown of the gate oxide layer at the end of the trench gate structure, especially at the sharp corner of the end, thereby improving the reliability of the device. The polysilicon bridge can be obtained by simply changing the mask pattern when removing the excess polysilicon layer outside the trench, the process is simple, and the manufacturing cost will not be increased.

Description of drawings

FIG. 1 shows a schematic cross-sectional structure of a trench-gate semiconductor device structure of the present invention.

FIG. 2 is a schematic top view of the trench-gate semiconductor device structure of the present invention.

FIG. 3 is a schematic cross-sectional view of the trench-gate semiconductor device structure in Embodiment 2 of the present invention.

FIG. 4 is a schematic diagram of forming trenches in a substrate in the method for fabricating a trench-gate semiconductor device structure according to the present invention.

FIG. 5 is a schematic diagram of forming a gate oxide layer on the inner surface of the trench in the method for fabricating the trench-gate semiconductor device structure of the present invention.

FIG. 6 is a schematic diagram of depositing a polysilicon layer in the manufacturing method of the trench-gate semiconductor device structure of the present invention.

FIG. 7 is a schematic diagram of etching a polysilicon layer to form a polysilicon bridge in the manufacturing method of the trench-gate semiconductor device structure of the present invention.

FIG. 8 is a schematic diagram of depositing an insulating layer and forming a contact hole in the manufacturing method of the trench-gate semiconductor device structure of the present invention.

FIG. 9 is a schematic diagram of depositing a gate metal layer in the manufacturing method of the trench-gate semiconductor device structure of the present invention.

Component designation description

1 Substrate

2 trench gate structure

3 polysilicon bridge

4 insulation layer

5 contact holes

6 gate metal layer

7 collector metal

8 collector layer

9 base area

10 launch area

11 Drain area

12 channel area

13 source area

14 Groove

15 gate oxide layer

16 polysilicon layer

17 Polysilicon gate

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 9. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

The present invention provides a trench gate semiconductor device structure, please refer to Figure 1 and Figure 2, which are respectively shown as a cross-sectional view and a top view of the trench gate semiconductor device structure, including:

substrate1;

At least two trench gate structures 2, the trench gate structures 2 are formed in the substrate 1 and extend from the front to the back of the substrate 1; the trench gate structures 2 are arranged in parallel with each other;

a polysilicon bridge 3 formed on the surface of the substrate 1 and in contact with the trench gate structures 2, connecting each trench gate structure 2 in parallel;

an insulating layer 4 covering the trench gate structure 2 and the polysilicon bridge 3;

At least one contact hole 5, the contact hole 5 is located above the polysilicon bridge 3 and penetrates through the insulating layer 4;

a gate metal layer 6, formed on the surface of the insulating layer 4 and filled in the contact hole 5, and in ohmic contact with the polysilicon bridge 3;

The polysilicon bridge 3 is close to the first end of the trench gate structure 2 , and the distance between the outside of the polysilicon bridge 3 and the first end of the trench gate structure 2 is L, wherein L>0.

Specifically, the structure of the trench gate semiconductor device is a power field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). In this embodiment, the structure of the trench gate semiconductor device is based on an insulated gate bipolar transistor type transistor as an example, wherein the substrate 1 serves as the drift region of the IGBT.

As shown in FIG. 1, the IGBT includes a collector metal 7, a collector layer 8, and a drift region (substrate 1) from bottom to top; the trench gate structure 2 is formed on the drift region. region; a base region 9 is also formed in the drift region, the base region 9 is located between two adjacent trench gate structures 2, and emitter regions 10 are formed on both sides of the upper part of the base region 9; An emitter metal (not shown) in ohmic contact with the base region 9 and the emitter region 10 is formed above the region 9 .

Specifically, the collector layer 8 is P-type doped, the drift region (substrate 1) is N-type doped, the base region 9 is P-type doped, and the emitter region 10 is N-type heavily doped. Doping, the trench gate structure 2 includes a trench extending from the front to the back of the drift region, a gate oxide layer formed on the inner wall of the trench, and a polysilicon gate filled in the trench, so The extending distance of the trench is smaller than the thickness of the drift region.

In another embodiment, an N-type buffer layer (not shown) may also be formed between the collector layer 8 and the drift region, so that the vertical withstand voltage structure of the IGBT consists of a non-punch-through structure (NPT, Non- Punch through) into a soft punch-through structure (SPT, Soft-Punch Through). The non-punch-through (NPT) technology has good transport efficiency based on not killing the minority carrier lifetime, but its carrier injection coefficient is relatively low; and the punch-through IGBT with a buffer layer between the drift region and the collector region can be used in Under the premise of ensuring the withstand voltage, reduce the thickness of the drift region and control the hole injection efficiency on the back surface of the IGBT, thereby improving the performance of the IGBT.

It should be pointed out that there are many types of trench-gate IGBTs, and this embodiment is only an example. In other embodiments, the type of the trench-gate IGBT can also be an existing IGBT structure such as a floating type. The protection scope of the present invention should not be unduly limited here.

As shown in FIG. 2 , the distance L between the outside of the polysilicon bridge 3 and the first end of the trench gate structure 2 is shown. The gate metal layer is filled in the contact hole in the insulating layer and is in ohmic contact with the polysilicon bridge, so that multiple trench gate structures are electrically connected to the gate metal layer through the polysilicon bridge. The distance between the outside of the polysilicon bridge and the first end of the trench gate structure is L>0, so that the polysilicon bridge avoids the end of the trench gate structure, and the end of the trench gate structure is covered by an insulating layer. The parallel connection of multiple trench gate structures can effectively reduce the probability of breakdown of the gate oxide layer at the end of the trench gate structure, especially at the sharp corner of the end, thereby improving the reliability of the device. In this embodiment, the value range of L is 0.1-5 μm, preferably 1 μm.

Further, the contact hole 5 is preferably located between two adjacent trench gate structures 2, so that the contact between the trench gate structure 2 and the polysilicon bridge 3 is not affected by the contact hole process, so that Further improve device reliability. Wherein, the part of the polysilicon bridge located at the bottom of the contact hole 5 can be heavily doped by ion implantation, so as to reduce the contact resistance between the gate metal layer 6 and the polysilicon bridge.

Specifically, the polysilicon bridge 3 includes, but is not limited to, a straight line, a broken line or an arc. In this embodiment, the polysilicon bridge 3 is preferably a straight line (as shown in FIG. 2 ), and the polysilicon bridge 3 and the The trench gate structure 2 is vertically connected. The polysilicon bridge 3 adopts a linear shape and is vertically connected to the trench gate structure 2, which can reduce the complexity of the device manufacturing process and is beneficial to improve production efficiency.

The trench type semiconductor device structure of the present invention comprises at least two trench gate structures arranged parallel to each other, each trench gate structure is connected in parallel through a polysilicon bridge, and the polysilicon bridge is close to the first end of the trench gate structure, The distance between the outer side of the polysilicon bridge and the first end of the trench gate structure is L>0, and the gate metal layer is filled in the contact hole in the insulating layer to be in ohmic contact with the polysilicon bridge. Since the polysilicon bridge avoids the end of the trench gate structure, this connection method can effectively reduce the probability of breakdown of the gate oxide layer at the end of the trench gate structure, especially at the sharp corner of the end, thereby improving the reliability of the device.

Embodiment two

This embodiment adopts basically the same technical solution as Embodiment 1, the difference is that in Embodiment 1, the structure of the trench gate type semiconductor device is an insulated gate bipolar transistor (IGBT), and in this embodiment, the The trench gate semiconductor device structure is a power field effect transistor (MOSFET), wherein the substrate 1 serves as a drift region of the power field effect transistor.

Please refer to FIG. 3, which shows a schematic cross-sectional view of a trench type power field effect transistor. As shown in the figure, the power field effect transistor includes a drain region 11, a drift region (substrate 1), a trench from bottom to top, and The channel region 12 and the source region 13, the trench gate structure 3 extends downward from the surface of the source region 13 into the drift region.

Specifically, in this embodiment, the drain region 11 is N-type heavily doped, the drift region is N-type doped, the channel region 12 is P-type doped, and the source region 13 is N-type heavily doped.

The power field effect transistor has a very low on-resistance when the device is in the on state, which minimizes the power loss of the device itself, and can have a sufficiently high reverse breakdown voltage when the device is in the off state.

It should be pointed out that there are many types of trench gate power field effect transistors, and this embodiment is only an example. In other embodiments, the trench gate power field effect transistors can also use other existing types, Such as deep groove type, etc., the protection scope of the present invention should not be excessively limited here.

In the trench gate type power field effect transistor, since the polysilicon bridge avoids the end of the trench gate structure, this connection method can effectively reduce the probability of breakdown of the gate oxide layer at the end of the trench gate structure, especially at the sharp corner of the end , thereby improving the reliability of the device.

Embodiment three

The present invention also provides a method for manufacturing a trench gate semiconductor device structure, comprising the following steps:

Referring first to FIG. 4 , a substrate 1 is provided, and at least two trenches 14 arranged in parallel are formed in the substrate 1 .

Specifically, the substrate 1 includes, but is not limited to, conventional semiconductor materials such as Si, Ge, and SiGe, and the substrate 1 can be P-type doped or N-type doped according to device types. The trench 14 is formed by etching.

Then referring to FIG. 5 , a gate oxide layer 15 is formed on the inner surface of the trench 14 by thermal oxidation or other deposition methods; the material of the gate oxide layer 15 may be silicon dioxide.

Referring to FIG. 6 , a polysilicon layer 16 is deposited, and the polysilicon layer 16 is filled in the trench 14 and covers the substrate 1 .

Referring to Fig. 7 again, a polysilicon bridge pattern is formed on the surface of the polysilicon layer 16 by conventional semiconductor processes such as photolithography and development, and the polysilicon layer 16 is etched to form a polysilicon bridge 3, and the excess outside the trench 14 is removed. polysilicon layer. Wherein, the polysilicon layer filled in the trench 14 serves as the polysilicon gate 17 of the trench gate structure 2 , and the outer surface and bottom of the polysilicon gate 17 are surrounded by the gate oxide layer 15 .

Specifically, as shown in FIG. 2 , the polysilicon bridge 3 is located on the surface of the substrate 1 and is in contact with the trench gate structures 2 to connect each trench gate structure 2 in parallel; the polysilicon bridge 3 is close to the The distance between the first end of the trench gate structure 2 and the outside of the polysilicon bridge 3 and the first end of the trench gate structure 2 is L, wherein L>0.

In this embodiment, the value range of L is 0.1-5 μm, preferably 1 μm. If the value of L is too small, the risk of breakdown of the gate oxide layer at the end of the trench gate structure 2, especially at the sharp corner of the end, is still relatively large; if the value of L is too large, the effective area of the active region will become smaller , which is not conducive to the miniaturization of the device.

Next, referring to FIG. 8, an insulating layer 4 covering the polysilicon bridge 3 and the first end of the trench gate structure is formed on the substrate 1, and at least one contact hole 5 is formed in the insulating layer 4; The contact hole 5 is located above the polysilicon bridge 3 and penetrates through the insulating layer 4 .

Specifically, the insulating layer 4 includes but not limited to insulating materials such as silicon dioxide and silicon nitride, and the insulating layer 4 serves as a protective layer covering the first end of the trench gate structure 2 .

Further, the contact hole 5 is preferably located between two adjacent trench gate structures 2, so that the contact between the trench gate structure 2 and the polysilicon bridge 3 is not affected by the contact hole process, so that Further improve device reliability. Wherein, the part of the polysilicon bridge located at the bottom of the contact hole 5 can be heavily doped by ion implantation, so as to reduce the contact resistance between the gate metal layer 6 and the polysilicon bridge.

Finally, referring to FIG. 9 , a gate metal layer 6 is deposited on the surface of the insulating layer 4 , and the gate metal layer 6 is filled in the contact hole 5 and is in ohmic contact with the polysilicon bridge 3 .

Specifically, the gate metal layer 6 includes, but is not limited to, good electrical conductors such as Cu, Ag, and Au. The gate metal layer is filled in the contact hole in the insulating layer and is in ohmic contact with the polysilicon bridge, so that multiple trench gate structures are electrically connected to the gate metal layer through the polysilicon bridge.

It should be pointed out that, in addition to the above steps, in the process of fabricating the trench gate semiconductor device structure, according to the specific type of the fabricated device, such as trench IGBT, power MOSFET, etc., and the specific conductivity type of the device, it is also necessary to It is common knowledge in the field to perform corresponding types of doping on relevant regions of the device and to fabricate related functional layers, and the protection scope of the present invention should not be excessively limited here.

So far, a trench type semiconductor device structure has been produced, wherein the polysilicon bridge can be produced by simply changing the mask pattern when removing the excess polysilicon layer outside the trench, the process is simple, and the production cost will not be increased. The polysilicon bridge connects multiple trench gate structures in parallel, and the polysilicon bridge is close to the first end of the trench gate structure, and the distance L between the outside of the polysilicon bridge and the first end of the trench gate structure >0, the gate metal layer is filled in the contact hole in the insulating layer and is in ohmic contact with the polysilicon bridge, so that multiple trench gates are electrically connected to the gate metal layer through the polysilicon bridge. Since the polysilicon bridge avoids the end of the trench gate structure, this connection method can effectively reduce the probability of breakdown of the gate oxide layer at the end of the trench gate structure, especially at the sharp corner of the end, thereby improving the reliability of the device.

To sum up, the trench type semiconductor device structure of the present invention includes at least two trench gate structures arranged parallel to each other, each trench gate structure is connected in parallel by a polysilicon bridge, and the polysilicon bridge is close to the trench gate structure The distance between the outside of the polysilicon bridge and the first end of the trench gate structure is L>0, and the gate metal layer is filled in the contact hole in the insulating layer to make ohmic contact with the polysilicon bridge. Since the polysilicon bridge avoids the end of the trench gate structure, this connection method can effectively reduce the probability of breakdown of the gate oxide layer at the end of the trench gate structure, especially at the sharp corner of the end, thereby improving the reliability of the device. The polysilicon bridge can be obtained by simply changing the mask pattern when removing the excess polysilicon layer outside the trench, the process is simple, and the manufacturing cost will not be increased. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (10)

1. a duck semiconductor device architecture, comprising:

Substrate;

Article at least two, trench gate structure, described trench gate structure is formed in described substrate, rearwardly extends in direction from described substrate face; Be arranged parallel to each other between each trench gate structure;

Polycrystalline silicon bridge, is formed at described substrate surface, and contacts with described trench gate structure, and each trench gate structure is in parallel;

Insulating barrier, covers described trench gate structure and described polycrystalline silicon bridge;

At least one contact hole, described contact hole to be positioned at above described polycrystalline silicon bridge and through described insulating barrier;

Gate metal layer, is formed at described surface of insulating layer and is filled in described contact hole, with described polycrystalline silicon bridge ohmic contact;

It is characterized in that:

Described polycrystalline silicon bridge is near the first end of described trench gate structure, and the distance outside described polycrystalline silicon bridge and between described trench gate structure first end is L, wherein, and L>0.

2. duck semiconductor device architecture according to claim 1, is characterized in that: the span of L is 0.1 ~ 5 μm.

3. duck semiconductor device architecture according to claim 1, is characterized in that: described contact hole is between adjacent two trench gate structures.

4. duck semiconductor device architecture according to claim 1, is characterized in that: described polycrystalline silicon bridge is linear pattern, fold-line-shaped or arc.

5. duck semiconductor device architecture according to claim 1, is characterized in that: described polycrystalline silicon bridge is connected with described trench gate structure is vertical.

6. duck semiconductor device architecture according to claim 1, is characterized in that: described duck semiconductor device architecture is power field effect transistor or insulated gate bipolar transistor.

7. duck semiconductor device architecture according to claim 6, it is characterized in that: described power field effect pipe comprises drain region, drift region, channel region and source region from bottom to top successively, described trench gate structure extends downward described drift region from described area surface.

8. duck semiconductor device architecture according to claim 6, is characterized in that: described insulated gate bipolar transistor comprises collector electrode metal, collector layer and drift region from bottom to top successively; Described trench gate structure is formed in described drift region; Also be formed with base in described drift region, described base is between adjacent two trench gate structures, and both sides, top, described base are formed with emitter region; The emitter metal with described base and emitter region ohmic contact is formed above described base.

9. a manufacture method for duck semiconductor device architecture, is characterized in that, comprises the following steps:

One substrate is provided, in described substrate, forms at least two grooves arranged in parallel;

Gate oxide is formed at described groove medial surface;

Deposition of polysilicon layer, described polysilicon layer is filled in described groove, and covers described substrate;

Etch described polysilicon layer and form polycrystalline silicon bridge, and remove the outer unnecessary polysilicon layer of described groove; Described polysilicon bridge location in described substrate surface, and contacts with described trench gate structure, and each trench gate structure is in parallel; Described polycrystalline silicon bridge is near the first end of described trench gate structure, and the distance outside described polycrystalline silicon bridge and between described trench gate structure first end is L, wherein, and L>0;

Form the insulating barrier covering described polycrystalline silicon bridge and described trench gate structure first end over the substrate, and form at least one contact hole in described insulating barrier; Described contact hole to be positioned at above described polycrystalline silicon bridge and through described insulating barrier;

At described surface of insulating layer deposition of gate metal level, described gate metal layer is filled in described contact hole, with described polycrystalline silicon bridge ohmic contact.

10. the manufacture method of duck semiconductor device architecture according to claim 9, is characterized in that: the span of L is 0.1 ~ 5 μm.