CN104319292A - Novel silicon carbide MOSFET and manufacturing method thereof - Google Patents

Abstract

The invention provides a novel silicon carbide MOSFET and a manufacturing method of the MOSFET. According to the manufacturing method, after all ions are implanted into a silicon carbide MOSFET device, a P-epitaxial layer with the low surface roughness is formed on a P trap surface in an epitaxy mode, and carriers are transported in an inversion channel in the P-epitaxial layer. As the roughness of the P-epitaxial layer is lower than that of the P trap surface, the probability of colliding or scattering of the carriers in the inversion channel is reduced, the carrier mobility of the inversion channel of the silicon carbide MOSFET device is increased, and on resistance of the device is reduced.

Description

A novel silicon carbide MOSFET and its manufacturing method

technical field

The invention relates to the technical field of electronic circuits, in particular to a novel silicon carbide MOSFET and a manufacturing method thereof.

Background technique

Usually, in the fabrication process of SiC MOSFET devices, multi-step ion implantation and high-temperature activation annealing processes are required, both of which will increase the roughness of the inversion conductive channel on the P-well surface of SiC MOSFET devices.

The normal use of silicon carbide devices depends on the transport of carriers in silicon carbide devices. Figure 1 shows the transport path of carriers on the surface of the P well. When transporting in the inversion conductive channel on the surface of the high-density P well, the probability of carrier collision or scattering will be very high, resulting in very low carrier mobility in the inversion layer channel of the MOSFET device, which will further increase the on-resistance of the MOSFET device , affecting the use of MOSFET devices.

Therefore, a new type of silicon carbide MOSFET is now needed to reduce the probability of carrier collision or scattering in the conductive channel, improve the low carrier mobility of the inversion channel of the silicon carbide MOSFET device, and reduce the on-resistance of the device.

Contents of the invention

The invention provides a novel silicon carbide MOSFET and a manufacturing method thereof. The invention can reduce the probability of carrier collision or scattering in the conductive channel, improve the low carrier mobility of the inversion channel of the silicon carbide MOSFET device, and reduce the conduction of the device. resistance.

In order to achieve the above object, the present invention provides the following technical means:

A novel silicon carbide MOSFET comprising: a SiC substrate, an N ^{-epitaxial layer disposed above the SiC substrate, two P wells disposed above the N- epitaxial} layer, two adjacent P wells disposed on the P wells The N ⁺ contact and P ⁺ contact are arranged in the JFET region between the two P wells, arranged above the JFET region and extending to the SiO ₂ oxide layer on the P well, and the gate is arranged above the SiO ₂ oxide layer. A source above the P well, a drain disposed below the SiC substrate, and a P ⁻ epitaxial layer disposed between the JFET region and the SiO ₂ oxide layer and extending to the P well.

Preferably, the thickness of the P ^- epitaxial layer is 0.01-0.1um.

Preferably, it is characterized in that the doping concentration of the P ^- epitaxial layer is 1×10 ¹⁶ cm ^-3 to 1×10 ¹⁷ cm ^-3 .

Preferably, it is characterized in that the doping medium ^of the P- epitaxial layer is aluminum or boron.

A method of manufacturing a novel silicon carbide MOSFET comprising:

Epitaxial N ^- epi layer on SiC substrate;

Ion implantation is performed on the N ^- epitaxial layer to form two P wells, and the middle of the two P wells is a JFET region;

performing ion implantation on the two P wells respectively to form N ⁺ contacts and P ⁺ contacts;

Annealing the device formed after the above steps at a temperature of 1500°C to 1850°C in a high-temperature activated annealing furnace;

an epitaxial P ^- epi layer over the JFET region;

thermally oxidizing the _SiO2 oxide layer over the P ^- epi layer;

depositing polysilicon over the _SiO2 oxide layer to form a gate;

constructing sources above the two P-wells respectively;

A drain is built under the SiC substrate.

Preferably, the epitaxial N ^- epitaxial layer on the SiC substrate specifically includes:

The epitaxial doping concentration is 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁶ cm ^-3 on the SiC substrate, and an N ^- epitaxial layer with a thickness of 5-35um is grown.

Preferably, performing ion implantation on the N ^- epitaxial layer to form two P wells specifically includes: performing ion implantation of Al ions on the N ^- epitaxial layer three or four times to form a growth depth of 0.5-1.5um, doped Two P-wells with impurity concentrations of 1×10 ¹⁸ cm ^-3 to 5×10 ¹⁸ cm ^-3 ;

The performing ion implantation on the two P wells to form the N ⁺ contact and the P ⁺ contact specifically includes: performing ion implantation of Al ions three or four times on each P well to form a doped P ⁺ contacts with a dopant concentration of 1×10 ¹⁹ cm ^-3 to 5×10 ¹⁹ cm ^-3 , and then three or four times of ion implantation of N ions to form a doped well with a depth of 0.2 to 0.3um in each P well N ⁺ contacts with a concentration of 1×10 ¹⁹ cm ^-3 to 5×10 ¹⁹ cm ^-3 .

Preferably, the epitaxial P ^- epitaxial layer above the JFET region specifically includes:

An epitaxial P- epitaxial layer with a doping concentration ^of 1×10 ¹⁶ cm ^-3 to 1×10 ¹⁷ cm ^-3 and a thickness of 0.01 to 0.1um is epitaxially formed above the JFET region.

Preferably, the thermal oxidation of the _SiO2 oxide layer above the P ^- epitaxial layer specifically includes:

In a high-temperature oxidation furnace at a temperature of 1200° C. to 1350° C., dry oxygen thermal oxidation of the P ^- epitaxial layer to grow a 20nm to 60nm SiO ₂ oxide layer.

Preferably, the depositing polysilicon on the SiO ₂ oxide layer to form the gate specifically includes: depositing 0.1-1um doping concentration of 1×10 ²⁰ cm on the SiO ₂ oxide layer by low-pressure chemical vapor deposition ^-3 ~ 3×10 ²⁰ cm ^-3 polysilicon, forming the gate;

The constructing the source above the two P wells ^and the drain below the SiC substrate respectively includes: depositing ^30-100nm Ti and 100-300nm Al alloy, used as ohmic contact metal, and annealed at 800°C-1000°C in nitrogen atmosphere for 2-5min to form ohmic contact.

The present invention provides a new type of silicon carbide MOSFET. After all the ions are implanted in the silicon carbide MOSFET device, a layer of P ^- epitaxy layer with lower surface roughness is epitaxy on the surface of the P well, and the carriers are transported in the P ^- epitaxy layer. layer inversion channel, since the roughness of the P ^- epitaxial layer is smaller than the roughness of the P well surface, the probability of carrier collision or scattering in the inversion layer channel is reduced, and the inversion channel carrier of SiC MOSFET devices is improved. Mobility, lower device on-resistance.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a transport path of carriers on the surface of a P well in the prior art;

2 is a schematic structural diagram of a novel silicon carbide MOSFET disclosed in an embodiment of the present invention;

FIG. 3 is a transport path of carriers in the P ^- epitaxial layer disclosed in the embodiment of the present invention;

4 is a schematic diagram of the conduction current of the drain and the source in a novel silicon carbide MOSFET disclosed in an embodiment of the present invention;

5 is a flow chart of a novel silicon carbide MOSFET manufacturing method disclosed in an embodiment of the present invention;

6a-6g are schematic diagrams of MOSFET structures corresponding to the novel silicon carbide MOSFET manufacturing method disclosed in the embodiments of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As shown in Figure 2, the present invention provides a novel silicon carbide MOSFET, comprising: a SiC substrate 9, an N ^- epitaxial layer 8 disposed above the SiC substrate 9, and an N-epitaxial layer disposed above the N ^- epitaxial layer 8. The two P wells 7, the N ⁺ contact 5 and the P ⁺ contact 6 arranged on the P well 7, which are adjacent to each other, the JFET region 11 arranged in the middle of the two P wells 7, arranged above the JFET region 11 and extending to the P The SiO2 oxide layer 2 on the well 7, the gate 1 disposed above the _SiO2 oxide layer ₂ , the source 4 disposed above the P well 7, and the drain 10 disposed below the SiC substrate 9 are disposed on Between the JFET region 11 and the SiO ₂ oxide layer 2 , and extending to the P ⁻ epitaxial layer 3 on the P well 7 .

In order to better improve the transfer efficiency of carriers, the preferred thickness of the P ^- epitaxial layer 3 is 0.01-0.1um, the doping concentration is 1×10 ¹⁶ cm ^-3 -1×10 ¹⁷ cm ^-3 , and the P ^- epitaxial layer 3 The doping medium of layer 3 is aluminum, and of course other trivalent elements can be used for doping, such as boron.

The surface roughness of the P well 7 formed by the MOSFET device after the multi-step ion implantation and high-temperature activation annealing process is relatively high, so the present invention epitaxially P ^- epitaxial layer 3 above the P well 7, and the epitaxial P ^- epitaxial layer 3 The surface roughness is lower than that of P well 7, as shown in Figure 3, after the epitaxial P ^- epitaxial layer 3 above P well 7, the transport path of carriers in the P ^- epitaxial layer inversion channel.

It can be seen from Figure 3 that the probability of carrier collision or scattering in the channel of the inversion layer of the P ^- epitaxial layer is significantly reduced. As the probability of collision and scattering of carriers decreases, the mobility of carriers in the inversion channel increases accordingly. , so that the on-resistance of the device is reduced, so that the user can use the MOSFET device better.

The conduction principle of the silicon carbide MOSFET device with the addition of P ^- epitaxial layer 3 is as follows: a positive voltage UGS is applied to the gate ₁ , and the gate _1SiO2 dielectric is insulating, so there will be no gate current flowing, but the gate 1 The positive voltage will push away the holes in the P ^- epi layer 3 below it, and attract the electrons in the N ^- epi layer 8 to the P ^- epi layer 3 below the gate 1, when U _GS is greater than the turn-on voltage or threshold voltage At this time, the electron concentration of the P ^- epitaxial layer 3 under the gate 1 will exceed the hole concentration, so that the P ^- epitaxial layer 3 is inverted into an N-type and becomes an N-type inversion layer 3', and the inversion layer forms an N channel. The PN junction is made to disappear, thereby making the drain 10 and the source 4 conductive. As shown in FIG. 4 , it is the current direction after the drain 10 and the source 4 conduct electricity.

The new silicon carbide MOSFET will not affect the normal use of the MOSFET, and it can increase the mobility of carriers and reduce the on-resistance during use, thereby reducing the self-consumption of the MOSFET and improving the use efficiency.

In order to put the above-mentioned new silicon carbide MOSFET into production, as shown in Figure 5, the present invention also provides a method for manufacturing a new silicon carbide MOSFET, which specifically includes:

Step S101 ^: Epitaxial N- epitaxial layer 8 on SiC substrate 9;

In specific implementation, the epitaxial doping concentration is 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁶ cm ^-3 on the SiC substrate 9 , and the N ^- epitaxial layer 8 with a thickness of 5-35um is grown, and formed after step 101 The silicon carbide device is shown in Figure 6a.

Step S102: performing ion implantation on the N ⁻ epitaxial layer 8 to form two P wells 7, and the middle of the two P wells 7 is a JFET region 11;

In specific implementation ^, Al ions are implanted three or four times on the N- epitaxial layer 8 to form a growth depth of 0.5-1.5um and a doping concentration of 1×10 ¹⁸ cm ^-3 to 5×10 ¹⁸ cm ^-3 The silicon carbide device formed after step 102 is shown in FIG. 6b.

Step S103: performing ion implantation on the two P wells 7 to form N ⁺ contacts 5 and P ⁺ contacts 6;

In specific implementation, Al ions are implanted three or four times on each P-well 7 to form a well with a depth of 0.2-0.3um and a doping concentration of 1×10 ¹⁹ cm ^-3 to 5×10 ¹⁹ cm ^-3 . P ⁺ contact 6, and then carry out three or four times of ion implantation of N ions, forming a depth of 0.2 ~ 0.3um in each P well 7, doping concentration of 1 × 10 ¹⁹ cm ^-3 ~ 5 × 10 ¹⁹ cm ^-3 The N ⁺ contact 5 of the silicon carbide device formed after step 103 is shown in FIG. 6c.

Step S104: annealing the device formed after the above steps at a temperature of 1500° C. to 1850° C. in a high-temperature activation annealing furnace;

Anneal the SiC device shown in Figure 6c in a high temperature activated annealing furnace.

Step S105: Epitaxially P ^- epitaxial layer 3 above the JFET region 11;

In a specific implementation, a P ^- epitaxial layer 3 with a doping concentration of 1×10 ¹⁶ cm ^-3 to 1×10 ¹⁷ cm ^-3 and a thickness of 0.01 to 0.1 um is epitaxially formed above the JFET region 11 , and the P ^- epitaxial layer 3 extends above the two P wells 7, and the silicon carbide device formed after step 105 is shown in FIG. 6d.

Step S106: thermally oxidizing the SiO ₂ oxide layer 2 above the P ^- epitaxial layer 3;

In specific implementation, at a temperature of 1200°C to 1350°C in a high temperature oxidation furnace, dry oxygen thermal oxidation ^of the P- epitaxial layer 3 grows a 20nm to 60nm _SiO2 oxide layer 2, and the silicon carbide device formed after step 106 is shown in the figure 6e shown.

Step S107: depositing polysilicon on the SiO ₂ oxide layer 2 to form the gate 1;

In specific implementation, polycrystalline silicon with a doping concentration of 1×10 ²⁰ cm ^-3 to 3×10 ²⁰ cm ^-3 is deposited on the SiO ₂ oxide layer 2 by low-pressure chemical vapor deposition to form a gate 1. The silicon carbide device formed after step 107 is shown in FIG. 6f.

Step S108 : constructing the source 4 above the two P-wells 7 ; constructing the drain 10 below the SiC substrate 9 .

In specific implementation, 30-100nm Ti and 100-300nm Al alloys are deposited on the back of the N ⁺ contact 5, P ⁺ contact 6, and SiC substrate 9 as ohmic contact metals, and deposited in a nitrogen atmosphere at 800°C-1000°C Anneal for 2-5 minutes to form an ohmic contact, thereby forming the source electrode 4 and the drain electrode 10. The silicon carbide device formed after step 108 is shown in FIG. 6g.

After the above steps, a new type of MOSFET device is formed. This device has a low on-resistance and is convenient for users to use. Before leaving the factory, the characteristics of the MOSFET device can be tested to determine whether it meets the requirements.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. a novel silicon carbide MOSFET, is characterized in that, comprising: SiC substrate (9), be arranged at described SiC substrate (9) top N ^-epitaxial loayer (8), be arranged at described N ^-two P traps (7) of epitaxial loayer (8) top, be arranged at the N of the mutual next-door neighbour on P trap (7) ⁺contact (5) and P ⁺contact (6), is arranged at the JFET district (11) in the middle of two P traps (7), is arranged at top, JFET district (11) and the SiO extended on P trap (7) ₂oxide layer (2), be arranged at SiO ₂the grid (1) of oxide layer (2) top, be arranged at the source electrode (4) of P trap (7) top, be arranged at the drain electrode (10) of described SiC substrate (9) below, and be arranged at described JFET district (11) and described SiO ₂between oxide layer (2) and the P extended on P trap (7) ^-epitaxial loayer (3).

2. novel silicon carbide MOSFET as claimed in claim 1, is characterized in that, described P ^-the thickness of epitaxial loayer (3) is 0.01 ~ 0.1um.

3. novel silicon carbide MOSFET as claimed in claim 1, is characterized in that, described P ^-epitaxial loayer (3) doping content is 1 × 10 ¹⁶cm ^-3~ 1 × 10 ¹⁷cm ^-3.

4. novel silicon carbide MOSFET as claimed in claim 3, is characterized in that, described P ^-the doped dielectric of epitaxial loayer (3) is aluminium or boron.

5. a manufacture method of novel silicon carbide MOSFET, is characterized in that, comprising:

At the upper extension N of SiC substrate (9) ^-epitaxial loayer (8);

At described N ^-epitaxial loayer (8) carrying out ion implantation and form two P traps (7), is JFET district (11) in the middle of described two P traps (7);

On described two P traps (7), carry out ion implantation respectively form N ⁺contact (5) and P ⁺contact (6);

In high temperature activation anneal stove, the device formed after above-mentioned steps is annealed at 1500 DEG C ~ 1850 DEG C temperature;

At described JFET district (11) top extension P ^-epitaxial loayer (3);

At described P ^-epitaxial loayer (3) top thermal oxidation SiO ₂oxide layer (2);

At described SiO ₂oxide layer (2) top depositing polysilicon forms grid (1);

Source electrode (4) is built respectively in described two P traps (7) top;

Drain electrode (10) is built in described SiC substrate (9) below.

6. method as claimed in claim 5, is characterized in that, described at the upper extension N of SiC substrate (9) ^-epitaxial loayer (8) specifically comprises:

In SiC substrate (9), epi dopant concentration is 1 × 10 ¹⁵cm ^-3~ 1 × 10 ¹⁶cm ^-3, growth thickness is the N of 5 ~ 35um ^-epitaxial loayer (8).

7. method as claimed in claim 5, is characterized in that, described at described N ^-epitaxial loayer (8) carries out ion implantation to form two P traps (7) and specifically comprise: at N ^-epitaxial loayer (8) carries out three times or four secondary ions injection Al ion, the formation growth degree of depth is 0.5 ~ 1.5um, doping content is 1 × 10 ¹⁸cm ^-3~ 5 × 10 ¹⁸cm ^-3two P traps (7);

Described ion implantation of carrying out on described two P traps (7) respectively forms N ⁺contact (5) and P ⁺contact (6) specifically comprises: carry out three times on each P trap (7) or four secondary ions injection Al ion, Formation Depth is 0.2 ~ 0.3um, doping content is 1 × 10 ¹⁹cm ^-3~ 5 × 10 ¹⁹cm ^-3p ⁺contact (6), then carries out three times or four secondary ions inject N ion, and in each P trap (7), Formation Depth is 0.2 ~ 0.3um, doping content is 1 × 10 ¹⁹cm ^-3~ 5 × 10 ¹⁹cm ^-3n ⁺contact (5).

8. method as claimed in claim 5, is characterized in that, described at described JFET district (11) top extension P ^-epitaxial loayer (3) specifically comprises:

In JFET district (11) top, extension one deck doping content is 1 × 10 ¹⁶cm ^-3~ 1 × 10 ¹⁷cm ^-3, thickness is the P of 0.01 ~ 0.1um ^-epitaxial loayer (3).

9. method as claimed in claim 5, is characterized in that, described at described P ^-epitaxial loayer (3) top thermal oxidation SiO ₂oxide layer (2) specifically comprises:

In high temperature oxidation furnace at 1200 DEG C ~ 1350 DEG C temperature, by P ^-the SiO of epitaxial loayer (3) dry oxygen thermal oxide growth 20nm ~ 60nm ₂oxide layer (2).

10. method as claimed in claim 5, is characterized in that, described at described SiO ₂oxide layer (2) top depositing polysilicon forms grid (1) and specifically comprises: at SiO ₂oxide layer (2) upper employing low-pressure chemical vapor phase deposition method deposit 0.1 ~ 1um, doping content are 1 × 10 ²⁰cm ^-3~ 3 × 10 ²⁰cm ^-3polysilicon, formed grid (1);

Described build source electrode (4) in described two P traps (7) top and build drain electrode (10) in described SiC substrate (9) below respectively specifically comprise: at described N ⁺contact (5), P ⁺contact (6) and SiC substrate (9) back side deposit 30 ~ 100nm Ti and 100 ~ 300nm Al alloy, as metal ohmic contact, and 2 ~ 5min formation ohmic contact of annealing in 800 DEG C ~ 1000 DEG C nitrogen atmospheres.