CN104409369A - Packaging assembly manufacturing method - Google Patents

Abstract

Disclosed is a method of manufacturing a package assembly, comprising: forming a lead frame on a substrate, the lead frame including a plurality of leads with a first surface exposed; mounting a plurality of levels of electronic components on a lead frame such that at least one level of electronic components is electrically connected to a first surface of at least one set of leads of the plurality of leads; and removing at least a portion of the substrate such that a second surface of the plurality of leads opposite the first surface is exposed for external connection. The method does not need to turn over the semiconductor structure in the manufacturing process, and can improve the yield of the packaging assembly, reduce the cost and improve the packaging quality.

Description

Packaging assembly manufacturing method

technical field

The present invention relates to semiconductor packaging, and in particular to a method of manufacturing a packaging assembly.

Background technique

With the increasing demand for miniaturization, light weight and multi-functionalization of electronic components, the requirements for semiconductor packaging density are getting higher and higher, so as to achieve the effect of reducing the package size. Therefore, a package assembly using a lead frame and containing multiple semiconductor dies has become a new hot spot. In such packages, the configuration of the plurality of semiconductor dies and their connection methods have a critical impact on the size and performance of the package.

Stacked multilayer package assemblies have been proposed in which multiple semiconductor dies are stacked on the same lead frame. The lowermost semiconductor die can be directly attached to the lead frame by solder. The semiconductor die on the upper layer may be secured to the top surface of the semiconductor die on the lower layer by the adhesive layer. Then, the upper semiconductor die is electrically connected to the lead frame by bonding wires. The semiconductor die integrated in a package assembly can be not only integrated circuit chips (such as power device chips and control chips of switching power supplies, etc.), but also discrete components (such as power plants, capacitors and resistors, etc.).

Compared with planar package components, stacked multilayer package components can reduce chip footprint, thereby reducing package size, while having shorter delay time and less noise. Accordingly, processes for forming multilayer package assemblies are of increasing interest.

However, stacking multiple semiconductor dies on the lead frame complicates the packaging process, for example, in the packaging process, the lead frame needs to be turned over, thereby reducing the yield of the package assembly and increasing the cost. In addition, in the packaging process, a part of the substrate carrying the lead frame is etched through. The thickness of the substrate must be large enough to provide the required mechanical support. As a result, it is difficult to miniaturize the size of packaged components.

Therefore, it is desired to further optimize the manufacturing method of the packaging component to reduce the complexity of the process.

Contents of the invention

In view of this, the object of the present invention is to provide a method for manufacturing a packaging component, so as to solve the problem of increased cost due to the complexity of the manufacturing process of the multilayer packaging component.

According to the present invention, there is provided a method for manufacturing a package assembly, comprising: forming a lead frame on a substrate, the lead frame including a plurality of leads exposed on a first surface; mounting electronic components on multiple levels on the lead frame, so that at least a level of electronic components electrically connected to a first surface of at least one set of the plurality of leads; and removing at least a portion of the substrate such that a second surface of the plurality of leads opposite the first surface is exposed for external connection.

Preferably, in the method, the step of forming the lead frame includes: forming a plurality of leads on the packaging substrate; and forming a mesa on at least another group of leads among the plurality of leads, the surface of the mesa is higher than the The above-mentioned first surface, and the surface heights of the mesas formed on different groups of leads in the at least another group of leads are different, wherein, in the step of mounting electronic components of multiple levels, the electronic components of at least another level are the same as the above-mentioned The first surface of the at least another set of leads of the plurality of leads is electrically connected.

Preferably, in the method, the plurality of leads are separated by trenches, and between the step of forming the plurality of leads and the step of forming the mesa, filling the trenches with encapsulation compound is also included.

Preferably, in the method, the step of forming the plurality of leads includes: forming a metal layer on the substrate; and patterning the metal layer into the plurality of leads by etching through a mask containing a pattern of the leads.

Preferably, in the method, the step of forming the plurality of leads includes: forming the plurality of leads by plating a metal material on the exposed surface of the substrate through a mask containing complementary patterns of the leads.

Preferably, in the method, the step of forming the plurality of leads includes: forming a mask on the substrate that contains complementary patterns of the leads; and patterning the surface layer of the substrate into the plurality of leads by etching.

Preferably, in the method, the step of forming the plurality of leads includes: patterning the surface layer of the substrate into the plurality of leads by stamping.

Preferably, in the method, the step of mounting electronic components on multiple levels on the lead frame comprises: starting from a first level adjacent to the lead frame, mounting electronic components level by level; and after mounting electronic components on all levels, using The encapsulant at least partially covers the lead frame and the electronic components, wherein the electronic components on the first level are electrically connected to the first surface of one set of leads in the at least one set of leads, and the electronic components on the subsequent level are connected to the at least another set of leads. Mesa electrical connections of corresponding sets of leads in the leads.

Preferably, in the method, the step of mounting electronic components on multiple levels on the lead frame includes: starting from a first level adjacent to the lead frame, mounting electronic components level by level and using encapsulant to at least partially cover the electronic components on the corresponding level , wherein, after installing the electronic components of one level and before installing the electronic components of the next level, the leads and the electronic components of the one level are at least partially covered with encapsulation material, the electronic components of the first level and the at least one set of leads The first surface of one set of leads in the at least one other set of leads is electrically connected, and the electronic components of the subsequent level are electrically connected with the mesas of the corresponding set of leads in the at least one other set of leads.

Preferably, in the method, before installing the electronic components on the next level, flattening the encapsulant on the one level to expose the first surface of the leads on the next level.

Preferably, in the method, in the step of mounting electronic components on multiple levels, the electronic components on at least one level form solder interconnections with the first surface of the at least one set of leads in the plurality of leads , and the electronic components at the at least another level form solder interconnections with the surface of the mesa.

Preferably, between the step of filling the trenches with encapsulant and the step of forming the mesas, a redistribution layer is formed, wherein the redistribution layer includes a plurality of conductor lines extending laterally and including A first surface and a second surface opposite to each other, wherein the first surfaces of the plurality of conductor lines contact the first surfaces of the plurality of lead wires.

Preferably, in the method, in the step of mounting electronic components on multiple levels, the electronic components on at least one level form solder interconnections with the second surface of at least one group of conductor lines of the plurality of conductor lines, And the electronic components of the at least another level form solder interconnections with the surface of the mesa.

According to the method according to the claims, between the step of installing electronic components on multiple levels on the lead frame and the step of removing the substrate, further comprising: attaching a heat sink on the surface of the encapsulation compound.

According to the method of claims, before attaching the heat sink on the surface of the encapsulation compound, it further comprises: smoothing the encapsulation compound and reducing the thickness of the top layer of the encapsulation compound by grinding.

In the above method of manufacturing a multilayer package assembly according to the present invention, the first surface of the lead is opposite to the substrate, and the second surface is in contact with the substrate. During the manufacturing process of the package assembly, the first surface of the lead is always placed upward, so that there is no need to flip the semiconductor structure. In addition, the substrate provides mechanical support throughout almost the entire packaging process and is not removed until the lead frame and electronic components have been encapsulated with the second encapsulant. In the final package assembly, the first surface of the lead provides the interconnection area with the electronic components inside the package structure, and the second surface provides the contact area with the external circuit (such as a printed circuit board, or PCB).

Since there is no need to flip the semiconductor structure in the above method, the packaging yield can be effectively improved and the packaging cost can be reduced.

During the packaging process, the substrate remains intact without being etched through until the final step of etching away. The substrate has better mechanical support in almost the entire packaging process, which is conducive to improving the quality of packaging. Since a sufficient mechanical supporting effect can be provided even if the thickness of the substrate is reduced, it facilitates miniaturization of package components.

Description of drawings

Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above-mentioned and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:

Figures 1a to 1g show cross-sectional views of various steps of a method of manufacturing a multilayer package assembly according to the prior art;

2a to 2g show cross-sectional views of various steps of a first embodiment of a method for manufacturing a multilayer package assembly according to the invention;

3a and 3b show cross-sectional views of some steps of a second embodiment of the method of manufacturing a multilayer package assembly according to the invention;

4a to 4d show cross-sectional views of some steps of a third embodiment of a method for manufacturing a multilayer package assembly according to the present invention; and

5a to 5e show cross-sectional views of some steps of a fourth embodiment of a method for manufacturing a multilayer package assembly according to the invention.

Detailed ways

Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. For simplicity, the package structure obtained after several steps can be described in one figure.

It should be understood that when describing a package structure, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may refer to being directly on another layer or another region, or on There are other layers or regions between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region. If it is to describe the situation directly on another layer or another area, the expression "directly on" or "on and adjacent to" will be used herein.

In the following, many specific details of the present invention are described, such as package structures, materials, dimensions, processing techniques and techniques, for a clearer understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

In the present application, the term "semiconductor structure" refers to a general designation of the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "electronic component" is not limited to a semiconductor die, and should be understood as a general package object, including semiconductor dies and discrete components (such as resistors, capacitors, inductors, diodes, transistors) and the like.

Figures 1a to 1g show cross-sectional views of various steps of a method of manufacturing a multilayer package assembly according to the prior art. The method includes forming a lead frame on a substrate and stacking multiple levels of electronic components on the lead frame.

The method eg starts with a stack comprising a substrate 101 (eg iron-nickel alloy) and a metal layer (eg Cu) thereon, wherein the substrate 101 acts as a support layer and will eventually be partly removed as a sacrificial layer. For example, by using a first mask, the metal layer is patterned into strip-shaped leads 102 by etching, as shown in FIG. 1 a . In etching, an etchant selectively removes exposed portions of the metal layer with respect to the underlying substrate 101 . The first mask is removed after etching.

The first surface of the leads 102 formed in the above steps is opposite to the substrate 101 , and the second surface is in contact with the substrate 101 .

Then, the exposed surfaces of the leads 102 and the substrate 101 are covered with a first encapsulant 103 (such as epoxy resin), as shown in FIG. 1 b . The thickness of the encapsulant 103 is at least sufficient to fill the trenches between adjacent leads 102 . For example, the encapsulation compound 103 is flattened by grinding, so that the first surface of the lead 102 is exposed again, as shown in FIG. 1c. For example, using a second mask, using a selective etchant, the substrate 101 is removed relative to the lead 102 and the encapsulant 103 in the mounting area of the substrate 101, thereby forming an opening that exposes the second surface of the lead 102, as shown in FIG. 1d . The first surface and the second surface are opposite to each other. The unetched portion of the substrate 101 provides mechanical support during the etching step. After exposing the second surface of the lead 102, the semiconductor structure is turned upside down. For example, a third mask is used to shield the entire second surface of a part of the leads, and to shield at least a part of the second surface of another part of the leads located at the periphery of the part of the leads. The mesa 104 is formed by plating (such as electroplating, electroless plating, etc.) the same metal material as the metal constituting the lead on the exposed surface of the other part of the lead 102 , as shown in FIG. 1 e . The part of leads 102 that is shielded serves as a first group of leads, and the other part of leads 102 forming a mesa serves as a second group of leads. The third mask is removed after the plating, thereby forming a lead frame 110 including two sets of leads 102 on the substrate 101 .

In the lead frame 110, the second surface of the lead 102 is placed upward. The second surfaces of the first group of leads 102 are directly exposed to provide interconnection regions. A mesa 104 is formed on a second surface of a second set of leads 102 for providing an interconnection region.

The first electronic component 120 is placed on the lead frame 110 . The internal circuit of the first electronic component 120 is electrically connected to the conductive bump 106 via a conductive via or the like. Solder balls 105 attached to the ends of conductive bumps 106 are in contact with interconnect regions of the first set of leads 102 . A reflow process is performed to melt the solder balls 105 to form solder 105 to fix the first electronic component 120 on the lead frame 110 . Then, the second electronic component 130 is placed on the lead frame 110 . The reflow process is performed again, and the second electronic component 130 is fixed on the second group of leads of the lead frame 110 by using the solder 107 , as shown in FIG. 1 g . Then, the lead frame 110 and the electronic components 120 , 130 are encapsulated with a second encapsulant 140 (such as epoxy resin), so as to form the encapsulation assembly 100 .

In the above method of manufacturing a multi-layer package assembly according to the prior art, the first surface of the lead 102 is opposite to the substrate 101 , and the second surface is in contact with the substrate 101 . The first surface of the lead 102 is initially placed facing upward. In the step shown in Figure 1e, the semiconductor structure is flipped over. This is because the mechanical strength of the etched substrate 101 is insufficient to support the lead frame 110 in subsequent processes. After turning over, the first surface of the lead 102 is placed downward, so that the first surface of the lead 102 itself can be used to provide mechanical support in subsequent steps.

In the final package assembly 100 , the first surface of the lead 102 is placed facing down for providing a contact area with external circuitry, and the second surface is placed facing up for providing an interconnection area with electronic components inside the package structure.

Since the semiconductor structure needs to be turned over in the above method, the operation process is relatively complicated, and it is not conducive to improving the yield of packaged devices, so that the cost of packaging cannot be effectively reduced.

2a to 2g show cross-sectional views of various steps of a first embodiment of a method for manufacturing a multilayer package assembly according to the invention. The method includes forming a lead frame on a substrate and stacking multiple levels of electronic components on the lead frame.

The method eg starts with a stack comprising a substrate 201 (eg iron-nickel alloy) and a metal layer (eg Cu) thereon, wherein the substrate 201 acts as a support layer and will eventually be partly removed as a sacrificial layer. For example, using a first mask containing a pattern of wiring, the metal layer is patterned into strip-shaped wiring 202 by etching, as shown in FIG. 2 a . In etching, an etchant selectively removes exposed portions of the metal layer with respect to the underlying substrate 201 . The first mask is removed after etching.

The first surface of the leads 202 formed in the above steps is opposite to the substrate 202 , and the second surface is in contact with the substrate 202 .

Then, the exposed surfaces of the leads 202 and the substrate 201 are covered with a first encapsulant 203 (such as epoxy resin), as shown in FIG. 2b. The thickness of the encapsulant 203 is at least sufficient to fill the trenches between adjacent leads 202 . The encapsulation compound 203 is flattened, for example by grinding, so that the first surface of the lead 202 is exposed again, as shown in FIG. 2c. For example, the second mask is used to block the entire first surface of a part of the leads, and to block at least a part of the first surface of another part of the leads located around the part of the leads. The mesa 204 is formed by plating the exposed surface of the other part of the lead 202 with the same metal material as the metal constituting the lead, as shown in FIG. 2d. The part of leads 202 that are shielded serves as a first group of leads, and the other part of leads 202 forming a mesa serves as a second group of leads. The second mask is removed after plating, thereby forming a lead frame 210 including two sets of leads 202 on the substrate 201 .

In the step of forming the mesas 204 , since the opening of the second mask is difficult to be precisely aligned with the lead 202 , the area of the second mask is generally slightly smaller than the cross-sectional area of the lead 202 (the cross-sectional area parallel to the opening). As a result, the surface area of the mesa 204 is slightly smaller than the surface area of the lead 202 to ensure that the mesa 204 is completely formed on the surface of the lead 202 and avoid forming the mesa 204 to connect the two connected leads 202 .

In the lead frame 210, the first surface of the lead 202 is placed facing upward. The first surface of the first group of leads 202 is directly exposed for providing an interconnection area. A mesa 204 is formed on a first surface of a second set of leads 202 for providing an interconnection region.

The first electronic component 220 is placed on the lead frame 210 . The internal circuit of the first electronic component 220 is electrically connected to the conductive bump 206 via a conductive via or the like. Solder balls 205 attached to the ends of conductive bumps 206 are in contact with interconnect regions of the first set of leads 202 . A reflow process is performed to melt the solder balls 205 to form solder 205 to fix the first electronic component 220 on the lead frame 210 . Then, the second electronic component 230 is placed on the lead frame 210 . The reflow process is performed again, and the second electronic component 230 is fixed on the mesa 204 of the second group of leads of the lead frame 210 by using the solder 207 , as shown in FIG. 2 e . Then, the lead frame 210 and the electronic components 220 and 230 are encapsulated with a second encapsulation material 240 (such as epoxy resin), as shown in FIG. 2f. For example, without using a mask, using a selective etchant, the substrate 201 is removed relative to the leads 202 and the encapsulation compound 203, thereby forming a second surface that exposes the leads 202, as shown in FIG. 2g, thereby forming the package assembly 200 .

The first electronic component 220 is, for example, a chip including a power device, such as a chip including a main power transistor in a power stage circuit of a switching power supply. The chip may also include a control circuit of the switching power supply, or a synchronous rectifier of the switching power supply. The second electronic component 230 includes, for example, an inductor in a switching power supply, and may also be a discrete component such as a capacitor or a resistor.

In a preferred embodiment, after the second encapsulation compound 240 is formed in the step shown in FIG. 2 f , a heat sink can be added on the surface of the second encapsulation compound 240 . The second encapsulation compound 240 is flattened, for example, by grinding, and the thickness of the top layer of the second encapsulation compound 240 is reduced, so as to reduce the encapsulation volume and improve heat dissipation efficiency. Then continue with the steps shown in FIG. 2g to remove the substrate 210 .

In an alternative embodiment, the step of forming the leads 202 on the substrate 201 begins with the substrate 201 (eg, an iron-nickel alloy), where the substrate 201 acts as a support layer and will eventually be partially removed as a sacrificial layer. For example a first mask is used which contains a complementary pattern of leads, ie the openings of the mask correspond to the pattern of leads. The first mask blocks a part of the surface of the substrate 201 . Strip-shaped leads 202 are formed by plating a metal material (such as Cu) on the exposed surface of the substrate 201 , as shown in FIG. 2 a . The first mask is removed after plating. Then, continue to execute the steps of FIG. 2 b to FIG. 2 g to form the package assembly 200 .

In another alternative embodiment, the step of forming the leads 202 on the substrate 201 begins with the substrate 201 (eg, an iron-nickel alloy). Leads 202 are formed on the surface of the substrate 201, for example by half-etching and/or punching process, as shown in FIG. 2a. Optionally, the encapsulation compound 203 is filled in the trenches between adjacent leads 202 . Then, continue to execute the steps of FIG. 2d to FIG. 2g to form the package assembly 200 .

Figures 3a and 3b show cross-sectional views of some steps of a second embodiment of a method for manufacturing a multilayer package assembly according to the invention. In the method according to the second embodiment, the lead frame 310 is first formed according to the steps shown in FIGS. 2a to 2d. The lead frame 310 is located on the substrate 301 and includes a first set of leads not forming a mesa and a second set of leads forming a mesa 304 . The surfaces of the first set of leads directly provide the interconnection area, and the mesas 304 of the second set of leads provide the interconnection area.

The difference from the first embodiment is that the method according to the second embodiment continues to execute the steps shown in Figs. 3a and 3b.

The first electronic component 320 is placed on the lead frame 310 . The internal circuit of the first electronic component 320 is electrically connected to the conductive bump 306 via a conductive via or the like. Solder balls 305 attached to the ends of conductive bumps 306 are in contact with interconnect regions of the first set of leads 302 . A reflow process is performed to melt the solder balls 305 to form solder 305 to fix the first electronic component 320 on the lead frame 310 . Then, the lead frame 310 and the electronic component 320 are encapsulated with a second encapsulant 340 (such as epoxy resin). The second encapsulation compound 340 is flattened, for example by grinding, to expose the mesa 304 of the second set of leads 302 . Then, the second electronic component 330 is placed on the second encapsulation compound 340 . The reflow process is performed again, and the second electronic component 330 is fixed on the mesa 304 of the second group of leads of the lead frame 310 by using the solder 307 . Then, the lead frame 310 and the electronic components 320 and 330 are encapsulated with a third encapsulation compound 350 (for example, epoxy resin), as shown in FIG. 3 a . For example, in the absence of a mask, a selective etchant is used to remove the substrate 301 relative to the leads 302 and the encapsulant 303, thereby forming a second surface exposing the leads 302, as shown in FIG. 3b, thereby forming a package assembly 300 .

4a to 4d show cross-sectional views of some steps of a third embodiment of a method for manufacturing a multilayer package assembly according to the invention. In the method according to the third embodiment, firstly, lead wires 402 are formed on a substrate 401 according to the steps shown in FIG. 2a. The first surface of the lead 402 is opposite to the substrate 401 , and the second surface is in contact with the substrate 401 .

The difference from the first embodiment is that the method according to the third embodiment continues to execute the steps shown in FIGS. 4a to 4d.

Then, for example, a first mask is used to shield the entire first surface of a part of the leads, and to shield at least a part of the first surface of another part of the leads located at the periphery of the part of the leads. The mesa 404 is formed by plating the exposed surface of the other part of the lead 402 with the same metal material as that of the lead, as shown in FIG. 4 a . The part of leads 402 that is shielded serves as a first group of leads, and the other part of leads 402 forming a mesa serves as a second group of leads. The first mask is removed after plating, thereby forming a lead frame 410 including two sets of leads 402 on the substrate 401 .

In the lead frame 410, the first surface of the lead 402 is placed facing upward. The first surface of the first set of leads in the leads 402 is directly exposed for providing an interconnection area. A mesa 404 is formed on the first surface of the second set of leads 402 for providing an interconnection region.

The first electronic component 420 is placed on the lead frame 410 . The internal circuit of the first electronic component 420 is electrically connected to the conductive bump 406 via a conductive via or the like. Solder balls 405 attached to the ends of conductive bumps 406 are in contact with the interconnection regions of the first set of leads 402 . A reflow process is performed to melt the solder balls 405 to form solder 405 to fix the first electronic component 420 on the lead frame 410 . Then, the second electronic component 430 is placed on the lead frame 410 . The reflow process is performed again, and the second electronic component 430 is fixed on the mesa 404 of the second group of leads of the lead frame 410 by using solder 407 , as shown in FIG. 4 b . Then, encapsulate the lead frame 410 and the electronic components 420 and 430 with an encapsulation material 440 (such as epoxy resin), as shown in FIG. 4c. For example, in the case of not using a mask, a selective etchant is used to remove the substrate 401 relative to the leads 402 and the encapsulation compound 403, thereby forming a second surface exposing the leads 402, as shown in FIG. 4d, thereby forming a package assembly 400 .

Compared with the method of the first embodiment, the method according to the third embodiment omits the step of filling the potting compound in the trench between the leads 402, and fills the potting compound 440 while encapsulating the lead frame and the electronic components. The groove between the leads 402 further simplifies the packaging process. And it has improved reliability due to the one-time encapsulant molding.

5a to 5e show cross-sectional views of some steps of a fourth embodiment of a method for manufacturing a multilayer package assembly according to the invention. In the method according to the fourth embodiment, a lead 502 is first formed on a substrate 501 according to the steps shown in FIGS. 2a to 2c. The first surface of the lead 502 is opposite to the substrate 501 , and the second surface is in contact with the substrate 501 . The trenches between the leads 502 are filled with a first encapsulant 503 (such as epoxy resin).

The difference from the first embodiment is that the method according to the fourth embodiment continues to execute the steps shown in FIGS. 5a to 5e.

A conductor layer is formed on the surface of the semiconductor structure by known plating or deposition processes. The plating process is, for example, one selected from electroplating and electroless plating. The deposition process is, for example, one selected from electron beam evaporation (EBM), chemical vapor deposition (CVD), atomic layer deposition (ALD), and sputtering.

The conductor layer is patterned into a redistribution layer (RDL) 508 by etching, for example using a first mask containing a redistribution pattern, as shown in FIG. 5a. In etching, the etchant selectively removes exposed portions of the conductor layer with respect to the underlying leads 502 and first encapsulant 503 . The first mask is removed after etching. The redistribution layer 508 includes a plurality of conductor lines contacting the top surfaces of the leads 502 so that the conductive paths can extend laterally.

Then, for example, a second mask is used to shield the entire first surface of a part of the conductor lines of the redistribution layer 508 and at least a part of the first surface of another part of the conductor lines of the redistribution layer 508 located around the part of the leads. The mesa 504 is formed by plating the exposed surface of another part of the conductor line of the redistribution layer 508 with the same metal material as the lead wire, as shown in FIG. 5 b . As a result, no mesa is formed on the redistribution layer 508 of the first group of wires 502 contacted, and a mesa is formed on the redistribution layer 508 of the second group of wire contacts. The second mask is removed after plating, thereby forming a lead frame 510 including two sets of leads 502 on the substrate 501 .

In the lead frame 510, the first surface of the lead 502 is placed facing upward. The first surface of the first set of leads in the leads 502 is directly exposed for providing an interconnection area. A mesa 504 is formed on the first surface of the second set of leads 502 for providing an interconnection region.

The first electronic component 520 is placed on the lead frame 510 . The internal circuit of the first electronic component 520 is electrically connected to the conductive bump 506 via a conductive via or the like. The solder balls 505 attached to the ends of the conductive bumps 506 are in contact with a part of the conductor lines in the redistribution layer 508 , so as to be electrically connected to the first set of leads in the leads 502 . A reflow process is performed to melt the solder balls 505 to form solder 505 to fix the first electronic component 520 on the lead frame 510 . Then, the second electronic component 530 is placed on the lead frame 510 . The reflow process is performed again, and the second electronic component 530 is fixed on the table 504 by solder 507 , as shown in FIG. 5 c . Then, encapsulate the lead frame 510 and the electronic components 520 and 530 with an encapsulation material 540 (such as epoxy resin), as shown in FIG. 5c. For example, without using a mask, using a selective etchant, the substrate 501 is removed relative to the leads 502 and the encapsulant 503, thereby forming a second surface that exposes the leads 502, as shown in FIG. 5d, thereby forming a package assembly 500 .

Compared with the method of the first embodiment, the method according to the fourth embodiment provides the redistribution layer 508 above the lead frame 510 . The redistribution layer 508 can connect the electrode terminals on the chip that are far apart and need to be connected, so that there is no need to connect outside the chip and reduce external interference. And when the upper layer of electronic components needs to be connected with the lower layer of chips, it can also be realized through the redistribution layer 508 . For example, one end of the inductor in the switching power supply needs to be connected to the LX end, which can be realized through the redistribution layer 508 .

In each of the above embodiments of the method of manufacturing a multilayer package assembly according to the present invention, the first surface of the lead is opposite to the substrate, and the second surface is in contact with the substrate. During the manufacturing process of the package assembly, the first surface of the lead is always placed upward, so that there is no need to flip the semiconductor structure.

During the packaging process, the substrate remains intact without being etched through until the final step of etching away. The substrate has better mechanical support in almost the entire packaging process, which is conducive to improving the quality of packaging. Since a sufficient mechanical supporting effect can be provided even if the thickness of the substrate is reduced, it facilitates miniaturization of package components.

In the final package assembly, the first surface of the lead provides the interconnection area with the electronic components inside the package structure, and the second surface provides the contact area with the external circuit (such as a printed circuit board, or PCB).

Since there is no need to flip the semiconductor structure in the above method, the packaging yield can be effectively improved and the packaging cost can be reduced. Moreover, the substrate has better mechanical support in almost the entire packaging process, which is conducive to improving the quality of packaging.

It should be noted that in this article, relational terms such as first and second etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Embodiments according to the present invention are described above, and these embodiments do not describe all details in detail, nor do they limit the invention to only the specific embodiments described. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modification on the basis of the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (15)

1. A method of manufacturing a packaged assembly, comprising: forming a lead frame on the substrate, the lead frame including a plurality of leads exposed on the first surface; Mounting multiple levels of electronic components on the lead frame such that at least one level of electronic components is electrically connected to a first surface of at least one set of leads of the plurality of leads; and At least a portion of the substrate is removed such that a second surface of the plurality of leads opposite to the first surface is exposed for external connection. 2. The method of claim 1, wherein the step of forming a lead frame comprises: forming a plurality of leads on the package substrate; and A mesa is formed on at least another set of leads of the plurality of leads, the surface of the mesa is higher than the first surface, and the surface height of the mesa formed on a different set of leads of the at least another set of leads is different, Wherein, in the step of mounting electronic components on multiple levels, at least another level of electronic components is electrically connected to the first surface of the at least another group of leads among the plurality of leads. 3. The method according to claim 2, wherein the plurality of leads are separated by trenches, and between the step of forming the plurality of leads and the step of forming the mesa, further comprising filling the trenches with encapsulant. 4. The method of claim 2, wherein the step of forming a plurality of leads comprises: forming a metal layer on the substrate; and The metal layer is patterned into the plurality of leads by etching through a mask containing the lead pattern. 5. The method of claim 2, wherein the step of forming a plurality of leads comprises: The plurality of leads are formed by plating a metallic material on the exposed surface of the substrate through a mask containing a complementary pattern of leads. 6. The method of claim 2, wherein the step of forming a plurality of leads comprises: forming a mask comprising a complementary pattern of leads on the substrate; and The surface layer of the substrate is patterned into the plurality of leads by etching. 7. The method of claim 2, wherein the step of forming a plurality of leads comprises: The surface layer of the substrate is patterned into the plurality of leads by stamping. 8. The method of claim 2, wherein the step of mounting multiple levels of electronic components on the lead frame comprises: Electronic components are mounted layer by layer starting from the first layer adjacent to the lead frame; and After mounting the electronic components at all levels, at least partially cover the lead frame and electronic components with encapsulant, Wherein, the electronic components of the first layer are electrically connected to the first surface of a group of leads in the at least one group of leads, and the electronic components of the subsequent layer are electrically connected to the mesa of the corresponding group of leads in the at least another group of leads . 9. The method of claim 2, wherein the step of mounting multiple levels of electronic components on the lead frame comprises: Starting from the first level adjacent to the lead frame, mounting electronic components layer by layer and covering the electronic components of the corresponding layer with encapsulant at least partially, Wherein, after installing the electronic components on one level and before installing the electronic components on the next level, at least partially covering the leads and the electronic components on the one level with encapsulation material, Electronic components of a first level are electrically connected to a first surface of one set of leads of the at least one set of leads, and electronic components of a subsequent level are electrically connected to mesas of a corresponding set of leads of the at least another set of leads. 10 . The method according to claim 9 , further comprising flattening the encapsulant on one level to expose the first surface of the leads on the next level before mounting the electronic components on the next level. 11 . 11. The method according to claim 2, wherein, in the step of mounting electronic components on multiple levels, said at least one level of electronic components is connected to the first of said at least one set of leads among said plurality of leads. The surface forms solder interconnections, and the electronic components of the at least another level form solder interconnections with the surface of the mesa. 12. The method according to claim 3, further comprising forming a redistribution layer between the step of filling the trench with encapsulant and the step of forming the mesa, wherein the redistribution layer includes a plurality of conductor lines, the A plurality of conductor lines extends laterally and includes first and second surfaces opposite to each other, wherein the first surfaces of the plurality of conductor lines contact the first surfaces of the plurality of leads. 13. The method according to claim 12, wherein, in the step of mounting electronic components on multiple levels, said at least one level of electronic components is connected to the second surface of at least one set of conductor lines of said plurality of conductor lines Solder interconnects are formed, and the at least another level of electronic components form solder interconnects with the surface of the mesa. 14. The method according to claim 1, between the step of mounting electronic components on multiple levels on the lead frame and the step of removing the substrate, further comprising: attaching a heat sink on the surface of the packaging material. 15. The method according to claim 14, before attaching the heat sink on the surface of the encapsulant, further comprising: smoothing the encapsulant and reducing the thickness of the top layer of the encapsulant by grinding.