CN104409486B - Low subthreshold oscillation range and high voltage withstanding insulated gate tunneling transistor and preparing method thereof - Google Patents

Abstract

The invention relates to a low subthreshold swing high withstand voltage insulated gate tunneling transistor, which introduces a low impurity concentration withstand voltage layer structure into the collector junction and emitter junction to improve the forward and reverse withstand voltage capabilities of the device. The extremely sensitive correlation between the resistance through the insulating layer and the electric field strength in the tunneling insulating layer enables lower subthreshold swing and better switching characteristics. By using the tunneling current generated on the insulating tunneling layer as the driving current of the collector current, better forward current conduction characteristics are achieved compared with common semiconductor band-to-band tunneling field effect transistors. The invention also proposes a specific manufacturing method of the low sub-threshold swing high withstand voltage insulated gate tunneling transistor. Therefore, the working characteristic of the nanoscale integrated circuit unit is significantly improved, and is suitable for popularization and application.

Description

Low subthreshold swing high withstand voltage insulated gate tunneling transistor and manufacturing method thereof

Technical field:

The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a low subthreshold swing, high withstand voltage insulating gate tunneling transistor and a manufacturing method thereof, which are suitable for manufacturing high-performance ultra-high integrated integrated circuits.

Background technique:

At present, the continuous shortening of the channel length of integrated circuit unit metal oxide semiconductor field effect transistors (MOSFETs) has led to the increase of the subthreshold swing of the device, which has brought about serious degradation of switching characteristics and a significant increase in static power consumption, etc. short channel effect. Although the degradation of the device performance can be alleviated by improving the gate electrode structure, when the device size is further reduced to below 50 nm, even with the optimized gate electrode structure, the subthreshold swing of the device will also decrease As the channel length of the device is further reduced, the short channel effect will again lead to the deterioration of device performance in the sub-50 nanometer field; in addition, due to the A steep abrupt PN junction is formed between them. With the continuous reduction of the channel length, when the drain-source voltage is large, this steep abrupt PN junction will have a breakdown effect, which will seriously affect the forward and reverse directions of MOSFETs. Pressure characteristics.

In order to solve the problem of physical size limit of MOSFETs devices, Tunneling Field Effect Transistors (TFETs) are proposed. Because of their potential to have better switching characteristics and lower power consumption, it is possible to replace MOSFETs devices and become the next generation of ultra-large-scale Integrated circuit logic unit or memory unit. However, compared with MOSFETs devices, its disadvantage is that the subthreshold slope only partially exceeds MOSFETs devices, and the forward conduction current is very small.

In order to improve the electrical characteristics of TFETs, the current main solution is to generate the tunneling part of the device by introducing materials with a narrower bandgap such as compound semiconductors, silicon germanium or germanium, so as to improve the subthreshold slope and increase the conductance. Pass current. However, such an approach not only increases the production cost, but also increases the difficulty of the process. In addition, the use of high dielectric constant insulating materials as the insulating dielectric layer between the gate and the substrate can only improve the control ability of the gate to the electric field distribution of the channel, but cannot essentially increase the tunneling probability of silicon materials, so The improvement of electrical characteristics such as sub-threshold slope conduction current is very limited.

Invention content:

purpose of invention

In order to significantly improve the forward and reverse withstand voltage characteristics of sub-50nm-scale devices on the premise of being compatible with existing silicon-based process technologies, significantly reduce the sub-threshold swing of basic unit devices in nanoscale integrated circuits, and ensure that the devices are in the boost switch The invention provides a low sub-threshold swing high withstand voltage insulated gate tunneling transistor suitable for the manufacture of high-performance ultra-high integration integrated circuits and a manufacturing method thereof.

Technical solutions

The present invention is achieved through the following technical solutions:

Low sub-threshold swing high withstand voltage insulated gate tunneling transistor, the substrate 1 uses a single crystal silicon wafer as the substrate for forming the device, or uses an SOI wafer as the substrate for forming the device; a withstand voltage layer 2 is formed above the substrate The emitter region 3, the moderately doped base region 4 and the collector region 5 are isolated from each other by the withstand voltage layer 2; the heavily doped base region 6 is located above the moderately doped base region 4; the emitter 10 is located at the emitter above the region 3; the collector 11 is above the collector region 5; the conductive layer 7 is above the heavily doped base region 6; the tunneling insulating layer 8 is above the conductive layer 7; the gate electrode 9 is located at the tunneling insulating layer 8 above; the blocking insulating layer 12 is located between the device units and between the electrodes, and plays an isolation role between the device units and the electrodes.

In order to achieve the device functions described in the present invention, the present invention proposes a low sub-threshold swing high withstand voltage insulated gate tunneling transistor, whose core structural features are:

The conductive layer 7, the tunnel insulating layer 8 and the gate electrode 9 are isolated from the emitter 10 and the emitter region 3 by a blocking insulating layer 12; the conductive layer 7, the tunnel insulating layer 8 and the gate electrode 9 are connected to the collector electrode 11 and the collector The regions 5 are separated by a blocking insulating layer 12; the adjacent emitter regions 3 and collector regions 5 are separated from each other by a blocking insulating layer 12; the adjacent emitters 10 and collectors 11 are separated from each other by a blocking insulating layer 12 Isolation: Adjacent voltage-resistant layers 2 are isolated from each other by a blocking insulating layer 12 .

The tunneling insulating layer 8 is an insulating layer for generating insulating gate tunneling current, and its thickness is less than 1 nanometer.

The impurity concentration of the pressure-resistant layer 2 is lower than 10 ¹⁶ per cubic centimeter;

The moderately doped base region 4 has the same doping type as the heavily doped base region 6, and has the opposite doping type to the emitter region 3 and the collector region 5, and its doping concentration is lower than 10 ¹⁷ per cubic centimeter ;

The doping concentration of the heavily doped base region 6 is not lower than 10 ¹⁸ per cubic centimeter;

The bottom of the conductive layer 7 forms ohmic contact with the heavily doped base region 6 and is made of metal material or heavily doped polysilicon with the same impurity type as the heavily doped base region 6 and a doping concentration higher than 10 ¹⁹ per cubic centimeter.

The gate electrode 9 is an electrode for controlling the tunneling effect of the tunneling insulating layer 8 , and is an electrode for controlling the turning on and off of the device.

Low sub-threshold swing high withstand voltage insulated gate tunneling transistor, taking N-type as an example, emitter region 3, base region 4 and collector region 5 are respectively N region, P region and N region, and its specific working principle is as follows: When the collector electrode 11 is positively biased and the gate electrode 9 is at a low potential, there is no sufficient potential difference formed between the gate electrode 9 and the conductive layer 7. At this time, the tunneling insulating layer 8 is in a high-resistance state, and no obvious tunneling current passes through. Therefore, the withstand voltage emitter junction formed by the conductive layer 7, the heavily doped base region 6, the moderately doped base region 4, the withstand voltage layer 2 and the emitter region 3 does not have a large enough current to drive the low sub-threshold swing high Voltage-resistant insulated gate tunneling transistor, that is, the device is in the off state; as the voltage of the gate electrode 9 gradually increases, the potential difference between the gate electrode 9 and the conductive layer 7 gradually increases, so that the voltage between the gate electrode 9 and the conductive layer 7 The electric field intensity in the tunneling insulating layer 8 between them gradually increases accordingly. When the electric field intensity in the tunneling insulating layer 8 is below the critical value, the tunneling insulating layer 8 still maintains a good high-resistance state, and the gate electrode The potential difference between 9 and the emitter 10 is almost completely dropped on the tunneling insulating layer 8, which makes the potential difference between the conductive layer 7 connected to the heavily doped base region 6 and the emitter region extremely small, so that the emitter region is almost No current flows, so the device remains in a good off state, and when the electric field strength in the tunneling insulating layer 8 is above a critical value, the tunneling insulating layer 8 will generate a significant tunneling current due to the tunneling effect, And the tunneling current will rise steeply at a very fast speed with the increase of the potential of the gate electrode 9, which makes the tunneling insulating layer 8 rapidly switch from a high resistance state to a low resistance state within a small range of potential changes of the gate electrode. state, when the tunneling insulating layer 8 is in a low-resistance state, the resistance formed by the tunneling insulating layer 8 between the gate electrode 9 and the conductive layer 7 is much smaller than the resistance formed between the conductive layer 7 and the emitter 3, which means The withstand voltage emitter junction formed by the conductive layer 7, the heavily doped base region 6, the moderately doped base region 4, the withstand voltage layer 2 and the emitter region 3 forms a sufficiently large forward bias voltage, and the tunneling Under the action of the effect, a large amount of electron movement occurs on the upper and lower sides of the tunneling insulating layer 8, which is caused by the conductive layer 7, the heavily doped base region 6, the moderately doped base region 4, the withstand voltage layer 2 and the emitter region 3. The formed withstand voltage emitter junction provides a sufficient current source to drive a low subthreshold swing high withstand voltage IGST, that is, the device is in an on state;

The low sub-threshold swing high withstand voltage insulated gate tunneling transistor uses the withstand voltage layer 2 to improve the forward and reverse withstand voltage characteristics of the device. Taking an N-type device as an example, when the collector 11 is positively biased relative to the emitter 10, it consists of a conductive layer 7, a heavily doped base region 6, a moderately doped base region 4, a withstand voltage layer 2 and a collector region. The collector junction is in the reverse biased state, and the moderately doped base region 4 and the withstand voltage layer 2 located between the heavily doped base region and the emitter region have an anti-breakdown protection effect on the reverse biased collector junction, which can significantly improve the device Forward withstand voltage capability; when the collector 11 is reverse-biased relative to the emitter 10, it consists of a conductive layer 7, a heavily doped base region 6, a moderately doped base region 4, a withstand voltage layer 2 and an emitter region 3 The emitter junction is in the reverse bias state, and the moderately doped base region 4 and the withstand voltage layer 2 between the heavily doped base region 6 and the emitter region 3 have a breakdown protection effect on the reverse-biased emitter junction, which can significantly improve the device reverse withstand voltage capability;

The low sub-threshold swing high withstand voltage insulated gate tunneling transistor uses the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, and selects an insulating material with a suitable dielectric constant, and the tunneling By properly adjusting the thickness of the insulating layer 8, the tunneling insulating layer 8 can realize the transition between the high-resistance state and the low-resistance state within the extremely small potential change interval of the gate electrode 9, compared with MOSFETs, TFETs or Ordinary bipolar transistors, can achieve lower subthreshold swing and thus better switching characteristics.

Low sub-threshold swing and high withstand voltage insulated gate tunneling transistor, the tunneling current generated on the insulating tunneling layer is used as the driving current of the collector current, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands as the conduction of the device. Compared with the current flow, it has better forward current conduction characteristics.

Advantages and effects

The present invention has following advantage and beneficial effect:

1. Good forward voltage and reverse voltage characteristics

The low sub-threshold swing high withstand voltage insulated gate tunneling transistor uses the withstand voltage layer 2 to improve the forward and reverse withstand voltage characteristics of the device. Taking an N-type device as an example, when the collector 11 is positively biased relative to the emitter 10, it consists of a conductive layer 7, a heavily doped base region 6, a moderately doped base region 4, a withstand voltage layer 2 and a collector region. The collector junction is in the reverse biased state, and the moderately doped base region 4 and the withstand voltage layer 2 located between the heavily doped base region and the emitter region have an anti-breakdown protection effect on the reverse biased collector junction, which can significantly improve the device Forward withstand voltage capability; when the collector 11 is reverse-biased relative to the emitter 10, it consists of a conductive layer 7, a heavily doped base region 6, a moderately doped base region 4, a withstand voltage layer 2 and an emitter region 3 The emitter junction is in the reverse bias state, and the moderately doped base region 4 and the withstand voltage layer 2 between the heavily doped base region 6 and the emitter region 3 have a breakdown protection effect on the reverse-biased emitter junction, which can significantly improve the device reverse withstand voltage capability;

2. Better switching characteristics

The low sub-threshold swing high withstand voltage insulated gate tunneling transistor uses the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, and selects an insulating material with an appropriate dielectric constant to control the tunneling By properly adjusting the thickness of the insulating layer 8, the tunneling insulating layer 8 can realize the transition between the high-resistance state and the low-resistance state within the extremely small potential change interval of the gate electrode 9, compared with MOSFETs, TFETs or Ordinary bipolar transistors, can achieve lower subthreshold swing and thus better switching characteristics.

3. Better forward current conduction characteristics

Low sub-threshold swing and high withstand voltage insulated gate tunneling transistor, the tunneling current generated on the insulating tunneling layer is used as the driving current of the collector current, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands as the conduction of the device. Compared with the current flow, it has better forward current conduction characteristics.

Description of drawings

FIG. 1 is a schematic diagram of a two-dimensional structure of a low subthreshold swing high withstand voltage insulated gate tunneling transistor formed on a bulk silicon substrate in the present invention;

Figure 2 is a schematic diagram of Step 1,

Figure 3 is a schematic diagram of step two,

Figure 4 is a schematic diagram of step three,

Figure 5 is a schematic diagram of step four,

Figure 6 is a schematic diagram of step five,

Figure 7 is a schematic diagram of step six,

Figure 8 is a schematic diagram of step seven,

Figure 9 is a schematic diagram of Step 8,

Figure 10 is a schematic diagram of step nine,

Figure 11 is a schematic diagram of step ten,

Figure 12 is a schematic diagram of step eleven,

Fig. 13 is a schematic diagram of step twelve.

Explanation of reference signs:

1. Substrate; 2. Voltage withstand layer; 3. Emitter region; 4. Moderately doped base region; 5. Collector region; 6. Heavily doped base region; 7. Conductive layer; 8. Tunneling insulating layer 9. Gate electrode; 10. Emitter; 11. Collector; 12. Blocking insulating layer.

detailed description

Below in conjunction with accompanying drawing, the present invention will be further described:

Figure 1 is a schematic diagram of a two-dimensional structure of a low subthreshold swing high withstand voltage insulated gate tunneling transistor formed on a bulk silicon substrate according to the present invention; specifically, it includes a single crystal silicon substrate 1; a withstand voltage layer 2; an emitter region 3; Moderately doped base region 4; collector region 5; heavily doped base region 6; conductive layer 7; tunnel insulating layer 8; gate electrode 9; emitter 10; collector 11; blocking insulating layer 12.

Low sub-threshold swing high withstand voltage insulated gate tunneling transistor, the substrate 1 uses a single crystal silicon wafer as the substrate for forming the device, or uses an SOI wafer as the substrate for forming the device; a withstand voltage layer 2 is formed above the substrate The emitter region 3, the moderately doped base region 4 and the collector region 5 are isolated from each other by the withstand voltage layer 2; the heavily doped base region 6 is located above the moderately doped base region 4; the emitter 10 is located at the emitter above the region 3; the collector 11 is above the collector region 5; the conductive layer 7 is above the heavily doped base region 6; the tunneling insulating layer 8 is above the conductive layer 7; the gate electrode 9 is located at the tunneling insulating layer 8 above; the blocking insulating layer 12 is located between the device units and between the electrodes, and plays an isolation role between the device units and the electrodes.

In order to achieve the device functions described in the present invention, the present invention proposes a low sub-threshold swing high withstand voltage insulated gate tunneling transistor, whose core structural features are:

1. The tunneling insulating layer 8 is an insulating layer used to generate an insulating gate tunneling current, and its thickness is less than 1 nanometer. It can be a silicon dioxide layer or an insulating material layer with a higher dielectric constant, such as: two Hafnium oxide, silicon nitride, aluminum oxide, etc., but not limited thereto.

2. The doping concentration of the voltage-resistant layer 2 is lower than 10 ¹⁶ per cubic centimeter;

3. The moderately doped base region 4 has the same doping type as the heavily doped base region 6, and has the opposite doping type to the emitter region 3 and the collector region 5, and its doping concentration is lower than 10 ¹⁷ per Cubic centimeter;

4. The doping concentration of the heavily doped base region 6 is not lower than 10 ¹⁸ per cubic centimeter;

5. The bottom of the conductive layer 7 forms an ohmic contact with the heavily doped base region 6, and is made of a metal material, or is heavily doped with the same impurity type as the heavily doped base region 6 and a doping concentration higher than 10 ¹⁹ per cubic centimeter polysilicon.

6. The gate electrode 9 is an electrode that controls the tunneling effect of the tunneling insulating layer 8, and is an electrode that controls the turning on and off of the device.

Low sub-threshold swing high withstand voltage insulated gate tunneling transistor, taking N-type as an example, emitter region 3, base region 4 and collector region 5 are respectively N region, P region and N region, and its specific working principle is as follows: When the collector electrode 11 is positively biased and the gate electrode 9 is at a low potential, there is no sufficient potential difference formed between the gate electrode 9 and the conductive layer 7. At this time, the tunneling insulating layer 8 is in a high-resistance state, and no obvious tunneling current passes through. Therefore, the withstand voltage emitter junction formed by the conductive layer 7, the heavily doped base region 6, the moderately doped base region 4, the withstand voltage layer 2 and the emitter region 3 does not have a large enough current to drive the low sub-threshold swing high Voltage-resistant insulated gate tunneling transistor, that is, the device is in the off state; as the voltage of the gate electrode 9 gradually increases, the potential difference between the gate electrode 9 and the conductive layer 7 gradually increases, so that the voltage between the gate electrode 9 and the conductive layer 7 The electric field intensity in the tunneling insulating layer 8 between them gradually increases accordingly. When the electric field intensity in the tunneling insulating layer 8 is below the critical value, the tunneling insulating layer 8 still maintains a good high-resistance state, and the gate electrode The potential difference between 9 and the emitter 10 is almost completely dropped on the tunneling insulating layer 8, which makes the potential difference between the conductive layer 7 connected to the heavily doped base region 6 and the emitter region extremely small, so that the emitter region is almost No current flows, so the device remains in a good off state, and when the electric field strength in the tunneling insulating layer 8 is above a critical value, the tunneling insulating layer 8 will generate a significant tunneling current due to the tunneling effect, And the tunneling current will rise steeply at a very fast speed with the increase of the potential of the gate electrode 9, which makes the tunneling insulating layer 8 rapidly switch from a high resistance state to a low resistance state within a small range of potential changes of the gate electrode. state, when the tunneling insulating layer 8 is in a low-resistance state, the resistance formed by the tunneling insulating layer 8 between the gate electrode 9 and the conductive layer 7 is much smaller than the resistance formed between the conductive layer 7 and the emitter 3, which means The withstand voltage emitter junction formed by the conductive layer 7, the heavily doped base region 6, the moderately doped base region 4, the withstand voltage layer 2 and the emitter region 3 forms a sufficiently large forward bias voltage, and the tunneling Under the action of the effect, a large amount of electron movement occurs on the upper and lower sides of the tunneling insulating layer 8, which is caused by the conductive layer 7, the heavily doped base region 6, the moderately doped base region 4, the withstand voltage layer 2 and the emitter region 3. The formed withstand voltage emitter junction provides a sufficient current source to drive a low subthreshold swing high withstand voltage IGST, that is, the device is in an on state;

The low sub-threshold swing high withstand voltage insulated gate tunneling transistor uses the withstand voltage layer 2 to improve the forward and reverse withstand voltage characteristics of the device. Taking an N-type device as an example, when the collector 11 is positively biased relative to the emitter 10, it consists of a conductive layer 7, a heavily doped base region 6, a moderately doped base region 4, a withstand voltage layer 2 and a collector region. The collector junction is in the reverse biased state, and the moderately doped base region 4 and the withstand voltage layer 2 located between the heavily doped base region and the emitter region have an anti-breakdown protection effect on the reverse biased collector junction, which can significantly improve the device Forward withstand voltage capability; when the collector 11 is reverse-biased relative to the emitter 10, it consists of a conductive layer 7, a heavily doped base region 6, a moderately doped base region 4, a withstand voltage layer 2 and an emitter region 3 The emitter junction is in the reverse bias state, and the moderately doped base region 4 and the withstand voltage layer 2 between the heavily doped base region 6 and the emitter region 3 have a breakdown protection effect on the reverse-biased emitter junction, which can significantly improve the device reverse withstand voltage capability;

The low sub-threshold swing high withstand voltage insulated gate tunneling transistor uses the extremely sensitive relationship between the impedance of the tunneling insulating layer and the electric field strength in the tunneling insulating layer, and selects an insulating material with a suitable dielectric constant, and the tunneling By properly adjusting the thickness of the insulating layer 8, the tunneling insulating layer 8 can realize the transition between the high-resistance state and the low-resistance state within the extremely small potential change interval of the gate electrode 9, compared with MOSFETs, TFETs or Ordinary bipolar transistors, can achieve lower subthreshold swing and thus better switching characteristics.

Low sub-threshold swing and high withstand voltage insulated gate tunneling transistor, the tunneling current generated on the insulating tunneling layer is used as the driving current of the collector current, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands as the conduction of the device. Compared with the current flow, it has better forward current conduction characteristics.

The specific manufacturing process steps of the unit and array of the low sub-threshold swing high withstand voltage insulated gate tunneling transistor proposed by the present invention on the bulk silicon wafer are as follows:

Step 1: Provide a bulk silicon wafer substrate 1, and form a rectangular parallelepiped single crystal silicon island array region as shown in Figure 2 on the provided substrate 1 through photolithography, etching and other processes, and initially form a withstand voltage layer 2, and this region is used to further form the withstand voltage layer 2, emitter region 3, moderately doped base region 4, collector region 5 and heavily doped base region 6 of the device;

Step 2, as shown in FIG. 3 , after depositing an insulating medium above the wafer, the surface is planarized, and a blocking insulating layer 12 is preliminarily formed;

Step 3, as shown in FIG. 4 , through an ion implantation process, an emitter region 3 and a collector region 5 are formed on each rectangular parallelepiped single crystal silicon island array;

Step 4. As shown in FIG. 5 , the moderately doped base region 4 is preliminarily formed through the ion implantation process and finally the withstand voltage layer 2 is formed. Conversely, concentrations below 10 ¹⁷ per cubic centimeter;

Step 5. As shown in FIG. 6 , a heavily doped base region 6 is formed through an ion implantation process, and finally a moderately doped base region 4 is formed, and the doping concentration of the heavily doped base region 6 is higher than 10 ¹⁸ per cubic centimeter;

Step 6, as shown in Figure 7, deposit metal or doped heavily doped polysilicon with the same type of impurity as the heavily doped base region on the surface of the wafer, with a concentration higher than 10 ¹⁹ per cubic centimeter, and form it by etching Conductive layer 7;

Step 7. As shown in FIG. 8 , after depositing an insulating medium above the wafer, the surface is planarized and the conductive layer 7 is exposed, and a blocking insulating layer 12 is further formed;

Step 8, as shown in FIG. 9 , deposit a tunneling insulating layer dielectric above the wafer, and form a tunneling insulating layer 8 through an etching process;

Step 9, as shown in FIG. 10 , after depositing an insulating medium on the wafer, planarize the surface and expose the tunneling insulating layer 8, and further form a blocking insulating layer 12;

Step ten, as shown in FIG. 11 , deposit metal or heavily doped polysilicon on the wafer, and form the gate electrode 9 through an etching process;

Step eleven, as shown in FIG. 12 , deposit an insulating dielectric layer on the wafer and planarize the surface, further forming a blocking insulating layer 12;

Step 12, as shown in FIG. 13 , etch through holes for forming the emitter 10 and the collector 11 above the emitter region 3 and the collector region 5 through an etching process, and deposit The metal layer is used to fill the through hole with metal, and then the metal layer is etched to form the emitter 10 and the collector 11 .

Claims (7)

1. The insulated gate tunneling transistor is characterized in that: the substrate (1) uses a single crystal silicon wafer as the substrate for forming the device or uses an SOI wafer as the substrate for forming the device; a withstand voltage layer (2) is formed above the substrate ); the emitter region (3), the moderately doped base region (4) and the collector region (5) are isolated from each other by the withstand voltage layer (2); the heavily doped base region (6) is located in the moderately doped Above the base region (4); the emitter (10) is located above the emitter region (3); the collector (11) is located above the collector region (5); the conductive layer (7) is located on the heavily doped base region (6 ); the tunneling insulating layer (8) is located above the conductive layer (7); the gate electrode (9) is located above the tunneling insulating layer (8); the blocking insulating layer (12) is located between the insulated gate tunneling transistor unit Between and above a single insulated gate tunneling transistor; the impurity concentration of the withstand voltage layer (2) is lower than 10 ¹⁶ per cubic centimeter; the doping concentration of the moderately doped base region (4) is lower than 10 ¹⁷ per cubic centimeter; heavy The doping concentration of the doped base region (6) is not lower than 10 ¹⁸ per cubic centimeter. 2. The insulated gate tunneling transistor according to claim 1, characterized in that: the conductive layer (7), the tunneling insulating layer (8), the gate electrode (9) and the emitter (10) and the emitter region (3) are isolated by a blocking insulating layer (12); between the conductive layer (7), the tunneling insulating layer (8) and the gate electrode (9) and the collector (11) and the collector region (5) are separated by a blocking insulating layer ( 12) Isolation; adjacent emitter regions (3) and collector regions (5) are isolated from each other by a barrier insulating layer (12); adjacent emitters (10) and collectors (11) are separated by barrier insulation The layers (12) are isolated from each other; adjacent voltage-resistant layers (2) are isolated from each other by the barrier insulating layer (12). 3. The insulated gate tunneling transistor according to claim 1, characterized in that the tunneling insulating layer (8) is an insulating layer for generating an insulated gate tunneling current, and its thickness is less than 1 nanometer. 4. The insulated gate tunneling transistor according to claim 1, characterized in that: the moderately doped base region (4) has the same doping type as the heavily doped base region (6), and has the same doping type as the emitter region (3 ) and the collector region (5) have opposite doping types. 5. The insulated gate tunneling transistor according to claim 1, characterized in that: the bottom of the conductive layer (7) forms an ohmic contact with the heavily doped base region (6), and the conductive layer (7) is made of a metal material or the same The heavily doped base region (6) has the same impurity type and the heavily doped polysilicon with a doping concentration higher than 10 ¹⁹ per cubic centimeter. 6 . The insulated gate tunneling transistor according to claim 1 , characterized in that the gate electrode ( 9 ) is an electrode for controlling the tunneling effect of the tunneling insulating layer ( 8 ), and is an electrode for controlling turning on and off of the device. 7. A method for manufacturing an insulated gate tunneling transistor as claimed in claim 1, characterized in that: the method steps are as follows: Step 1. Provide a bulk silicon wafer substrate (1), form a rectangular parallelepiped single crystal silicon island array region on the provided substrate (1) through photolithography and etching processes, and initially form a withstand voltage layer (2) , and this region is used to further form the withstand voltage layer (2), emitter region (3), moderately doped base region (4), collector region (5) and heavily doped base region (6) of the device; Step 2, planarizing the surface after depositing an insulating medium on the wafer, and preliminarily forming a blocking insulating layer (12); Step 3, forming an emitter region (3) and a collector region (5) on each rectangular parallelepiped single crystal silicon island array through an ion implantation process; Step 4. Through the ion implantation process, the moderately doped base region (4) is initially formed and finally the withstand voltage layer (2), the doping type of the moderately doped base region (4) and the emitter region (3) collector Zone (5) on the contrary, the concentration is lower than 10 ¹⁷ per cubic centimeter; Step 5, forming a heavily doped base region (6) and finally a moderately doped base region (4) through an ion implantation process, the doping concentration of the heavily doped base region (6) being higher than 10 ¹⁸ per cubic centimeter; Step 6. Depositing metal or doping heavily doped polysilicon with the same impurity type as the heavily doped base region on the surface of the wafer, with a concentration higher than 10 ¹⁹ per cubic centimeter, and forming a conductive layer through an etching process (7); Step 7, after depositing an insulating medium on the wafer, planarize the surface and expose the conductive layer (7), and further form a blocking insulating layer (12); Step 8, depositing a tunneling insulating layer dielectric on the wafer, and forming a tunneling insulating layer through an etching process (8); Step 9, after depositing an insulating medium on the wafer, planarizing the surface and exposing the tunneling insulating layer (8), further forming a blocking insulating layer (12); Step 10, depositing metal or heavily doped polysilicon on the wafer, and forming a gate electrode (9) through an etching process; Step eleven, depositing an insulating dielectric layer on the wafer and planarizing the surface, further forming a blocking insulating layer (12); Step 12. Etch through holes for forming emitter (10) and collector (11) above the emitter region (3) and collector region (5) through an etching process, and make the upper surface of the wafer A metal layer is deposited to fill the through hole with metal, and then the metal layer is etched to form an emitter (10) and a collector (11).