CN104465380B - The production method of semiconductor devices - Google Patents

Abstract

A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a gate structure; forming a mask layer covering the semiconductor substrate and the gate structure; and oxidizing the mask layer treatment, so that the partial thickness of the mask layer is converted into an oxide layer; patterning the mask layer and the oxide layer, using the patterned mask layer and the oxide layer as a mask, for the semiconductor substrate located in the lateral region of the gate structure The bottom is etched to form a groove; and a stress layer filling the groove is formed. The manufacturing method of the semiconductor device provided by the present invention improves the selectivity of the stress layer forming process after the mask layer is oxidized, thereby avoiding that the material of the stress layer is formed on the surface of the mask layer when the stress layer is formed , to optimize the electrical performance of semiconductor devices.

Description

Manufacturing method of semiconductor device

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device.

Background technique

With the continuous development of semiconductor technology, carrier mobility enhancement technology has been widely studied and applied. Improving the carrier mobility in the channel region can increase the driving current of MOS devices and improve the performance of the devices.

In the existing manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, it has become more and more common means to improve the performance of semiconductor devices through stress. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS devices, holes in PMOS devices) can be increased, thereby increasing the driving current, thereby greatly improving the performance of semiconductor devices.

At present, embedded silicon germanium (Embedded SiGe) or/and embedded carbon silicon (Embedded SiC) technology is used, that is, silicon germanium material is first formed in the region where the source region and drain region of the PMOS region need to be formed, and then doped to form The source region and the drain region of the PMOS device, in the region of the source region and the drain region of the NMOS region, a carbon silicon material is first formed, and then doped to form the source region and the drain region of the NMOS device; the silicon germanium material is formed to introduce Compressive stress created by lattice mismatch between silicon and silicon germanium (SiGe) to enhance the performance of PMOS devices. The silicon carbon material is formed to introduce tensile stress formed by lattice mismatch between silicon and silicon carbon (SiC), so as to improve the performance of the NMOS device.

The application of embedded silicon germanium and embedded silicon carbon technologies can improve the carrier mobility of semiconductor devices to a certain extent, but in practical applications, it is found that there are still problems to be solved in the manufacturing process of semiconductor devices.

Contents of the invention

The problem solved by the present invention is to provide an optimized semiconductor device manufacturing method, improve the selectivity of the stress layer forming process, avoid the stress layer material from growing in the undesired region during the stress layer formation process, and improve the semiconductor device. electrical properties.

In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the surface of which has a gate structure; forming a mask layer covering the semiconductor substrate and the gate structure; Oxidizing the mask layer so that part of the mask layer is converted into an oxide layer; patterning the mask layer and the oxide layer, using the patterned mask layer and the oxide layer as a mask, Etching the semiconductor substrate in the lateral region of the pole structure to form a groove; forming a stress layer filling the groove.

Optionally, the oxidation treatment process is plasma radical oxidation.

Optionally, the reaction gas for the plasma radical oxidation is O ₂ .

Optionally, the specific process of the plasma radical oxidation is as follows: the plasma power is 300 watts to 2500 watts, the reaction chamber pressure is 0.1 Torr to 20 Torr, and the O ₂ flow rate is 10 sccm to 10000 sccm.

Optionally, the oxide layer has a thickness of 5 angstroms to 100 angstroms.

Optionally, the mask layer has a thickness of 50 angstroms to 200 angstroms.

Optionally, the material of the mask layer is silicon nitride.

Optionally, the formation process of the mask layer is chemical vapor deposition.

Optionally, the specific process parameters of the chemical vapor deposition are: feed NH ₃ and silicon source gas into the reaction chamber, the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , wherein the NH ₃ flow rate is 5 sccm to 1000 sccm , the silicon source gas flow rate is 5 sccm to 500 sccm, the temperature of the reaction chamber is 300 degrees to 800 degrees, and the pressure of the reaction chamber is 0.05 Torr to 50 Torr.

Optionally, the material of the oxide layer is silicon oxynitride.

Optionally, the stress layer is formed using a selective epitaxy process.

Optionally, the material of the stress layer is SiC, SiCP, SiGe or SiGeB.

Optionally, when the material of the stress layer is SiGe, the specific process parameters of the selective epitaxy process are: feeding silicon source gas, germanium source gas, HCl and _H2 into the reaction chamber, the silicon source gas SiH ₄ or SiH ₂ Cl ₂ , the germanium source gas is GeH ₄ , wherein the silicon source gas flow rate is 1 sccm to 1000 sccm, the germanium source gas flow rate is 1 sccm to 1000 sccm, the HCl flow rate is 1 sccm to 1000 sccm, and the _H2 flow rate is 100 sccm to 1000 sccm 50000 sccm, the pressure of the reaction chamber is 1 torr to 500 torr, and the temperature of the reaction chamber is 450 to 850 degrees.

Optionally, when the material of the stress layer is SiC, the specific process parameters of the selective epitaxy process are: feeding silicon source gas, carbon source gas, HCl and _H2 into the reaction chamber, the germanium source gas SiH ₄ or SiH ₂ Cl ₂ , the carbon source gas is CH ₄ , CH ₂ Cl ₂ , CH ₃ Cl, wherein, the germanium source gas flow rate is 1 sccm to 1000 sccm, the carbon source gas flow rate is 1 sccm to 1000 sccm, and the HCl flow rate is 1 sccm to 1000 sccm, H ₂ flow rate of 100 sccm to 50000 sccm, reaction chamber pressure of 1 torr to 500 torr, reaction chamber temperature of 450 to 850 degrees.

Optionally, when the material of the stress layer is SiC, the atomic percentage of C in the material of the stress layer is 1% to 10%.

Optionally, when the material of the stress layer is SiGe, the atomic percentage of Ge in the material of the stress layer is 10% to 55%.

Optionally, the formed semiconductor device is an NMOS transistor, a PMOS transistor or a CMOS transistor.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In this embodiment, after the mask layer is formed, the mask layer is oxidized so that a part of the mask layer is converted into an oxide layer. The material of the mask layer has a lot of floating Si bonds. After the mask layer is oxidized to form an oxide layer, the floating Si bonds are oxidized to form Si-O bonds, so the floating Si bonds in the oxide layer material There are fewer floating Si bonds than in the mask layer material; the reduction of the floating Si bonds is conducive to improving the selectivity of the subsequent stress layer forming process, thereby avoiding the growth of stress layer materials in undesired regions, for example, in this embodiment , the material of the stress layer does not grow on the surface of the oxide layer, so the difficulty of subsequent removal of the oxide layer and mask layer is low, and the mask layer and oxide layer can be completely removed, so that the top of the gate structure has a clean surface. When the metal silicide is formed on the surface of the pole structure, the metal silicide is in close contact with the gate structure, which is beneficial to reduce the contact resistance of the semiconductor device, improve the operating speed of the semiconductor device, and further optimize the electrical performance of the semiconductor device.

At the same time, due to the good selectivity of the process of forming the stress layer, the stress layer material does not grow on the surface of the oxide layer above the groove. Therefore, during the formation of the stress layer, the process window for forming the stress layer remains unchanged, which is conducive to the formation of high-quality The stress layer increases the carrier mobility of the semiconductor device and improves the driving current of the semiconductor device.

Further, in this embodiment, an optimized process is used to oxidize the mask layer, the oxidation process is plasma radical oxidation, the oxidation rate of the plasma radical oxidation process is fast, and the material of the mask layer The content of floating Si bonds in the oxide layer is more oxidized, and the content of floating Si bonds in the formed oxide layer material is less, which is more conducive to improving the selectivity of forming the stress layer and improving the electrical performance of semiconductor devices.

Description of drawings

Fig. 1 is a schematic flow chart of forming a semiconductor device according to an embodiment;

2 to 9 are schematic cross-sectional structure diagrams of the formation process of a semiconductor device according to another embodiment of the present invention.

Detailed ways

It can be seen from the background art that there are still problems to be solved in the formation process of semiconductor devices in the prior art.

According to research on the formation process of semiconductor devices, it is found that the formation process of semiconductor devices includes the following steps, please refer to Figure 1: step S1, providing a semiconductor substrate, the semiconductor substrate includes a first region and a second region; step S2, in A first gate structure is formed on the surface of the semiconductor substrate in the first region, a second gate structure is formed on the surface of the semiconductor substrate in the second region, and both sides of the first gate structure and the second gate structure have Offset sidewalls; step S3, forming a first mask layer covering the semiconductor substrate, the first gate structure and the second gate structure; step S4, patterning the first mask layer to form the patterned first mask layer A mask layer is a mask, etching the semiconductor substrate located in the lateral region of the first gate structure to form a first groove; step S5, using a selective epitaxy process to form a first stressor that fills the first groove layer; step S6, removing the first mask layer; step S7, forming a second stress layer in the semiconductor substrate in the lateral region of the second gate structure, the second stress layer and the first stress layer The type is opposite, and the formation process of the second stress layer is similar to that of the first stress layer.

For the semiconductor device formed by the above process steps, the process of removing the first mask layer is very difficult, and after the process of removing the first mask layer is completed, there will still be There are residual substances that are difficult to remove and affect the electrical performance of the semiconductor device. In particular, a salicide will be formed on the top of the first gate structure and the top of the second gate structure. If the top of the first gate structure and the second gate structure The presence of residual substances on the top of the double gate structure will affect the formation of salicide, and also form salicide in undesired areas.

Further research on the formation process of semiconductor devices found that the reason for the above problems is that the formation process of the first stress layer is selective epitaxy. In order to better complete the growth of the first stress layer, the first mask layer It must have a high selectivity ratio with the semiconductor substrate, and the selectivity of the process of forming the first stress layer is good; and before or after the formation of the first groove, the first groove will be cleaned with a hydrofluoric acid solution, so , the first mask layer must also have a strong ability to resist hydrofluoric acid solution etching.

Theoretically, silicon nitride or silicon oxide can be used as the material of the first mask layer; there are usually two methods for forming silicon oxide materials, one is the thermal oxidation method, and the silicon oxide material formed by the thermal oxidation method has a higher density than the silicon nitride material. Higher selectivity, however, the thermal oxidation method requires pure silicon material as the target material, and in the formation process of semiconductor devices, after the offset sidewall is formed, pure silicon material cannot be provided as the target material, so thermal oxidation cannot be used The oxidation method forms the first mask layer; the second is the chemical vapor deposition process to form the silicon oxide material, but the silicon oxide material formed by the chemical vapor deposition process has a low selectivity ratio and is easily etched by the hydrofluoric acid solution. Therefore, the chemical vapor deposition process The formed silicon oxide material is not suitable as the material of the first mask layer. Since the silicon nitride material has high selectivity and is not easy to be etched by the hydrofluoric acid solution, a silicon nitride film is usually used as the first mask layer.

However, although the selective epitaxial process for forming the first stress layer has high selectivity between the silicon nitride film and the semiconductor substrate when the silicon nitride film is used as the first mask layer, since the silicon nitride film There are still more floating Si bonds in the film, and the material of the first stress layer contains more Si bonds, so the existence of the floating Si bonds leads to the formation of the first stress layer by using the selective epitaxy process. The first stress layer material will also grow on the surface of the first mask layer; after the first stress layer forming process is completed, there will be a first stress layer material on the surface of the first mask layer, and even if the content of the first stress layer material is relatively high Small, it will still lead to the difficulty of the subsequent removal of the first mask layer, and the first mask layer is difficult to remove; when the salicide is subsequently formed, the salicide will be formed on the entire surface of the mask layer , leading to the formation of salicides in undesired regions, reducing the reliability of semiconductor devices.

At the same time, because the material of the first stress layer is also formed on the surface of the first mask layer above the groove, the process window for filling the first groove is reduced, and the reduction of the process window leads to the formation of The difficulty of high-quality first stress layer increases, and the quality of the formed first stress layer deteriorates.

For this reason, the present invention provides a kind of manufacturing method of optimized semiconductor device, after forming mask layer, described mask layer is carried out oxidation treatment, and the mask layer of partial thickness is converted into oxide layer, improves subsequent forming stress layer. The selectivity of the process prevents the growth of the stress layer in the undesired area and improves the electrical performance of the semiconductor device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

2 to 9 are schematic cross-sectional structural views of the formation process of the semiconductor device provided by the embodiment of the present invention.

Referring to FIG. 2 , a semiconductor substrate 200 is provided, and the surface of the semiconductor substrate 200 has a gate structure.

It should be noted that the semiconductor substrate 200 includes one or both of an NMOS region or a PMOS region.

When the semiconductor substrate 200 only includes the NMOS region I, the formed transistor is an NMOS transistor; when the semiconductor substrate 200 only includes the PMOS region II, the formed transistor is a PMOS transistor; the semiconductor substrate 200 includes the NMOS region I and PMOS region II, the formed transistor is a CMOS transistor.

In this embodiment, the semiconductor substrate 200 includes the NMOS region I and the PMOS region II, and the semiconductor device formed is a CMOS transistor for exemplary illustration, and the positions of the NMOS region I and the PMOS region II can be interchanged.

In this embodiment, the gate structure includes a first gate structure 210 located on the surface of the semiconductor substrate 200 in the NMOS region I and a second gate structure 220 located on the surface of the semiconductor substrate 200 in the PMOS region II.

In other embodiments of the present invention, if the semiconductor substrate only includes one of the NMOS region or the PMOS region, the gate structure only includes the gate structure on the surface of the semiconductor substrate in the NMOS region or the gate structure on the surface of the semiconductor substrate in the PMOS region. grid structure.

The semiconductor substrate 200 is one of monocrystalline silicon, polycrystalline silicon, amorphous silicon or silicon-on-insulator; the semiconductor substrate 200 can also be a Si substrate, a Ge substrate, a SiGe substrate or a GaAs substrate .

Several epitaxial interface layers or strain layers can also be formed on the surface of the semiconductor substrate 200 to improve the electrical performance of the semiconductor device.

In this embodiment, the semiconductor substrate 200 is a Si substrate.

In this embodiment, the semiconductor substrate 200 further has an isolation structure 201 to prevent the electrical connection between the NMOS region I and the PMOS region II. The filling material of the isolation structure 201 may be one or more of silicon oxide, silicon nitride or silicon oxynitride.

In order to meet the development trend of continuous miniaturization of semiconductor devices, there may be one first gate structure or multiple first gate structures on the surface of the semiconductor substrate in the NMOS region I, and the materials of the multiple first gate structures and The structures can be the same or different; the surface of the PMOS region II semiconductor substrate can have a second gate structure or multiple second gate structures, and the materials and structures of multiple second gate structures can be the same or can be different.

In this embodiment, one first gate structure 210 is formed on the surface of the semiconductor substrate 200 in the NMOS region I, two second gate structures 220 are formed on the surface of the semiconductor substrate 200 in the PMOS region II, and the two second gate structures 220 The materials and structures are the same, and one of the sidewalls of the second gate structure 220 is close to the isolation structure 201 for exemplary illustration. In other embodiments of the present invention, the first gate structure 210 or the second gate structure 220 may be partially located on the surface of the isolation structure 201 or away from the isolation structure 201, and the first gate structure 210 or the second gate structure should not be restricted too much. The positional relationship between the pole structure 220 and the isolation structure 201 .

The first gate structure 210 includes a first gate oxide layer 211 on the surface of the semiconductor substrate 200 , and a first gate electrode layer 212 on the surface of the first gate oxide layer 211 .

The second gate structure 220 includes a second gate oxide layer 221 on the surface of the semiconductor substrate 200 , and a second gate electrode layer 222 on the surface of the second gate oxide layer 221 .

The material of the first gate oxide layer 211 or the second gate oxide layer 221 is silicon oxide or a high-k dielectric material, and the material of the first gate electrode layer 212 or the second gate electrode layer 222 is polysilicon, doped polysilicon or metal.

Referring to FIG. 3 , offset spacers 202 are formed on the surface of the semiconductor substrate 200 , and the offset spacers 202 are located on both sides of the first gate structure 210 or the second gate structure 220 .

The offset spacer 202 protects both sides of the first gate structure 210 or the second gate structure 220 from being damaged by the subsequent process; in order to prevent the short channel effect of the semiconductor device, the semiconductor substrate 200 on both sides of the gate structure A pocket area is formed inside, and the offset sidewall 202 is a mask for forming the pocket area.

The material of the offset sidewall 202 is silicon oxynitride or silicon nitride, and the offset sidewall 202 can be a single-layer structure or a multi-layer structure.

In this embodiment, the offset sidewall 202 is a single-layer structure of silicon nitride.

Before forming the offset spacer 202, lightly doped ion implantation can also be performed on the semiconductor substrate 200 on both sides of the first gate structure 210 or the second gate structure 220 to form a lightly doped region (LDD ), to prevent the hot carrier effect in semiconductor devices.

After the offset spacer 202 is formed, ion implantation can also be performed on the semiconductor substrate 200 on both sides of the first gate structure 210 or the second gate structure 220 to form a pocket region, and the pocket region and the light The types of doped regions are reversed to prevent short channel effects in semiconductor devices.

It should be noted that the formation of the offset sidewall 202 is optional but not necessary.

Referring to FIG. 4 , a mask layer 203 covering the semiconductor substrate 200 and the gate structure is formed.

Specifically, in this embodiment, the mask layer 203 covers the semiconductor substrate 200 , the offset spacer 202 , the first gate structure 210 and the second gate structure 220 .

The function of the mask layer 203 is to serve as a mask for subsequent etching of the semiconductor substrate 200 to form a groove, and to protect the first gate structure 210 of the NMOS region I from being damaged by the formation process of the groove.

The mask layer 203 is used as a mask for the subsequent groove formation process, and the material of the mask layer 203 must meet the following two conditions: first, when the stress layer is formed by the subsequent selective epitaxy process, the stress layer only fills the groove , therefore, there must be a high selectivity between the mask layer 203 and the material of the semiconductor substrate 200; secondly, there is a hydrofluoric acid solution in the subsequent groove formation and groove cleaning process, therefore, the mask layer 203 The material must have a high ability to resist etching by hydrofluoric acid solution.

When the material of the mask layer 203 is silicon oxide grown by thermal oxidation, the stress layer formation process has the best selectivity for the mask layer 203, but the conditions for forming silicon oxide by thermal oxidation growth process are harsh, and the growth temperature is above 1000 degrees. , and pure silicon must be provided as a target, but in this embodiment, since the material of the offset spacer 202 is silicon nitride, it is impossible to provide pure silicon as a target on the surface of the first gate structure 210 and the second gate structure 220 material, even if pure silicon can be provided as the target material, the thermal oxidation process is carried out at a high temperature above 1000 degrees, and the high temperature will destroy the formed gate structure; therefore, in this embodiment, silicon oxide grown by thermal oxidation cannot be used as the target material. The material of the mask layer 203 . However, when the material of the mask layer 203 is silicon nitride, the above requirements on the properties of the material of the mask layer 203 are basically met.

In this embodiment, the material of the mask layer 203 is silicon nitride, and the thickness of the mask layer 203 is 50 angstroms to 200 angstroms.

The formation process of the mask layer 203 is chemical vapor deposition.

As an example, the specific process parameters of the chemical vapor deposition are: feed NH ₃ and silicon source gas into the reaction chamber, the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , wherein the flow rate of NH ₃ is 5 sccm to 1000 sccm, the flow rate of the silicon source gas is 5 sccm to 500 sccm, the temperature of the reaction chamber is 300 degrees to 800 degrees, and the pressure of the reaction chamber is 0.05 Torr to 50 Torr.

Although silicon nitride is used as the material of the mask layer 203, it can basically meet the requirements of good selectivity and strong corrosion resistance, but since the material of the mask layer 203 is silicon nitride, the Si-N bond has a negative effect on Si The binding ability of atoms is limited, resulting in more floating Si bonds in the material of the mask layer 203. When the stress layer is formed by the selective epitaxy process, the stress layer material will also grow on the surface of the mask layer 203; the mask layer 203 will be removed later. The film layer 203 forms a metal silicide on the top of the first gate structure 210 or the top of the second gate structure 220. If there is a stress layer material on the surface of the mask layer 203, the mask layer 203 cannot be removed later. When the metal silicide is formed on the top of the structure 210 or the top of the second gate structure 220, the metal silicide is also formed on the sidewall of the first gate structure 210 or the second gate structure 220, which affects the electrical performance of the semiconductor device; A stress layer material is formed on the surface of the mask layer 203 of the groove, which causes the process window for filling the groove to gradually become smaller. The reduction of the process window is not conducive to the formation of a high-quality stress layer, and the difficulty of filling the groove increases, which affects the semiconductor device. Enhancement of flow rate.

Therefore, in the embodiment of the present invention, the mask layer 203 is oxidized to form an oxide layer, and the selectivity ratio between the oxide layer and the semiconductor substrate 200 is increased during the formation of the stress layer, so as to avoid the occurrence of the above undesirable phenomena.

Referring to FIG. 5 , an oxidation treatment 230 is performed on the mask layer 203 so that a part of the mask layer 203 is transformed into an oxide layer 204 .

The oxidation treatment 230 oxidizes the floating Si bonds in the material of the mask layer 203 to form Si-O bonds, and the Si-O bonds bind the floating Si bonds in the material of the mask layer 203. Therefore, compared with the mask layer 203, there are fewer floating Si bonds in the material of the oxide layer 204, and there is better selectivity between the material of the oxide layer 204 and the material of the semiconductor substrate 200. Therefore, during the subsequent formation of the stress layer, the stress layer Material will not form on the surface of the oxide layer 204 .

In this embodiment, the process of the oxidation treatment 230 is plasma radical oxidation, that is, the reactive gas is introduced into the reaction chamber, and the reactive gas forms oxygen free radicals after plasma treatment, and the oxygen free radicals affect the mask layer 203 Oxidation treatment 230 is performed. Oxygen radicals are very active in the plasma radical oxidation process, and it is easier to oxidize the material in the mask layer 203, so the plasma radical oxidation process has a higher oxidation rate, and the Si bonds floating in the material of the mask layer 203 are The content of oxidation is large, so that the content of floating Si bonds in the formed oxide layer 204 material is very small, which is conducive to the formation of an oxide layer 204 with less floating Si bond content, and the less floating Si bonds in the oxide layer 204 material, the oxide layer 204 The greater the structural difference between the material and the semiconductor substrate 200 material, the better the selectivity when forming the stress layer subsequently.

As an example, the reaction gas of the plasma radical oxidation is O ₂ , and the specific process of the plasma radical oxidation is as follows: the plasma power is 300 watts to 2500 watts, and the reaction chamber pressure is 0.1 Torr to 20 Torr, the flow of O ₂ into the reaction chamber is 10sccm to 10000sccm.

If the thickness of the oxide layer 204 is too small, the floating Si bonds in the material of the mask layer 203 will still diffuse to the surface of the oxide layer 204, resulting in a limited degree of selectivity improvement when forming a stress layer in the future; if the thickness of the oxide layer 204 is too large, This will increase the difficulty of the oxidation treatment 230 process.

In this embodiment, the material of the oxide layer 204 is silicon oxynitride, and the thickness of the oxide layer 204 is 5 angstroms to 100 angstroms.

Referring to FIG. 6, the mask layer 203 and the oxide layer 204 are patterned to form an opening 205 in the mask layer 203 and the oxide layer 204, the opening 205 is located in the lateral area of the second gate structure 220 in the PMOS region II, And the position and width of the opening 205 correspond to the position and width of the subsequently formed groove.

As an example, the forming process of the opening 205 is: forming a photoresist layer covering the oxide layer 204, the photoresist layer has a pattern corresponding to the opening 205, and using the photoresist layer as a mask film, etch the oxide layer 204 and the mask layer 203, and form an opening 205 in the oxide layer 204 and the mask layer 203, and the opening 205 is located in the lateral area of the second gate structure 220 in the PMOS region II.

In other embodiments of the present invention, if the second gate structure is far away from the isolation structure, openings are formed in both the oxide layer and the mask layer on both sides of the second gate structure, and subsequently the semiconductor substrates on both sides of the second gate structure are Grooves are formed in the bottom.

It should be noted that the position of the opening 205 is determined according to the position where the stress layer needs to be formed, and the position and width of the opening 205 should not be restricted too much.

Referring to FIG. 7 , using the patterned oxide layer 204 and mask layer 203 as a mask, the semiconductor substrate 200 in the lateral region of the gate structure is etched to form a groove 206 .

Specifically, using the patterned oxide layer 204 and the mask layer 203 as a mask, etch the semiconductor substrate 200 in the lateral region of the second gate structure 220 along the opening 205 (please refer to FIG. 6 ) to form a groove 206.

The shape of the groove 206 is U-shape, square or sigma (Σ) shape.

As an embodiment, the shape of the groove 206 is Σ-shape.

The sidewall of the Σ-shaped groove is concave toward the direction of the device channel. This shape can effectively shorten the length of the device channel and meet the requirements of device size miniaturization; and the Σ-shaped groove has a large undercut under the gate spacer. The characteristics of the stress material formed in the groove of this shape can generate greater stress on the channel region of the device.

The forming process of the groove 206 may be dry etching, wet etching or an etching process combining dry etching and wet etching.

As an example, the formation process of the Σ-shaped groove 206 is used as an exemplary illustration: first, the oxide layer 204 and the mask layer 203 are used as a mask, and the semiconductor is etched along the opening 205 by using a dry etching process. On the substrate 200 , an inverted trapezoidal pre-groove is formed, and then the pre-groove is continuously etched by using a wet etching process to form a Σ-shaped groove 206 .

Referring to FIG. 8 , a stress layer 207 filling the groove 206 (please refer to FIG. 7 ) is formed.

The top of the stress layer 207 is level with or higher than the surface of the semiconductor substrate 200 . In this embodiment, the top of the stress layer 207 is flush with the surface of the semiconductor substrate 200 for exemplary illustration.

The stress layer 207 is made of SiC, SiCP, SiGe or SiGeB.

In this embodiment, the stress layer 207 provides stress for the channel region of the PMOS region II to improve carrier mobility in the PMOS region, and the material of the stress layer 207 is a compressive stress material. Specifically, the material of the stress layer 207 is SiGe or SiGeB, and the atomic percentage of Ge in the material of the stress layer 207 is 10% to 55%.

The stress layer 207 is formed by a selective epitaxy process. As an example, when the material of the stress layer 207 is SiGe, the specific process parameters of the selective epitaxy process are: feeding silicon source gas, germanium source gas, HCl and _H2 into the reaction chamber, the silicon The source gas is SiH ₄ or SiH ₂ Cl ₂ , the germanium source gas is GeH ₄ , wherein the silicon source gas flow rate is 1 sccm to 1000 sccm, the germanium source gas flow rate is 1 sccm to 1000 sccm, the HCl flow rate is 1 sccm to 1000 sccm, and the H ₂ flow rate is 100 sccm to 50000 sccm, the pressure of the reaction chamber is 1 torr to 500 torr, and the temperature of the reaction chamber is 450 to 850 degrees.

In other embodiments of the present invention, the stress layer provides stress for the channel region of the NMOS region I to improve carrier mobility in the NMOS region I, and the material of the stress layer is a tensile stress material. Specifically, the material of the stress layer is SiC or SiCP, and the atomic percentage of C in the material of the stress layer is 1% to 10%.

As an example, when the material of the stress layer is SiC, the specific process parameters of the selective epitaxy process are: feeding silicon source gas, carbon source gas, HCl and _H2 into the reaction chamber, the germanium source The gas is SiH ₄ or SiH ₂ Cl ₂ , the carbon source gas is CH ₄ , CH ₂ Cl ₂ , CH ₃ Cl, wherein the germanium source gas flow rate is 1 sccm to 1000 sccm, the carbon source gas flow rate is 1 sccm to 1000 sccm, and the HCl flow rate is 1sccm to 1000sccm, the _H2 flow rate is 100sccm to 50000sccm, the reaction chamber pressure is 1 Torr to 500 Torr, and the reaction chamber temperature is 450 degrees to 850 degrees.

In the embodiment of the present invention, the material of the stress layer 207 is SiGe or SiGeB, there are few floating Si bonds in the oxide layer 204 , and the material structures of the oxide layer 204 and the stress layer 207 are quite different. Since the characteristics of the selective epitaxial process are: if the structure of the epitaxial layer material is the same or similar to that of the substrate material, the epitaxial layer material is grown on the surface of the substrate; Slower, the greater the structure difference between the epitaxial layer material and the substrate material, the slower the growth rate of the epitaxial layer material on the substrate surface. Since in this embodiment, the material structures of the oxide layer 204 and the stress layer 207 are quite different, the material of the stress layer 207 will not be formed on the surface of the oxide layer 204 during the process of forming the stress layer 207 .

At the same time, since the material of the stress layer 207 will not be formed on the surface of the oxide layer 204 above the groove 206, the process window for forming the stress layer 207 remains unchanged as the process time increases, which is conducive to the formation of a dense stress layer. 207, which is beneficial to improving the carrier mobility of the semiconductor device, thereby increasing the driving current of the semiconductor device. However, in the prior art, during the formation of the stress layer, the material of the stress layer is also formed on the surface of the mask layer. As the process time increases, the process window for forming the stress layer decreases, resulting in poor quality of the formed stress layer. , Poor density, affecting the electrical properties of semiconductor devices.

It should be noted that, before the stress layer 207 is formed, a step may also be included: cleaning the groove 206 to remove the residues of the groove 206 formed by etching, and the cleaning may be performed by using a hydrofluoric acid solution.

Referring to FIG. 9 , the mask layer 203 (please refer to FIG. 8 ) and the oxide layer 204 (please refer to FIG. 8 ) are removed.

As an embodiment, a wet etching process is used to remove the mask layer 203 and the oxide layer 204 .

The etching liquid used in the wet etching process is hydrofluoric acid solution and hot phosphoric acid solution. Specifically, the oxide layer 204 is removed with a hydrofluoric acid solution, and the mask layer 203 is removed with a hot phosphoric acid solution.

In other embodiments of the present invention, the mask layer 203 and the oxide layer 204 located on the top of the first gate structure 210, the top of the second gate structure 220 and the surface of the semiconductor substrate 200 are removed, and the The mask layer 203 and the oxide layer 204, the remaining mask layer 203 and the oxide layer 204 can be used as the main sidewall of the semiconductor device, and when the heavily doped region of the semiconductor device is subsequently formed, the main sidewall is used to form a heavily doped The mask of the heterogeneous area.

It should be noted that, after the stress layer 207 in the PMOS region II is formed, a tensile stress layer may also be formed in the semiconductor substrate in the region next to the first gate structure 210 in the NMOS region I. For the formation process of the tensile stress layer, refer to the formation process of the stress layer 205 in this embodiment; in the process of forming the tensile stress layer, it is also necessary to form the covering semiconductor substrate 200, the first gate structure 210 and the second gate structure 220 The NMOS mask layer of the NMOS mask layer is subjected to an oxidation treatment similar to the oxidation treatment 230 provided in this embodiment.

Since no difficult-to-remove stress layer material, such as SiGe, SiGeB, SiC or SiCP, is formed on the surface of the oxide layer 204, the process difficulty of removing the mask layer 203 and the oxide layer 204 is low, and they are located on the top of the first gate structure 210. The oxide layer 204 and the mask layer 203 on top of the second gate structure 220 may be completely removed. When the metal silicide is subsequently formed on the top of the first gate structure 210 and the top of the second gate structure 220, the metal silicide is in close contact with the top of the first gate structure 210 or the top of the second gate structure 220, and avoids metal The silicide is formed in the undesired area, which is beneficial to reduce the contact resistance of the semiconductor device, increase the operating speed of the semiconductor device, and improve the electrical performance of the semiconductor device.

In summary, the technical solution provided by the present invention has the following advantages:

First, in the embodiment of the present invention, the mask layer is oxidized to oxidize the floating Si bonds in the mask layer material, so that a part of the thickness of the mask layer is converted into an oxide layer, and the floating Si bonds in the formed oxide layer material The Si bond content is less than that of the floating Si bond in the mask layer material; when the stress layer is subsequently formed, the selectivity between the semiconductor substrate material and the oxide layer material is better than the selectivity between the semiconductor substrate material and the mask layer material, avoiding the The material of the stress layer is grown in the undesired area, which improves the quality of the subsequent formation of metal silicide on the top of the gate structure, avoids the formation of metal silicide in the undesired area, and improves the electrical performance of the semiconductor device.

Secondly, the less the content of floating Si bonds in the oxide layer, the greater the structural difference between the oxide layer material and the semiconductor substrate material, and the better the selectivity for forming the stress layer; in this embodiment, the optimized oxidation treatment process is adopted, and the The oxidation treatment process is plasma radical oxidation, so that the content of oxidized floating Si bonds in the mask layer material is large, and there are almost no floating Si bonds in the formed oxide layer material, which is more conducive to improving the selection of subsequent stress layer formation processes and improve the electrical performance of semiconductor devices.

Again, in this embodiment, since the stress layer material does not grow on the surface of the oxide layer above the groove, during the stress layer formation process, the window of the stress layer formation process remains unchanged, which has no effect on the process difficulty of forming the stress layer. It can form a stress layer with good density, thereby improving the carrier mobility of semiconductor devices and improving the electrical properties of semiconductor devices.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (17)

1. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a gate structure; forming a mask layer covering the semiconductor substrate and the gate structure; performing oxidation treatment on the mask layer, so that part of the thickness of the mask layer is converted into an oxide layer; Patterning the mask layer and oxide layer, the patterned mask layer and oxide layer are located on the top and side walls of the gate structure, using the patterned mask layer and oxide layer as a mask, and opposite to the gate structure Etching the semiconductor substrate in the lateral region of the pole structure to form grooves; A stress layer is formed filling the groove. 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein the oxidation treatment process is plasma radical oxidation. 3 . 3 . The method for manufacturing a semiconductor device according to claim 2 , wherein the reaction gas for the plasma radical oxidation is O ₂ . 4. The manufacturing method of a semiconductor device according to claim 3, wherein the specific process of the plasma radical oxidation is as follows: the plasma power is 300 watts to 2500 watts, and the reaction chamber pressure is 0.1 Torr to 20 Torr, _O2 flow from 10sccm to 10000sccm. 5 . The method for fabricating a semiconductor device according to claim 1 , wherein the oxide layer has a thickness of 5 angstroms to 100 angstroms. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the mask layer has a thickness of 50 angstroms to 200 angstroms. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the material of the mask layer is silicon nitride. 8 . The method for manufacturing a semiconductor device according to claim 7 , wherein the mask layer is formed by chemical vapor deposition. 9. The manufacturing method of a semiconductor device according to claim 8, characterized in that, the specific process parameters of the chemical vapor deposition are: in the reaction chamber, feed NH ₃ and silicon source gas, and the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , wherein the NH ₃ flow rate is 5 sccm to 1000 sccm, the silicon source gas flow rate is 5 sccm to 500 sccm, the reaction chamber temperature is 300°C to 800°C, and the reaction chamber pressure is 0.05 Torr to 50 Torr. 10 . The method for manufacturing a semiconductor device according to claim 1 , wherein the material of the oxide layer is silicon oxynitride. 11 . 11. The method for manufacturing a semiconductor device according to claim 1, wherein the stress layer is formed by a selective epitaxy process. 12 . The method for manufacturing a semiconductor device according to claim 11 , wherein the material of the stress layer is SiC, SiCP, SiGe or SiGeB. 13. The manufacturing method of a semiconductor device according to claim 12, wherein, when the material of the stress layer is SiGe, the specific process parameters of the selective epitaxy process are: a silicon source gas is introduced into the reaction chamber , germanium source gas, HCl and H ₂ , the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , the germanium source gas is GeH ₄ , wherein the flow rate of the silicon source gas is from 1 sccm to 1000 sccm, and the flow rate of the germanium source gas is from 1 sccm to 1000sccm, the flow rate of HCl is 1sccm to 1000sccm, the flow rate of _H2 is 100sccm to 50000sccm, the pressure of the reaction chamber is 1 torr to 500 torr, and the temperature of the reaction chamber is 450 degrees to 850 degrees. 14. The manufacturing method of a semiconductor device according to claim 12, wherein when the material of the stress layer is SiC, the specific process parameters of the selective epitaxy process are: a silicon source gas is introduced into the reaction chamber , carbon source gas, HCl and H ₂ , the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , the carbon source gas is CH ₄ , CH ₂ Cl ₂ , CH ₃ Cl, wherein the flow rate of the silicon source gas is 1 sccm to 1000sccm, the flow rate of carbon source gas is 1sccm to 1000sccm, the flow rate of HCl is 1sccm to 1000sccm, the flow rate of _H2 is 100sccm to 50000sccm, the pressure of the reaction chamber is 1 torr to 500sccm, and the temperature of the reaction chamber is 450 degrees to 850 degrees. 15. The manufacturing method of a semiconductor device according to claim 12, wherein when the material of the stress layer is SiC, the atomic percentage of C in the material of the stress layer is 1% to 10%. 16. The manufacturing method of a semiconductor device according to claim 12, wherein when the material of the stress layer is SiGe, the atomic percentage of Ge in the material of the stress layer is 10% to 55%. 17. The method for manufacturing a semiconductor device according to claim 1, wherein the formed semiconductor device is an NMOS transistor, a PMOS transistor or a CMOS transistor.