CN104465381B - A kind of manufacture method of half floating-gate device of planar channeling - Google Patents

Abstract

The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a method for manufacturing a planar channel semi-floating gate device. The invention adopts the gate-last process to prepare the semi-floating gate device of the planar channel. After the source contact region and the drain contact region are formed, the polysilicon control gate sacrificial material is first etched away, and then the metal control gate material is made to occupy the original polysilicon control gate sacrificial material. The position of the material forms the metal control gate, which can prevent the metal control gate from being damaged during the high-temperature annealing process of the source contact region and the drain contact region, and improves the performance of the planar channel semi-floating gate device. At the same time, the present invention also uses a self-alignment process to manufacture the source contact region and the drain contact region of the semi-floating gate device, the process is simple and stable, and the production cost is reduced.

Description

A method of manufacturing a planar channel semi-floating gate device

technical field

The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a method for manufacturing a planar channel semi-floating gate device.

Background technique

A planar channel semi-floating gate device proposed in Chinese patent 201310006320.3, its cross-sectional view is shown in Figure 1, the planar channel semi-floating gate device is formed in a semiconductor substrate 600 with the first doping type A source region 601 and a drain region 602 having the second doping type, and a semiconductor substrate having the first doping type between the source region 601 and the drain region 602 form a channel region of the device. The first doping type is n-type, and the second doping type is p-type, or, the first doping type is p-type, and the second doping type is n-type.

A gate dielectric layer 603 of the device is formed above the source region 601 , the drain region 602 and the channel region, and a floating gate opening region 604 is formed in the gate dielectric layer 603 above the drain region 602 . Covering the gate dielectric layer 603 and the floating gate opening region 604, a floating gate 605 with the first doping type is formed as a charge storage node, and the doping impurities in the floating gate 605 pass through the floating gate opening under the floating gate 605 The region 604 is diffused into the drain region 602 to form a diffusion region 802 , so that the floating gate 605 forms a pn junction contact with the drain region 602 .

A second insulating film 606 is formed covering the floating gate 605 , and a control gate 607 formed covering the second insulating film 606 is longer than the floating gate 605 along the channel direction, covering and surrounding the floating gate 605 . Gate spacers 608 are formed on both sides of the control gate 607 . On both sides of the gate spacer 608 , high-concentration ion-doped regions are formed in the source region 601 and the drain region 602 , serving as the source contact region 609 and the drain contact region 610 respectively. At the same time, the device also includes a source electrode 611, a control gate electrode 612, a drain electrode 613, and a semiconductor substrate formed of conductive materials for connecting the source region 601, the control gate 607, the drain region 602, and the semiconductor substrate 600 to external electrodes. The bottom electrode 614.

Chinese patent 201310006320.3 also proposes a method for manufacturing a semi-floating gate device with a planar channel as shown in 1, which is to prepare a semi-floating gate device with a planar channel through a gate-first process, that is, the control gate is formed first, and then the source, Drain contact area. At present, metal gates and high dielectric constant material gate dielectrics have been widely used in integrated circuits. The use of metal gate materials can not only reduce gate resistance but also eliminate the depletion effect of polysilicon gates. However, the high temperature resistance of the metal gate is poor, and high temperature annealing is required after the source and drain contact regions are formed in the gate-first process, which will cause damage to the previously formed metal gate.

Contents of the invention

In view of this, the object of the present invention is to provide a method for manufacturing a planar channel semi-floating gate device.

The purpose of the present invention is achieved through the following technical solutions:

A method for manufacturing a semi-floating gate device with a planar channel. The semi-floating gate device with a planar channel is prepared by using a gate-last process. After forming a source contact region and a drain contact region, the polysilicon control gate sacrificial material is first etched away, and then the polysilicon control gate sacrificial material is etched away. The metal control gate material occupies the position of the original polysilicon control gate sacrificial material to form the metal control gate.

A method for manufacturing a planar channel semi-floating gate device as described above, comprising the following steps:

Depositing a layer of photoresist on the surface of the semiconductor substrate with the first doping type on which the shallow trench isolation structure has been formed, and forming a pattern through a photolithography process;

Using the photoresist as a mask to form a source region and a drain region with the second doping type on both sides of the photoresist in the semiconductor substrate respectively, located between the source region and the drain region A semiconductor substrate having a first doping type forms a channel region of a device;

Form a first layer of insulating film on the surface of the semiconductor substrate, and etch the first layer of insulating film to form a floating gate opening area, the floating gate opening area is located above the drain region, and it is close to the channel The distance between one edge of the region and the channel region is greater than 1 nanometer;

depositing a layer of polysilicon having a first doping type on the exposed surface of the formed structure;

The position of the floating gate of the device is defined by a photolithography process, and then the polysilicon with the first doping type is etched using the photoresist as a mask, and the remaining polysilicon with the first doping type after etching forms the device A floating gate, the floating gate at least covers the channel region and the floating gate opening region, and a pn is formed between the floating gate and the drain region through the floating gate opening region under the floating gate Junction contact;

Etching away the exposed first layer of insulating film using the floating gate as a mask;

Depositing and forming a second layer of insulating film on the surface of the formed structure;

Depositing a layer of polysilicon sacrificial material on the second layer of insulating film, and depositing a third layer of insulating film on the polysilicon sacrificial material;

The third insulating film and polysilicon sacrificial material are etched by photolithography and etching processes, and the remaining polysilicon sacrificial material after etching forms the polysilicon control gate sacrificial material of the device, and the polysilicon control gate sacrificial material is formed along the channel The length in the direction exceeds the floating gate, and covers and surrounds the floating gate;

Depositing and forming a fourth layer of insulating film covering the formed structure, and etching back the fourth layer of insulating film to form gate spacers on both sides of the polysilicon control gate sacrificial material, and then The exposed second layer of insulating film is etched away by the pole sidewall;

performing source and drain etching on both sides of the gate spacer, and forming a source contact region and a drain contact region by an epitaxial process at the position after the source and drain etching;

Depositing the first layer of interlayer dielectric material covering the formed structure, and then polishing until the sacrificial material of the polysilicon control gate is exposed;

Etching off the exposed polysilicon control gate sacrificial material, and then continuing to etch off the exposed second insulating film;

Depositing a fifth layer of insulating film and metal control gate material on the surface of the formed structure, and then polishing so that the polished metal control gate material occupies the position of the original polysilicon control gate sacrificial material, thereby forming a metal control gate;

A second layer of interlayer dielectric material is deposited covering the formed structure, and then contact holes are formed in the second layer of interlayer dielectric material and the first layer of interlayer dielectric material, and source electrodes, drain electrodes and gate electrodes are formed.

In the method for manufacturing a planar channel semi-floating gate device as described above, after etching away the exposed polysilicon control gate sacrificial material, the second layer of insulating film is reserved, and then the second layer of insulating film is deposited on the second layer of insulating film. Five layers of insulating film and metal control gate material.

In the method for manufacturing a semi-floating gate device with a planar channel as described above, after etching away the exposed polysilicon control gate sacrificial material, the second layer of insulating film is retained, and then directly deposited on the second layer of insulating film Metal control gate material.

In the method for manufacturing a planar channel semi-floating gate device as described above, the first doping type is n-type, and the second doping type is p-type; or, the first doping type The heterotype is p-type, and the second doping type is n-type.

A method for manufacturing a semi-floating gate device with a planar channel as described above, the first insulating film, the second insulating film and the fifth insulating film are respectively silicon dioxide, silicon nitride, silicon oxynitride , an insulating material with a high dielectric constant value or any one of the stacked layers between them, and the gate spacer, the third layer of insulating film and the fourth layer of insulating film are respectively silicon dioxide or nitride any of silicon.

According to the above method for manufacturing a planar channel semi-floating gate device, the semiconductor substrate is any one of single crystal silicon, polycrystalline silicon or silicon on insulator.

According to the method for manufacturing a semi-floating gate device with a planar channel as described above, silicon germanium or silicon carbide is epitaxially epitaxy at the position after the source and drain are etched to form the source contact region and the drain contact region.

In the above-mentioned method for manufacturing a semi-floating gate device with a planar channel, after the gate spacer is formed, source and drain etching and epitaxial processes are not performed, and ion implantation is directly performed on both sides of the gate spacer. A high-concentration doped region is formed in the source region and the drain region to form the source contact region and the drain contact region.

According to the method for manufacturing a planar channel semi-floating gate device as described above, the third layer of insulating film and polysilicon sacrificial material are etched by a photolithography process and an etching process, and the remaining polysilicon sacrificial material after etching forms a device polysilicon control gate sacrificial material, and the length of the polysilicon control gate sacrificial material exceeds the floating gate only on one side of the drain region along the channel direction.

A method for manufacturing a semi-floating gate device with a planar channel of the present invention uses a gate-last process to prepare a semi-floating gate device with a planar channel. After the source contact region and the drain contact region are formed, the sacrificial polysilicon control gate is etched away first. material, and then make the metal control gate material occupy the position of the original polysilicon control gate sacrificial material to form a metal control gate, which can prevent the metal control gate from being damaged during the high-temperature annealing process of the source contact region and the drain contact region, and improve the planar channel The performance of the semi-floating gate device. At the same time, the present invention also utilizes the self-alignment process to manufacture the source contact region and the drain contact region of the semi-floating gate device, the process is simple and stable, and the production cost is reduced.

Description of drawings

Figure 1 is a cross-sectional view of a planar channel semi-floating gate device in Chinese patent 201310006320.3;

2 to 11 are process flow charts of an embodiment of a planar channel semi-floating gate device manufactured by a method for manufacturing a planar channel semi-floating gate device of the present invention;

12 is a cross-sectional view of an embodiment of a planar channel semi-floating gate device structure of a double memory cell manufactured by the method for manufacturing a planar channel semi-floating gate device of the present invention;

13 is a schematic circuit diagram of a memory cell array composed of a plurality of planar channel semi-floating gate devices manufactured by the method for manufacturing a planar channel semi-floating gate device of the present invention.

detailed description

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. In the drawings, the thicknesses of layers and regions are exaggerated for convenience of illustration, and the shown sizes do not represent actual sizes. The referenced figures are schematic illustrations of idealized embodiments of the invention, and the illustrated embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated in the figures but are to include resulting shapes, such as manufacturing-induced deviations. For example, the curves obtained by etching are usually curved or rounded, but in the embodiment of the present invention, they are all represented by rectangles. The representation in the figure is schematic, but this should not be considered as limiting the scope of the present invention. Meanwhile, in the following description, the term substrate used can be understood to include the semiconductor substrate being processed, possibly including other thin film layers prepared thereon.

Described below is the process flow of an embodiment of manufacturing a planar channel semi-floating gate device using a method for manufacturing a planar channel semi-floating gate device of the present invention.

First, as shown in FIG. 2, a layer of photoresist 301 is deposited on the surface of the semiconductor substrate 200 with the first doping type on which the shallow trench isolation structure (not shown in the figure) has been formed, and a mask, Exposure and development to form a pattern, and then form a source region 201 and a drain region 202 with the second doping type respectively in the semiconductor substrate 200 and on both sides of the formed photoresist pattern through an ion implantation process, and are located in the source region The semiconductor substrate with the first doping type between the drain region 201 and the drain region 202 forms a channel region of the device. The semiconductor substrate 200 may be single crystal silicon, polycrystalline silicon or silicon on insulator. The first doping type is p-type, and the second doping type is n-type; or, correspondingly, the first doping type is n-type, and the second doping type is p-type.

After the photoresist 301 is stripped off, a first layer of insulating film 203 is grown on the surface of the semiconductor substrate 200. The first layer of insulating film 203 can be made of silicon dioxide, silicon nitride, silicon oxynitride, or silicon dioxide with a high dielectric constant value. insulating materials or for laminations between them. Next, deposit a layer of photoresist on the first layer of insulating film 203 and define the position of the floating gate opening region 204 through a photolithography process, and then use the photoresist as a mask to etch away the exposed first layer of insulating film. thin film 203 to form a floating gate opening region 204, as shown in FIG. 3 after stripping off the photoresist. The floating gate opening region 204 is located above the drain region 202 , and the distance between the edge of the floating gate region and the channel region is greater than 1 nanometer.

Next, deposit a layer of polysilicon with the first doping type on the exposed surface of the formed structure, then deposit a layer of photoresist on the formed polysilicon with the first doping type and pass The photolithography process defines the position of the floating gate of the device, and then uses the photoresist as a mask to etch away the exposed polysilicon with the first doping type, and the remaining polysilicon with the first doping type after etching The floating gate 205 of the device is formed. Then continue to etch away the exposed first insulating film 203 by using the floating gate 205 as a mask, and after stripping off the photoresist, as shown in FIG. 4 . The floating gate 205 should at least cover the channel region and the floating gate opening region 204 . The dopant impurities in the floating gate 205 will diffuse into the drain region 202 through the floating gate opening region 204 under the floating gate 205 to form a diffusion region 402, and form a pn junction between the floating gate 205 and the drain region 202 through the floating gate opening region 204 touch.

Next, deposit a second layer of insulating film 206 covering the formed structure. The second layer of insulating film 206 can be made of silicon dioxide, silicon nitride, silicon oxynitride, an insulating material with a high dielectric constant value, or one of them. interlayer. Next, a layer of polysilicon sacrificial material is deposited on the second layer of insulating film 206, and a third layer of insulating film 401 is deposited on the polysilicon sacrificial material. The third layer of insulating film 401 is silicon dioxide or silicon nitride. Then, the formed third insulating film 401 and polysilicon sacrificial material are etched by a photolithography process and an etching process, and the remaining polysilicon sacrificial material after etching forms a polysilicon control gate sacrificial material 207, and the polysilicon control gate sacrificial material 207 is formed along the trench The length in the track direction should exceed the floating gate 205, and cover and surround the floating gate 205, as shown in FIG. 5a after stripping the photoresist. Optionally, the third insulating film 401 and the polysilicon sacrificial material are etched by a photolithography process and an etching process, and the remaining polysilicon sacrificial material after etching forms the polysilicon control gate sacrificial material 207 of the device, and the polysilicon control gate sacrificial material 207 is Along the channel direction, only the length of one side of the drain region 202 exceeds the length of the floating gate 205, as shown in FIG. 5b.

Next, deposit and form a fourth layer of insulating film covering the formed structure, and etch back the formed fourth layer of insulating film to form gate spacers 208 on both sides of the polysilicon control gate sacrificial material 207, and then Continue to etch away the exposed second insulating film 206 along the gate spacer 208 , as shown in FIG. 6 . The gate spacer 208 can be made of silicon dioxide or silicon nitride, and the fourth insulating film is made of silicon oxide or silicon nitride.

Next, the source and drain are etched on both sides of the formed gate spacer 208, and silicon germanium or silicon carbide is epitaxially grown at the position after the source and drain etching to form the source contact region 209 and the drain contact. Area 210, as shown in Figure 7a. Optionally, instead of performing source and drain etching and epitaxial processes, ion implantation is directly used to form high-concentration ion-doped regions in the source region 201 and the drain region 202 respectively, so as to form the source contact region 209 and the drain contact region. Area 210, as shown in Figure 7b.

Next, as shown in FIG. 7a, a first layer of interlayer dielectric material 211 is deposited covering the formed structure, and the formed first layer of interlayer dielectric material 211 is polished by chemical mechanical polishing technology until the polysilicon control gate is exposed. Sacrificial material 207, as shown in FIG. 8 . Then etch away the exposed polysilicon control gate sacrificial material 207, and continue to etch away the exposed second insulating film 206, as shown in FIG. 9 . Then deposit and form a fifth layer of insulating film 212 and metal control gate material on the surface of the formed structure, and then carry out chemical mechanical polishing so that the polished metal control gate material occupies the position of the original polysilicon control gate sacrificial material 207 to form a metal The control grid 213 is shown in FIG. 10 . Optionally, the second insulating film 206 may not be etched away, but the fifth insulating film 212 and the metal control gate material may be deposited directly after the polysilicon control gate sacrificial material 207 is etched away, or the fifth insulating film 212 and the metal control gate material may not be etched away. The second layer of insulating film 206 is directly covered with the second layer of insulating film 206 after etching away the polysilicon control gate sacrificial material 207 to form a metal control gate material. The fifth layer of insulating film 212 can be silicon dioxide, silicon nitride, silicon oxynitride, insulating material with high dielectric constant, or a laminated layer between them.

Finally, as shown in FIG. 11, a second layer of interlayer dielectric material 214 is deposited covering the formed structure, and then contact holes are formed in the formed second layer of interlayer dielectric material 214 and the first layer of interlayer dielectric material 211. , and form a source electrode 215, a drain electrode 217 and a gate electrode 216, which is a well-known process in the industry.

Fig. 12 is an embodiment of the half-floating gate device structure of the planar channel of the double memory cell manufactured by the method for manufacturing the half-floating gate device of the planar channel of the present invention, which is composed of two devices as shown in Fig. 11 The half-floating gate device of the planar channel is formed, and the half-floating gate devices of the two planar channels form a symmetrical structure. As shown in Figure 12, the half-floating gate devices of the two planar channels share the drain region 202, the drain contact region 210 and the drain electrode 217, and the half-floating gate device structure of the planar channel of the double memory cell can store two bits The data.

FIG. 13 is a schematic circuit diagram of a memory cell array composed of a plurality of planar channel semi-floating gate devices as shown in FIG. 11 manufactured by a method for manufacturing a planar channel semi-floating gate device of the present invention. As shown in FIG. 13 , among the multiple source lines SL 603 a - 603 b , any one of them is connected to the sources of multiple semi-floating gate devices. Any one of the plurality of word lines WL 601a-601d is connected to the control gate of the plurality of semi-floating gate devices. Any one of the plurality of bit lines BL 602a-602d is connected to the drains of the plurality of semi-floating gate devices. Any one of the plurality of bit lines BL 602a-602d can be combined with any one of the plurality of word lines WL 601a-601d to select an independent half-floating gate device. Word lines WL 601a-601d can be selected by word line address decoder 901, bit lines BL 602a-602d can be selected by a bit line selection control module 902, and bit line selection control module 902 generally includes an address decoder, a multiplexer device and a set of sense amplifiers. Meanwhile, the source lines SL 603a and 603b can be connected with a common source line or a source line selection control module.

As mentioned above, many widely different embodiments can be constructed without departing from the spirit and scope of the present invention. It should be understood that the invention is not limited to the specific examples described in the specification, except as defined in the appended claims.

Claims (9)

1. A method for manufacturing a semi-floating gate device of a planar channel, characterized in that: the semi-floating gate device of a planar channel is prepared by a gate-last process, and after forming a source contact region and a drain contact region, the polysilicon control is etched away gate sacrificial material, and then make the metal control gate material occupy the position of the original polysilicon control gate sacrificial material to form the metal control gate, which specifically includes the following steps: A source region and a drain region having a second doping type are formed on the surface of the semiconductor substrate having the first doping type on which the shallow trench isolation structure has been formed, and the source region and the drain region between the source region and the drain region have A semiconductor substrate of the first doping type forms a channel region of the device; Form a first layer of insulating film on the surface of the semiconductor substrate, and etch the first layer of insulating film to form a floating gate opening area, the floating gate opening area is located above the drain region, and it is close to the channel The distance between one edge of the region and the channel region is greater than 1 nanometer; depositing a layer of polysilicon having a first doping type on the exposed surface of the formed structure; The position of the floating gate of the device is defined by a photolithography process, and then the polysilicon with the first doping type is etched using the photoresist as a mask, and the remaining polysilicon with the first doping type after etching forms the device A floating gate, the floating gate at least covers the channel region and the floating gate opening region, and a pn is formed between the floating gate and the drain region through the floating gate opening region under the floating gate Junction contact; Etching away the exposed first layer of insulating film using the floating gate as a mask; Depositing and forming a second layer of insulating film on the surface of the formed structure; Depositing a layer of polysilicon sacrificial material on the second layer of insulating film, and depositing a third layer of insulating film on the polysilicon sacrificial material; The third insulating film and polysilicon sacrificial material are etched by photolithography and etching processes, and the remaining polysilicon sacrificial material after etching forms the polysilicon control gate sacrificial material of the device, and the polysilicon control gate sacrificial material is formed along the channel The length in the direction exceeds the floating gate, and covers and surrounds the floating gate; Depositing and forming a fourth layer of insulating film covering the formed structure, and etching back the fourth layer of insulating film to form gate spacers on both sides of the polysilicon control gate sacrificial material, and then The exposed second layer of insulating film is etched away by the pole sidewall; performing source and drain etching on both sides of the gate spacer, and forming a source contact region and a drain contact region by an epitaxial process at the position after the source and drain etching; Deposit the first layer of interlayer dielectric material covering the formed structure, and then polish until the polysilicon control gate sacrificial material is exposed; etch the exposed polysilicon control gate sacrificial material, and then continue to etch the exposed second layer of insulation film; Deposit a fifth layer of insulating film and metal control gate material on the surface of the formed structure, and then perform polishing so that the polished metal control gate material occupies the position of the original polysilicon control gate sacrificial material, thereby forming a metal control gate; covering the formed Deposit a second layer of interlayer dielectric material, and then form a contact hole in the second layer of interlayer dielectric material and the first layer of interlayer dielectric material, and form a source electrode, a drain electrode and a gate electrode. 2. The manufacturing method of a semi-floating gate device with a planar channel according to claim 1, characterized in that: after etching away the exposed polysilicon control gate sacrificial material, the second layer of insulating film is reserved, and then A fifth layer of insulating film and a metal control gate material are deposited on the second layer of insulating film. 3. The manufacturing method of a semi-floating gate device with a planar channel according to claim 1, characterized in that: after etching away the exposed polysilicon control gate sacrificial material, the second layer of insulating film is reserved, and then The metal control gate material is directly deposited on the second layer of insulating film. 4. The manufacturing method of a planar channel semi-floating gate device according to claim 1, characterized in that: the first doping type is n-type, and the second doping type is p-type ; or, the first doping type is p-type, and the second doping type is n-type. 5. The manufacturing method of a semi-floating gate device with a planar channel according to claim 1, characterized in that: the first layer of insulating film, the second layer of insulating film and the fifth layer of insulating film are respectively Silicon, silicon nitride, silicon oxynitride, insulating material with high dielectric constant value or any one of stacked layers between them, the gate spacer, the third layer of insulating film and the fourth layer of insulating The thin films are either silicon dioxide or silicon nitride. 6 . The method for manufacturing a planar channel semi-floating gate device according to claim 1 , wherein the semiconductor substrate is any one of single crystal silicon, polycrystalline silicon, or silicon-on-insulator. 7. The method for manufacturing a semi-floating gate device with a planar channel according to claim 1, characterized in that: silicon germanium or silicon carbide is epitaxially epitaxy at the position after source and drain etching to form the source and drain contact regions. 8. The method for manufacturing a semi-floating gate device with a planar channel according to claim 1, characterized in that: after the gate spacer is formed, no source-drain etching and epitaxial process are performed, and the gate spacer is directly A high-concentration doped region is formed in the source region and the drain region on both sides of the source region and the drain region by ion implantation, so as to form the source contact region and the drain contact region. 9. The manufacturing method of a semi-floating gate device with a planar channel according to claim 1, characterized in that: etching the third layer of insulating film and polysilicon sacrificial material by photolithography process and etching process, engraving polysilicon sacrificial The sacrifice material forms the sacrificial material of the polysilicon control gate of the device, and the length of the sacrificial material of the polysilicon control gate in the direction of the channel exceeds that of the floating gate only on one side of the drain region.