CN104465662B - Monolayer polycrystalline EEPROM and preparation method thereof - Google Patents
Monolayer polycrystalline EEPROM and preparation method thereof Download PDFInfo
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Abstract
The invention relates to an EEPROM and a preparation method of the EEPROM, in particular to a monolayer polycrystalline EEPROM and a preparation method of the monolayer polycrystalline EEPROM and belongs to the technical field of semiconductors. According to the technical scheme, the monolayer polycrystalline EEPROM comprises a semiconductor substrate, wherein the upper portion in the semiconductor substrate is provided with a plurality of storage units used for data storage; each storage unit comprises a control capacitor, a PMOS programming transistor and a PMOS selection transistor which is connected with the PMOS programming transistor in series; the control capacitor is isolated from the PMOS programming transistor and the PMOS selection transistor through isolation media in the semiconductor substrate. The monolayer polycrystalline EEPROM is compact in structure, convenient to operate, safe and reliable, and lowers processing cost and process complexity.
Description
Technical field
The present invention relates to a kind of EEPROM and preparation method thereof, especially a kind of EEPROM with monolayer polycrystalline and its system
Preparation Method, belongs to the technical field of quasiconductor.
Background technology
EEPROM is indispensable electronic devices and components in modern electronic product.At present, eeprom memory is using E side
Prepared by technique processing obtains, and the memory element of EEPROM is typically with the polysilicon semiconductor technique preparation of bilayer, technique
Research and development and complex manufacturing process, it usually needs the time of several years researches and develops the process node of a quasiconductor.
Additionally, in chip architecture for an EEPROM, the programming or erasing for EEPROM needs 18V's or more
Being operated, what such periphery circuit was corresponding needs high voltage transistor to produce or bear above-mentioned operating voltage voltage.
For above-mentioned generation or bearing the transistor of high pressure, corresponding semiconductor technology processing procedure needs many upper several layers, therefore,
The cost increase and difficulty of technique can be caused to increase, it is difficult to adapt to the growth requirement for EEPROM.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided a kind of EEPROM with monolayer polycrystalline and
Its preparation method, its compact conformation reduce processing cost and process complexity, easy to operate, safe and reliable.
According to the technical scheme that the present invention is provided, the EEPROM with multilamellar monocrystalline, including semiconductor substrate；Institute
State top in semiconductor substrate and some memory element for data storage be set, the memory element include controlling electric capacity,
PMOS programming transistors and the PMOS selection transistors connected with the PMOS programming transistors；Control electric capacity passes through quasiconductor
Spacer medium in substrate is isolated with PMOS programming transistors and PMOS selection transistors；
The control electric capacity includes the P type trap zone in semiconductor substrate and floating above the P type trap zone
Gate electrode, is provided with floating gate oxide layers, the floating gate oxide layers and floating gate electrode between the floating gate electrode and the first P type trap zone
Also part covers the P+ regions in P type trap zone；
The PMOS programming transistors and PMOS selection transistors are respectively positioned in the N-type well region in semiconductor substrate, institute
State N-type well region to isolate with P type trap zone by spacer medium；PMOS programming transistors include the 2nd P+ positioned at N-type well region top
Region and the 4th P+ regions；Floating gate electrode on control electric capacity is extended to above PMOS programming transistors and by programming oxidation
Layer segment is covered in the top in the 2nd P+ regions and the 4th P+ regions；
The PMOS selection transistors are included positioned at the 2nd P+ regions and the 3rd P+ regions on N-type well region top, described
2nd P+ regions and the 3rd P+ overlying regions arrange word line electrode, selective oxidation layer segment of the word line electrode by lower section
It is covered on the 2nd P+ regions and the 3rd P+ regions.
The floating gate electrode is the conductive polycrystalline silicon of P conduction types, and floating gate electrode and word line electrode with word line electrode
For same technique manufactures layer.
The floating gate oxide layers, selective oxidation layer and programming oxide layer are silicon dioxide layer, and floating gate oxide layers, choosing
It is same technique manufactures layer to select oxide layer and programming oxide layer.
The material of the spacer medium is silicon dioxide；There is N conduction type deep traps, the p-type in semiconductor substrate
Well region and N-type well region are respectively positioned on the surface of N conduction type deep traps, and the bottom of P type trap zone and the bottom of N-type well region are equal
Adjacent N conduction types deep trap.
A kind of preparation method of the EEPROM with monolayer polycrystalline, the preparation method of the EEPROM comprise the steps：
A, semiconductor substrate of the offer with two corresponding interareas, described two interareas include the first interarea and second
Interarea；First barrier layer is set on the first interarea of semiconductor substrate, and is optionally sheltered and is etched first stop
Layer, to obtain the first window on the first barrier layer described in insertion；
B, N-type ion is carried out using above-mentioned first barrier layer and first window above the first interarea of semiconductor substrate
Injection, so that N conduction type deep traps are obtained in semiconductor substrate；
C, the first barrier layer removed on above-mentioned the first interarea of semiconductor substrate, with the first interarea of semiconductor substrate
The second barrier layer needed for arranging, optionally shelters and etches the second barrier layer, to obtain the second of the second barrier layer of insertion
Window；
D, N-type ion note is carried out on the first interarea of above-mentioned semiconductor substrate using the second barrier layer and the second window
Enter, to obtain the N-type well region above N conduction type deep traps；
E, the second barrier layer removed on above-mentioned the first interarea of semiconductor substrate, with the first interarea of semiconductor substrate
3rd barrier layer is set, the 3rd barrier layer is optionally sheltered and etch, to obtain the 3rd window on the 3rd barrier layer of insertion；
F, p-type ion is carried out in the first interarea of above-mentioned semiconductor substrate using above-mentioned 3rd barrier layer and the 3rd window
Injection, to obtain the P type trap zone above N conduction type deep traps；
G, the 3rd barrier layer removed on above-mentioned the first interarea of semiconductor substrate, and in the upper of above-mentioned N conduction types deep trap
Side arranges spacer medium, with will be P type trap zone mutually isolated with the top of N-type well region by spacer medium；
H, on the first interarea of above-mentioned semiconductor substrate arrange the 4th barrier layer, optionally shelter and etch the 4th resistance
Barrier, to obtain the 4th window on the 4th barrier layer of insertion；
I, p-type ion note is carried out on the first interarea of semiconductor substrate using above-mentioned 4th barrier layer and the 4th window
Enter, to obtain positioned at the P+ regions on N-type well region, P type trap zone top；
J, the 4th barrier layer removed on above-mentioned semiconductor substrate, and substrate is set on the first interarea of semiconductor substrate
Oxide layer；
K, electrode layer is set on the first interarea of above-mentioned semiconductor substrate, the electrode layer is located on substrate oxide layers；
L, above-mentioned electrode layer and substrate oxide layers are optionally sheltered and etch, to obtain on semiconductor substrate
Floating gate oxide layers, selective oxidation layer, word line electrode, floating gate electrode and programming oxide layer.
The material of the semiconductor substrate includes P conduction type silicon plates.
First barrier layer, the second barrier layer, the 3rd barrier layer and the 4th barrier layer are silicon dioxide layer or nitrogen
SiClx layer.
The substrate oxide layers are silicon dioxide layer, and electrode layer is the conductive polycrystalline silicon of P conduction types.
Advantages of the present invention：EEPROM includes controlling electric capacity, and PMOS programming transistors are mutually gone here and there with PMOS selection transistors
Connection, the floating gate electrode controlled on electric capacity are extended on PMOS programming transistors, to realize controlling capacitance series in PMOS programming crystalline substances
The gate terminal of body pipe, floating gate electrode are same technique manufactures layer with word line electrode, needed for being formed by the polycrystalline of monolayer
EEPROM, compact conformation reduce processing cost and process complexity, easy to operate, safe and reliable.
Description of the drawings
Fig. 1 is the equivalent circuit diagram of the present invention.
Fig. 2 is the plane graph of the present invention.
A-A sectional views of the Fig. 3 for Fig. 2.
B-B sectional views of the Fig. 4 for Fig. 2.
C-C sectional views of the Fig. 5 for Fig. 2.
Fig. 6 ~ Figure 13 be the present invention be embodied as processing step sectional view.
Fig. 6 is the sectional view after the present invention obtains N conduction type deep traps.
Fig. 7 is the sectional view after the present invention obtains N-type well region.
Fig. 8 is the sectional view after the present invention obtains P type trap zone.
Fig. 9 is the sectional view after the present invention obtains spacer medium.
Figure 10 is the sectional view after the present invention obtains P+ regions.
Figure 11 is the sectional view after the present invention obtains substrate oxide layers.
Figure 12 is the sectional view after the present invention obtains electrode layer.
Figure 13 is that the present invention obtains the sectional view after controlling electric capacity, PMOS programming transistors and PMOS selection transistors.
Description of reference numerals：1- semiconductor substrates, 2-N conduction type deep traps, 3-N type well regions, 4-P type well regions, 5- isolation
Medium, 6- floating gate oxide layers, 7- selective oxidation layers, 8- word line electrodes, 9- floating gate electrodes, the first P+ regions of 10-, the 2nd P+ of 11-
Region, the 3rd P+ regions of 12-, the 5th P+ regions of 13-, the first barrier layers of 14-, 15- first windows, the second barrier layers of 16-, 17-
Second window, 18- programming oxide layer, the 4th P+ regions of 19-, the 3rd barrier layers of 20-, the 3rd windows of 21-, the 4th barrier layers of 22-,
23- substrate oxide layers, the 4th window of 24- electrode layers and 25-.
Specific embodiment
With reference to concrete drawings and Examples, the invention will be further described.
As shown in Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Figure 13：In order to be able to reduce processing cost and process complexity, operation side
Just, the present invention includes semiconductor substrate 1；Top in the semiconductor substrate 1 arranges some storages for data storage
Unit, the memory element are included controlling electric capacity 30, PMOS programming transistors 40 and are gone here and there with the PMOS programming transistors 40
The PMOS selection transistors 50 of connection；Control electric capacity 30 is by the spacer medium 5 and PMOS programming transistors 40 in semiconductor substrate 1
And PMOS selection transistors 50 are isolated；
The control electric capacity 30 includes the P type trap zone 4 in semiconductor substrate 1 and is located above the P type trap zone 4
Floating gate electrode 9, be provided with floating gate oxide layers 6 between the floating gate electrode 9 and the first P type trap zone 4, the floating gate oxide layers 6 with
And the also part of floating gate electrode 9 covers the P+ regions 10 in P type trap zone 4；
The PMOS programming transistors 40 and PMOS selection transistors 50 are respectively positioned on the N-type well region 3 in semiconductor substrate 1
Interior, the N-type well region 3 is isolated with P type trap zone 4 by spacer medium 5；PMOS programming transistors 40 are included in N-type well region 3
The 2nd P+ regions 11 in portion and the 4th P+ regions 19；Floating gate electrode 9 on control electric capacity 30 extends to PMOS programming transistors
The top in the 2nd P+ regions 11 and the 4th P+ regions 19 is partially covered on above in the of 40 and by programming oxide layer 18；
The PMOS selection transistors 50 are included positioned at the 2nd P+ regions 11 and the 3rd P+ regions on 3 top of N-type well region
12, word line electrode 8 is set above the 2nd P+ regions 11 and the 3rd P+ regions 12, the word line electrode 8 is by lower section
Selective oxidation layer 7 is partially covered on the 2nd P+ regions 11 and the 3rd P+ regions 12.
Specifically, as shown in figure 1, control electric capacity 30 is connected to the gate terminal of PMOS programming transistors 40, PMOS programmings are brilliant
Body pipe 40 is in series with PMOS selection transistors 50.Wherein, formed between floating gate electrode 9, floating gate oxide layers 6 and P type trap zone 4
Capacitance structure, has the 5th P+ regions 13, floating gate oxide layers 6 and 9 part of floating gate electrode to cover P type trap zone 4 in P type trap zone 4
Interior P+ regions 10, the 5th P+ regions 13, part cover and refer to floating gate oxide layers 6, floating gate electrode 9 to be all covered in the
On one P+ regions 10 and the 5th P+ regions 13, the exterior lateral area in a P+ regions 10 and the 5th P+ regions 13 does not have floating
Gate oxide 6 and floating gate electrode 9, so that the loading for carrying out the voltages such as follow-up storage is operated, can be used by floating gate electrode 9
In storage electronics.
In N-type well region 3, PMOS programming transistors 40 share the 2nd P+ regions 11 with PMOS selection transistors 50, and control
The floating gate electrode 9 of electric capacity processed 30 extend and be located at after spacer medium 5 the 2nd P+ regions 11 in PMOS programming transistors 40, the
The top in four P+ regions 19, the floating gate electrode 9 above the 2nd P+ regions 11, the 4th P+ regions 19 is by programming oxide layer 18
Part covers the 2nd P+ regions 11 and the 4th P+ regions 19.Usually, programming electrode is needed on PMOS programming transistors 40,
The programming electrode is generally conductive polycrystalline silicon, and in the embodiment of the present invention, the programming electrode on PMOS programming transistors 4 is by floating boom
Electrode 9 stretches out and the top positioned at PMOS programming transistors 40 after spacer medium 5 is formed, so that PMOS programmings are brilliant
Floating gate electrode 9 on body pipe 4 is connected as a single entity with the floating gate electrode 9 on control electric capacity 30.
Part in the embodiment of the present invention covers and specifically refers to floating gate electrode 9, programming oxide layer 18 and be not exclusively covered in the
On two P+ regions 11 and the 4th P+ regions 19, and word line electrode 8 and selective oxidation layer 7 not exclusively cover the 2nd P+ regions 11 with
And the 3rd on P+ regions 12.
The floating gate electrode 9 is the conductive polycrystalline silicon of P conduction types, and floating gate electrode 9 and wordline electricity with word line electrode 8
Pole 8 is same technique manufactures layer.The floating gate oxide layers 6, selective oxidation layer 7 and programming oxide layer 18 are silicon dioxide
Layer, and floating gate oxide layers 6, selective oxidation layer 7 and programming oxide layer 8 are same technique manufactures layer.
The material of the spacer medium 5 is silicon dioxide；There is N conduction types deep trap 2, the P in semiconductor substrate 1
Type well region 4 and N-type well region 3 are respectively positioned on the surface of N conduction types deep trap 2, and bottom and the N-type well region 3 of P type trap zone 4
Bottom adjoin N conduction types deep trap 2.
In the embodiment of the present invention, control electric capacity 30 is in order to the voltage being carried on a P+ regions 10 is passed to floating boom electricity
On pole 9.It, for programming, is electron injection floating gate electrode 9, the electronics removed in floating gate electrode 9 that PMOS programming transistors 40 are
Use during with the whole EEPROM storage states of reading.PMOS selection transistors 50 for programming with read storage state when, isolation
Other memory element, it is to avoid produce interference.
As shown in Fig. 6 ~ Figure 13, by taking silicon plate of the semiconductor substrate 1 using P conduction types as an example, to said structure
EEPROM can be prepared using following processing steps, and the preparation method of the EEPROM comprises the steps：
A, the semiconductor substrate 1 with two corresponding interareas is provided, described two interareas include the first interarea and the
Two interareas；First barrier layer 14 is set on the first interarea of semiconductor substrate 1, and is optionally sheltered and is etched described first
Barrier layer 14, to obtain the first window 15 on the first barrier layer 14 described in insertion；
As shown in fig. 6, the first barrier layer 14 can be silicon dioxide layer or silicon nitride layer, by entering to the first barrier layer 14
Row etching obtains first window 15, by first window 15 with by the semiconductor substrate 1 corresponding with the first window 15
First interarea is exposed.First barrier layer 14 is performed etching obtain first window 15 processing step it is ripe for the art
Know, following concrete technology steps that window is obtained to barrier etch are identical, specifically repeat no more.
B, N is carried out using above-mentioned first barrier layer 14 and first window 15 above the first interarea of semiconductor substrate 1
Type ion implanting, to obtain N conduction types deep trap 2 in semiconductor substrate 1；
The work that N-type impurity ion implanting can adopt the art to commonly use is carried out on 1 first interarea of semiconductor substrate
Skill step, concrete technology condition can be selected as needed, as long as forming N conduction types deep trap 2 in semiconductor substrate 1
, the band of position of N conduction types deep trap 2 is corresponding to the same with first window 15.
C, the first barrier layer 14 removed on above-mentioned 1 first interarea of semiconductor substrate, to lead the first of semiconductor substrate 1
The second barrier layer 16 needed for arranging on face, optionally shelters and etches the second barrier layer 16, stopped with obtaining insertion second
Second window 17 of layer 16；
As shown in fig. 7, the second barrier layer 16 is also silicon dioxide layer or silicon nitride layer, partly will can be led by the second window 17
1 corresponding first interarea of structure base board is exposed, and the second window 17 is located at the position for forming N-type well region 3.
D, N-type is carried out using the second barrier layer 16 and the second window 17 on the first interarea of above-mentioned semiconductor substrate 1
Ion implanting, to obtain the N-type well region 3 above N conduction types deep trap 2；
In the embodiment of the present invention, the concentration impurity ion for forming N-type well region 3 in injection is less than and forms N conduction types deep trap 2
Concentration impurity ion, so as to N-type well region 3 is formed above the N conduction types deep trap 2.Form the concrete injection of N-type well region 3
Technique and process are known to those skilled in the art, and here is omitted.
E, the second barrier layer 14 removed on above-mentioned 1 first interarea of semiconductor substrate, to lead the first of semiconductor substrate 1
3rd barrier layer 20 is set on face, the 3rd barrier layer 20 is optionally sheltered and etch, to obtain the 3rd barrier layer 20 of insertion
3rd window 21；
As shown in figure 8, the 3rd barrier layer 20 is silicon dioxide layer or silicon nitride layer, the band of position of the 3rd window 21 with treat
The position for forming P type trap zone 4 is corresponding to the same.
F, P is carried out in the first interarea of above-mentioned semiconductor substrate 1 using above-mentioned 3rd barrier layer 20 and the 3rd window 21
Type ion implanting, to obtain the P type trap zone 4 above N conduction types deep trap 2；
Using the barrier effect on the 3rd barrier layer 20, P type trap zone 4, shape can be formed in the top of N-type guided missile type deep trap 2
Into N-type well region 3 from formed P type trap zone 4 difference be that the different foreign ion of injection is different, concrete technology step phase
Seemingly, here is omitted.
G, the 3rd barrier layer 20 removed on above-mentioned 1 first interarea of semiconductor substrate, and in above-mentioned N conduction types deep trap 2
Top spacer medium 5 is set, with will be P type trap zone 4 mutually isolated with the top of N-type well region 3 by spacer medium 5；
As shown in figure 9, spacer medium 5 can be silicon dioxide, spacer medium 5 can be prepared into by thermal oxidation technology
Arrive, it is also possible to obtained by trench fill in semiconductor substrate 1, specifically can be selected according to implementing process.P type trap zone
After 4 are isolated by spacer medium 5 with N-type well region 3, so that control electric capacity 30 can be selected with PMOS programming transistors 40 and PMOS
Select transistor 50 to be isolated.
H, the 4th barrier layer 22 is set on the first interarea of above-mentioned semiconductor substrate 1, optionally shelters and etch the
Four barrier layers 22, to obtain the 4th window 25 on the 4th barrier layer 22 of insertion；
As shown in Figure 10, the 4th barrier layer 22 is silicon dioxide layer or silicon nitride layer, can be in p-type trap by the 4th window 25
Injection in area 4 and N-type well region 3 obtains P+ regions.
I, p-type is carried out using above-mentioned 4th barrier layer 22 and the 4th window 25 on the first interarea of semiconductor substrate 1
Ion implanting, to obtain positioned at the P+ regions of N-type well region 3,4 top of P type trap zone；
In the embodiment of the present invention, the P+ regions for obtaining include the P+ regions 10 in P type trap zone 4 and
Five P+ regions 13, and the 2nd P+ regions 11 in N-type well region 3, the 3rd P+ regions 12 and the 4th P+ regions 19.
J, the 4th barrier layer 22 removed on above-mentioned semiconductor substrate 1, and arrange on the first interarea of semiconductor substrate 1
Substrate oxide layers 23；
As shown in figure 11, the substrate oxide layers 23 are silicon dioxide layer, and substrate oxide layers 23 are covered in semiconductor substrate 1
The first interarea on.It is used to form floating gate oxide layers 6, selective oxidation layer 7 and programming oxide layer 18 by substrate oxide layers 23.
K, on the first interarea of above-mentioned semiconductor substrate 1 arrange electrode layer 24, the electrode layer 24 be located at substrate oxidation
On layer 23；
As shown in figure 12, polysilicon of the electrode layer 24 for P conduction types.It is used to form floating gate electrode 9 by electrode layer 24
And word line electrode 8.
L, above-mentioned electrode layer 24 and substrate oxide layers 23 are optionally sheltered and etch, to obtain positioned at semiconductor substrate
Floating gate oxide layers 6, selective oxidation layer 7, word line electrode 8, floating gate electrode 9 and programming oxide layer 18 on 1.
As shown in figure 13, by the etching to substrate oxide layers 23 and electrode layer 24, floating gate oxide layers 6 is obtained, oxygen is selected
After changing layer 7, word line electrode 8, floating gate electrode 9 and programming oxide layer 18, so as to obtain controlling electric capacity 30, PMOS programming transistors
40 and the PMOS selection transistors 50 connected with the PMOS programming transistors 40.
When needing to be programmed whole EEPROM, need 3V voltages are loaded on a P+ regions 10, in the 3rd P+
5V voltages are loaded on region 12,5V voltages are loaded in N-type well region 3,0V voltages are loaded on the 4th P+ regions 19, in wordline electricity
0V voltages are loaded on pole 8, so that electron injection is in floating gate electrode 9, now the unlatching threshold value of PMOS programming transistors 40 becomes
It is little or be changed into positive unlatching threshold value from negative unlatching threshold value, so as to carry out data programming.
When needing to wipe whole EEPROM, -5V voltages are loaded on a P+ regions 10, in the 3rd P+ regions
5V voltages are loaded on 12,5V voltages are loaded in N-type well region 3,5V voltages are loaded on the 4th P+ regions 19, in word line electrode 8
Upper loading 5V voltages, by above-mentioned voltage, the high electric field formed in the programming oxide layer 18 of PMOS programming transistors 40 is more than
10MV/cm, forms the electric field needed for FN tunnel-effects, and the electronics in floating gate electrode 9 is removed by FN tunnels, that is, it is right to realize
The data erasing of EEPROM.
When needing to be read out whole EEPROM, by 0V voltages are loaded on a P+ regions 10, in the 3rd P+
1V voltages are loaded on region 12,2V voltages is loaded in N-type well region 2, the voltage of 2V is loaded on the 4th P+ regions 19, and in word
On line electrode 8 load 0V voltages, then by the larger data mode of 12 electric current of the 3rd P+ regions be " 1 ", by the 3rd P+ regions
The less data mode of 12 electric currents is " 0 " such that it is able to read the storage state of EEPROM.
EEPROM of the present invention includes controlling electric capacity 30, and PMOS programming transistors 40 are mutually gone here and there with PMOS selection transistors 50
Connection, the floating gate electrode 9 controlled on electric capacity 30 are extended on PMOS programming transistors 40, to realize that controlling electric capacity 30 is serially connected in PMOS
The gate terminal of programming transistor 40, floating gate electrode 9 are same technique manufactures layer with word line electrode 8, by the polycrystalline energy shape of monolayer
Into required EEPROM, compact conformation, processing cost and process complexity are reduced, it is easy to operate, it is safe and reliable.
Claims (5)
1. a kind of EEPROM with monolayer polycrystalline, including semiconductor substrate（1）；It is characterized in that：In the semiconductor substrate（1）
Interior top arranges some memory element for data storage, and the memory element includes controlling electric capacity（30）, PMOS programming
Transistor（40）And with the PMOS programming transistors（40）The PMOS selection transistors of series connection（50）；Control electric capacity（30）It is logical
Cross semiconductor substrate（1）Interior spacer medium（5）With PMOS programming transistors（40）And PMOS selection transistors（50）It is separated by
From；
The control electric capacity（30）Including positioned at semiconductor substrate（1）Interior P type trap zone（4）And it is located at the P type trap zone（4）
The floating gate electrode of top（9）, the floating gate electrode（9）With the first P type trap zone（4）Between be provided with floating gate oxide layers（6）, it is described floating
Gate oxide（6）And floating gate electrode（9）Also part covers P type trap zone（4）An interior P+ regions（10）；
The PMOS programming transistors（40）And PMOS selection transistors（50）It is respectively positioned on semiconductor substrate（1）Interior N-type trap
Area（3）It is interior, the N-type well region（3）By spacer medium（5）With P type trap zone（4）Isolation；PMOS programming transistors（40）Including
Positioned at N-type well region（3）The 2nd P+ regions on top（11）And the 4th P+ region（19）；Control electric capacity（30）On floating gate electrode
（9）Extend to PMOS programming transistors（40）Top simultaneously passes through to program oxide layer（18）It is partially covered on the 2nd P+ regions（11）With
And the 4th P+ region（19）Top；
The PMOS selection transistors（50）Including positioned at N-type well region（3）The 2nd P+ regions on top（11）And the 3rd P+ area
Domain（12）, the 2nd P+ regions（11）And the 3rd P+ region（12）Top arranges word line electrode（8）, the word line electrode
（8）By the selective oxidation layer of lower section（7）It is partially covered on the 2nd P+ regions（11）And the 3rd P+ region（12）On；
The floating gate electrode（9）With word line electrode（8）It is the conductive polycrystalline silicon of P conduction types, and floating gate electrode（9）With wordline
Electrode（8）For same technique manufactures layer；
The floating gate oxide layers（6）, selective oxidation layer（7）And programming oxide layer（18）It is silicon dioxide layer, and floating boom oxygen
Change layer（6）, selective oxidation layer（7）And programming oxide layer（8）For same technique manufactures layer；
The spacer medium（5）Material be silicon dioxide；In semiconductor substrate（1）It is interior with N conduction type deep traps（2）, institute
State P type trap zone（4）And N-type well region（3）It is respectively positioned on N conduction type deep traps（2）Surface, and P type trap zone（4）Bottom with
And N-type well region（3）Bottom adjoin N conduction type deep traps（2）.
2. a kind of preparation method of the EEPROM with monolayer polycrystalline, is characterized in that, the preparation method of the EEPROM include as
Lower step：
（a）, provide with two corresponding interareas semiconductor substrate（1）, described two interareas include the first interarea and
Two interareas；In semiconductor substrate（1）The first interarea on the first barrier layer is set（14）, and optionally shelter and etch described
First barrier layer（14）, to obtain the first barrier layer described in insertion（14）First window（15）；
（b）, using above-mentioned first barrier layer（14）And first window（15）In semiconductor substrate（1）The first interarea above enter
Row N-type ion implanting, with semiconductor substrate（1）N conduction type deep traps are obtained inside（2）；
（c）, remove above-mentioned semiconductor substrate（1）The first barrier layer on first interarea（14）, with semiconductor substrate（1）
The second barrier layer needed for arranging on one interarea（16）, optionally shelter and etch the second barrier layer（16）, to obtain insertion
Second barrier layer（16）The second window（17）；
（d）, using the second barrier layer（16）And second window（17）In above-mentioned semiconductor substrate（1）The first interarea on carry out
N-type ion implanting, to obtain positioned at N conduction type deep traps（2）The N-type well region of top（3）；
（e）, remove above-mentioned semiconductor substrate（1）The second barrier layer on first interarea（14）, with semiconductor substrate（1）
3rd barrier layer is set on one interarea（20）, optionally shelter and etch the 3rd barrier layer（20）, to obtain the 3rd resistance of insertion
Barrier（20）The 3rd window（21）；
（f）, using above-mentioned 3rd barrier layer（20）And the 3rd window（21）In above-mentioned semiconductor substrate（1）The first interarea enter
Row p-type ion implanting, to obtain positioned at N conduction type deep traps（2）The P type trap zone of top（4）；
（g）, remove above-mentioned semiconductor substrate（1）The 3rd barrier layer on first interarea（20）, and in above-mentioned N conduction types deep trap
（2）Top arrange spacer medium（5）, with by spacer medium（5）By P type trap zone（4）With N-type well region（3）Top it is mutual
Isolation；
（h）, in above-mentioned semiconductor substrate（1）The first interarea on arrange the 4th barrier layer（22）, optionally shelter and etch
4th barrier layer（22）, to obtain the 4th barrier layer of insertion（22）The 4th window（25）；
（i）, using above-mentioned 4th barrier layer（22）And the 4th window（25）In semiconductor substrate（1）The first interarea on carry out
P-type ion implanting, to obtain positioned at N-type well region（3）, P type trap zone（4）The P+ regions on top；
（j）, remove above-mentioned semiconductor substrate（1）On the 4th barrier layer（22）, and in semiconductor substrate（1）The first interarea on
Substrate oxide layers are set（23）；
（k）, in above-mentioned semiconductor substrate（1）The first interarea on electrode layer is set（24）, the electrode layer（24）Positioned at substrate
Oxide layer（23）On；
（l）, optionally shelter and etch above-mentioned electrode layer（24）And substrate oxide layers（23）, to obtain positioned at semiconductor-based
Plate（1）On floating gate oxide layers（6）, selective oxidation layer（7）, word line electrode（8）, floating gate electrode（9）And programming oxide layer
（18）.
3. there is the preparation method of the EEPROM of monolayer polycrystalline according to claim 2, it is characterized in that, the semiconductor substrate
（1）Material include P conduction type silicon plates.
4. there is the preparation method of the EEPROM of monolayer polycrystalline according to claim 2, it is characterized in that, first barrier layer
（14）, the second barrier layer（16）, the 3rd barrier layer（20）And the 4th barrier layer（22）It is silicon dioxide layer or silicon nitride layer.
5. there is the preparation method of the EEPROM of monolayer polycrystalline according to claim 2, it is characterized in that, the substrate oxide layers
（23）For silicon dioxide layer, electrode layer（24）For the conductive polycrystalline silicon of P conduction types.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410785392.7A CN104465662B (en) | 2014-12-16 | 2014-12-16 | Monolayer polycrystalline EEPROM and preparation method thereof |
Applications Claiming Priority (1)
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| CN1459869A (en) * | 2002-05-24 | 2003-12-03 | 力旺电子股份有限公司 | A single-layer polysilicon electrically erasable programmable read-only memory |
| CN204243039U (en) * | 2014-12-16 | 2015-04-01 | 无锡来燕微电子有限公司 | A kind of EEPROM with single-layer polycrystalline |
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| US8658495B2 (en) * | 2012-03-08 | 2014-02-25 | Ememory Technology Inc. | Method of fabricating erasable programmable single-poly nonvolatile memory |
| US8592886B2 (en) * | 2012-03-08 | 2013-11-26 | Ememory Technology Inc. | Erasable programmable single-ploy nonvolatile memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1459869A (en) * | 2002-05-24 | 2003-12-03 | 力旺电子股份有限公司 | A single-layer polysilicon electrically erasable programmable read-only memory |
| CN204243039U (en) * | 2014-12-16 | 2015-04-01 | 无锡来燕微电子有限公司 | A kind of EEPROM with single-layer polycrystalline |
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