CN104486261A - Interlaken interface-based two-chip interconnection method - Google Patents
Interlaken interface-based two-chip interconnection method Download PDFInfo
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Abstract
The invention discloses an interlaken interface-based two-chip interconnection method. The method comprises the following steps: interconnecting two chips by virtue of an interlaken interface, determining a destination forwarding port of a message by searching a forwarding table item after the message enters anyone chip, forwarding the message to the interlaken interface if the fording manner is a chip crossing forwarding manner, receiving the message by an end chip from the interlaken interface, then mapping the message to an inner port, forwarding the message to a destination port which is directly connected to the inner port by virtue of the inner port, and finally forwarding the message from an external port corresponding to the destination port. By virtue of the interlaken interface-based two-chip interconnection method, the complexity of system software is simplified; meanwhile, a switch system can be used for supporting higher communication capability and more ports.
Description
Technical field
The present invention relates to network communication technology field, especially relate to a kind of dual chip interconnecting method based on interlaken interface.
Background technology
In existing switch system, in order to support larger communication capacity and more port, multiple exchange chip usually can be adopted to interconnect.Current exchanger chip manufacturer, the method realizing multiple chip interconnects can use custom chip (Fabric chip) to interconnect usually.But this custom chip price is very expensive, this will strengthen the cost of product undoubtedly greatly; And adopt the scheme of Fabric chip, usually need the quantity seeing interconnect die when systemic software development, like this for software exploitation too increase complexity.
For use the chip of HSSI High-Speed Serial Interface agreement (interlaken) mutual connection can orientate as Master (master) and Slave (from) two kinds of patterns.Under Master pattern, exchange chip can carry out the forwarding of message; The dest (destination interface) that can come according to the band in interlaken protocol massages in slave pattern is forwarded to corresponding destination interface.In the equipment use of traditional interlaken interfaces interconnect, normally an equipment is Master, and another one equipment is Slave.Slave does not normally possess transfer capability, just message is delivered on Master equipment and carries out searching transmitting forwarding.
Summary of the invention
The object of the invention is to the defect overcoming prior art, a kind of dual chip interconnecting method based on interlaken interface is provided, to shield the quantity of exchange chip, thus simplify the complexity of systems soft ware.
For achieving the above object, the present invention proposes following technical scheme: a kind of dual chip interconnecting method based on interlaken interface, comprises the following steps:
By two chips by interlaken interfaces interconnect, externally have multiple outside port after interconnection, each described chip internal has multiple logic port, and described logic port comprises the internal port of direct port connection and the object logic port of corresponding outside port;
When message enters into after in any chip piece from described outside port, be first mapped on logic port corresponding in chip, then search the destination interface transmitted and obtain message repeating according to the message in chip;
Forward if local, then direct the object outside port of message from correspondence to be forwarded; If forward across chip, then message is first forwarded on interlaken interface, after the chip of opposite end receives message from interlaken interface, message is mapped on its internal port, by described internal port, message is sent to the object logic port direct-connected with it, finally forwards out from the outside port of correspondence.
Preferably, in two described chips, the message repeating table of configuration is identical.
Preferably, if forward across chip, then message is first forwarded on interlaken interface, and is carried in interlaken protocol massages by described destination interface.
Preferably, after the chip of opposite end receives message from interlaken interface, first from described interlaken protocol massages, recover described destination interface information, offset base value according to port corresponding with described Interlaken interface on self chip again, message is mapped on inner corresponding described internal port.
Preferably, if across chip forward, after message is mapped to internal port, by direct port connection message repeating to object logic port.
The invention has the beneficial effects as follows: the invention provides a kind of method based on interlaken Interface realization chip interconnects, concerning the quantity that can shield exchange chip upper system software, be equivalent to only process a chip, thus simplify the complexity of systems soft ware, also realize switch system simultaneously and can support larger communication capacity and more port.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the method that the present invention is based on interlaken Interface realization chip interconnects;
Fig. 2 is the principle schematic of the embodiment of the present invention based on the method for interlaken Interface realization chip interconnects.
Embodiment
Below in conjunction with accompanying drawing of the present invention, clear, complete description is carried out to the technical scheme of the embodiment of the present invention.
As shown in Figure 1, present invention is disclosed a kind of method based on interlaken Interface realization chip interconnects, comprise the following steps:
Step S1, by two chips by interlaken interfaces interconnect, externally have multiple outside port after interconnection, each chip internal has multiple logic port, and logic port comprises the internal port of direct port connection and the object logic port of corresponding outside port;
Step S2, when message enters into after in any chip piece from outside port, now this chip is in main (Master) pattern, is first mapped on logic port corresponding in chip, then searches the destination interface transmitted and obtain message repeating according to the message in chip;
Step S3, forwards if local, then directly forwarded by the object outside port of message from correspondence, if forward across chip, then message is first forwarded on interlaken interface, and destination interface is carried in interlaken protocol massages, after the chip of opposite end receives message from interlaken interface, the now chip of opposite end, be in from (Slave) pattern, first from interlaken protocol massages, recover destination interface information, base value (portbase) is offset again according to port corresponding with Interlaken interface on self chip, message is mapped on inner corresponding described internal port, by internal port, message is sent to the object logic port direct-connected with it, finally forward out from the outside port of correspondence.
Preferably, the present invention, when configuring forwarding information, two chips configures identical message repeating table, so just can reach the effect of two chips when a chip process, thus simplify the cost of software development.
As shown in Figure 2, the embodiment of the present invention, with two identical chip interconnects, specifically introduces the dual chip interconnecting method that the present invention is based on interlaken interface.
By interlaken interfaces interconnect between Fig. 2 chips 1 (Chip 1) and chip 2 (Chip 2).If chip 1 and chip 2 all have 12 outside ports and 36 inner local logic ports, like this, externally altogether has 24 external physical ports after interconnection, namely externally visible is 1 ~ 24 port.Certainly, the outside port of chip and local logic port number are not unique.
In 36 local logic ports of two chips, wherein front 24 ports (LPort1 ~ 24) be used for expression two interconnection after chip one have 24 network ports, rear 12 ports (LPort25 ~ 36) are used for the internal port that direct port connection (Port cross connect) uses.
Wherein, between port LPort1 ~ 12 of chip 1 and self outside port 1-12, between port LPort13 ~ 24 and the outside port 1-12 of chip 2, there is man-to-man port mapping relationship.In like manner, between port LPort1 ~ 12 of chip 2 and the outside port 1-12 of chip 1, between port LPort13 ~ 24 and self outside port 1-12, there is man-to-man port mapping relationship.
Particularly, as in the embodiment of the present invention, 24 logic ports of chip 1 and the outside port of himself and and the outside port of chip 2 between mapping relations as follows:
LPort1 ~ 12---> Chip 1 port one-12
LPort13 ~ 24---> Chip 2 port one-12
Namely local logic port LPort1 ~ 12 of chip 1 are mapped to himself outside port and get on, and the outside port that local logic port LPort13 ~ 24 are mapped to chip 2 gets on.
24 logic ports of chip 2 and the outside port of himself and and the outside port of chip 2 between mapping relations as follows:
LPort1 ~ 12---> Chip 1 port one-12
LPort13 ~ 24---> Chip 2 port one-12
Namely the outside port that local logic port LPort1 ~ 12 of chip 2 are mapped to chip 1 gets on, and the outside port that local logic port LPort13 ~ 24 are mapped to himself gets on.
Port LPort13 ~ 24 are mapped to Interlaken interface by chip 1 get on, port LPort1 ~ 12 are mapped to interlaken interface by chip 2 and get on.
After receiving message, corresponding local to forward or across chip processing procedure is carried out to message by the chip after interlaken interfaces interconnect.
Particularly, be described for chip 1, message repeating flow process and the chip 1 of chip 2 are similar.When message is from outside port 1 ~ 12, as entered into from port one after in chip 1, first be mapped on logic port LPort1 corresponding in chip 1, then the destination interface address (dest id) of transmitting and obtaining message repeating is searched according to the message in chip, if dest id is local outside port 1 ~ 12, then represent it is local forwarding, directly the object outside port of message from correspondence is forwarded, suppose obtain dest id be 11, such message be exactly direct from outside port 11 out.
If dest id is outside port 13 ~ 24, then represents and will be forwarded to opposite end chip 2, namely forward across chip, suppose that dest id is 14, then as follows to the detailed process of Message processing:
Message is forwarded on Interlaken interface on chip 1, and is carried in interlaken protocol massages by dest id, and now, chip 1 is in Master pattern; After the message that chip 2 forwards from interlaken interface to chip 1, now, chip 2 is in Slave pattern, first from interlaken protocol massages, recover object dest id information, according to dest Id=DestPort 14, and according to destination interface mark dest id+portbase (12)---the mapping relations of the inner LPort of-> chip 2 (25 ~ 36), are mapped to message on chip 2 internal port LPort 26.
Wherein, logic port LPort13 ~ 24 are specially with the mapping relations of the inner LPort of chip 2 (25 ~ 36):
LPort25-----＞LPort13
LPort26-----＞LPort14
………
LPort36-----＞LPort24
The internal port LPort 26 of chip 2 forwards the packet to logic port LPort14 direct-connected with it, carries out Port cross connect message repeating.
Finally, by logic port LPort14, the object outside port 14 of message from chip 2 correspondence is forwarded.
In like manner, when message is from the external network port repeat of chip 2 to chip 1, when namely carrying out forwarding across chip to message, suppose that dest id is 1, as follows to the detailed process of Message processing:
Message is forwarded on Interlaken interface on chip 2, and is carried in interlaken protocol massages by dest id, and now, chip 2 is in Master pattern; After the message that chip 1 forwards from interlaken interface to chip 1, now, chip 1 is in Slave pattern, first from interlaken protocol massages, recover object dest id information, according to dest Id=DestPort 1, and according to destination interface mark dest id+portbase (24)---the mapping relations of the inner LPort 25 of-> chip 1, are mapped to message on chip 1 internal port LPort 25.
Logic port LPort1 ~ 12 are specially with the mapping relations of the inner LPort of chip 1 (25 ~ 36):
LPort25-----＞LPort1
LPort26-----＞LPort2
………………
LPort36-----＞LPort12
The internal port LPort 25 of chip 1 forwards the packet to logic port LPort 1 direct-connected with it, carries out Port cross connect message repeating.
Finally, by chip 1 logic port LPort 1, the object outside port 1 of message from correspondence is forwarded.
The embodiment of the present invention only needs 24 the internal logic ports processing corresponding ports when software development, on two chips, identical transmitting is configured while configuration forwarding information, just can reach the effect of two chips when a chip process, thus simplify the cost of software development.
In addition, two chips in the embodiment of the present invention also can be used as Slave equipment as while Master equipment.Difference is different data message process different: the message of coming in from external network port, and this equipment is in Master pattern, can to this message transmit search after forward.For the message of coming from interlaken interface, now equipment is in slave pattern, can be forwarded to corresponding port get on according to destination interface (dest) information with coming in interlaken agreement.
Technology contents of the present invention and technical characteristic have disclosed as above; but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement; therefore; scope should be not limited to the content that embodiment discloses; and various do not deviate from replacement of the present invention and modification should be comprised, and contained by present patent application claim.
Claims (5)
1., based on a dual chip interconnecting method for interlaken interface, it is characterized in that, comprise the following steps:
By two chips by interlaken interfaces interconnect, externally have multiple outside port after interconnection, each described chip internal has multiple logic port, and described logic port comprises the internal port of direct port connection and the object logic port of corresponding outside port;
When message enters into after in any chip piece from described outside port, be first mapped on logic port corresponding in chip, then search the destination interface transmitted and obtain message repeating according to the message in chip;
Forward if local, then direct the object outside port of message from correspondence to be forwarded; If forward across chip, then message is first forwarded on interlaken interface, after the chip of opposite end receives message from interlaken interface, message is mapped on its internal port, by described internal port, message is sent to the object logic port direct-connected with it, finally forwards out from the outside port of correspondence.
2. the method based on interlaken Interface realization chip interconnects according to claim 1, is characterized in that, in two described chips, the message repeating table of configuration is identical.
3. the method based on interlaken Interface realization chip interconnects according to claim 1 and 2, it is characterized in that, if forward across chip, then message is first forwarded on interlaken interface, and is carried in interlaken protocol massages by described destination interface.
4. the method based on interlaken Interface realization chip interconnects according to claim 3, it is characterized in that, after the chip of opposite end receives message from interlaken interface, first from described interlaken protocol massages, recover described destination interface information, offset base value according to port corresponding with described Interlaken interface on self chip again, message is mapped on inner corresponding described internal port.
5. the method based on interlaken Interface realization chip interconnects according to claim 1 or 4, is characterized in that, if across chip forward, after message is mapped to internal port, by direct port connection message repeating to object logic port.
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| CN201410799697.3A CN104486261A (en) | 2014-12-19 | 2014-12-19 | Interlaken interface-based two-chip interconnection method |
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Citations (5)
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| CN101557275A (en) * | 2008-04-08 | 2009-10-14 | 华为技术有限公司 | Method and device for fluid controller information transfer in interconnection application |
| CN102308538A (en) * | 2011-07-20 | 2012-01-04 | 华为技术有限公司 | Message processing method and device |
| CN102638398A (en) * | 2012-03-21 | 2012-08-15 | 华为技术有限公司 | Method for indicating port states and switch |
| CN102821458A (en) * | 2012-08-13 | 2012-12-12 | 华为技术有限公司 | Dynamic link adjustment method and link management equipment |
| US20130104012A1 (en) * | 2011-10-25 | 2013-04-25 | Cavium, Inc. | Bit Error Rate Impact Reduction |
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- 2014-12-19 CN CN201410799697.3A patent/CN104486261A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101557275A (en) * | 2008-04-08 | 2009-10-14 | 华为技术有限公司 | Method and device for fluid controller information transfer in interconnection application |
| CN102308538A (en) * | 2011-07-20 | 2012-01-04 | 华为技术有限公司 | Message processing method and device |
| US20130104012A1 (en) * | 2011-10-25 | 2013-04-25 | Cavium, Inc. | Bit Error Rate Impact Reduction |
| CN102638398A (en) * | 2012-03-21 | 2012-08-15 | 华为技术有限公司 | Method for indicating port states and switch |
| CN102821458A (en) * | 2012-08-13 | 2012-12-12 | 华为技术有限公司 | Dynamic link adjustment method and link management equipment |
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Application publication date: 20150401 |