CN104576511A - Method for fabricating interconnect and interconnect structure - Google Patents

Abstract

A method for fabricating an interconnect and an interconnect structure are provided. A substrate is provided, on which a first dielectric layer is formed, and two plugs are formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench is formed in the second dielectric layer exposing the two plugs. A metal wire is formed on each plug.

Description

Method for making internal connection and structure of internal connection

technical field

The invention relates to a method for manufacturing a semiconductor element, and in particular to a method for manufacturing an interconnection line in the semiconductor element.

Background technique

In the current semiconductor process, tungsten is often used to fill contact vias to form so-called plugs or metal lines to connect metal layers and silicon or to connect different metal layers. Ideally, it would be desirable for the contact window material to have as low a resistivity as possible to achieve a faster current conduction rate.

As the size of IC components shrinks, the contact hole between the wiring layers will become smaller and narrower, thus increasing the gap-fill capability of the tungsten wire (W metal line). Require. If the filling ability of the tungsten wire is not good, voids or seams will be formed in the wire, which will cause the resistance value of the tungsten wire to increase and the performance of the device to decrease.

Since tungsten metal cannot be well adsorbed on the surface of silicon dioxide when tungsten is formed by chemical vapor deposition (CVD), sometimes a layer of titanium nitride (TiN) is first filled when filling tungsten to help tungsten adhere. , and prevent the fluorine in the reactant tungsten hexafluoride (WF ₆ ) gas from reacting with silicon dioxide when tungsten is formed by CVD. However, the resistance value of titanium nitride is higher than that of tungsten, which will cause the resistance value of the tungsten wire to increase, resulting in a decrease in device performance.

Contents of the invention

The invention provides an internal connection structure and a manufacturing method of the internal connection, which can manufacture metal internal connections with high conductivity.

The manufacturing method of the interconnection wire of the present invention includes the following steps. A substrate is provided, on which a first dielectric layer has been formed, and two plugs have been formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench exposing the two plugs is formed in the second dielectric layer. A metal wire is formed on each plug respectively.

In an embodiment of the present invention, the extending direction of the trench is substantially perpendicular to the connecting direction of the two plugs.

In an embodiment of the present invention, the method for forming a metal wire on each plug includes: conformally forming a metal layer on a substrate; and the metal layer on the second dielectric layer and the metal layer on the second dielectric layer. the metal layer between the two plugs.

In an embodiment of the present invention, the method for forming a metal wire on each plug includes: forming a metal layer in the trench, the metal layer including a first portion and a second portion formed on opposite side walls of the trench. part, and a third part connecting the first part and the second part and formed at the bottom of the trench; and removing the third part.

In an embodiment of the present invention, after removing the third part, the first part forms a metal wire electrically connected to one of the two plugs, and the second part forms a metal wire electrically connected to one of the two plugs. Another metal wire electrically connected to the other one.

In an embodiment of the invention, after removing the third part, a dielectric material is filled between the first part and the second part.

In an embodiment of the present invention, before forming a metal wire on each plug, the method for making the interconnect further includes conformally forming a barrier layer on the substrate.

In an embodiment of the present invention, the method for fabricating an interconnect further includes removing the barrier layer on the second dielectric layer and the barrier layer between the two plugs.

In an embodiment of the invention, the second dielectric layer is a composite dielectric layer including two different dielectric materials.

The interconnection structure of the present invention includes a first dielectric layer, a second dielectric layer, a plug, a wire and a barrier layer. The second dielectric layer is configured on the first dielectric layer. The plug is configured in the first dielectric layer and extends to the second dielectric layer. The wire is disposed in the second dielectric layer and located on the plug. The wire has two opposite sides, and a barrier layer is arranged between one side of the wire and the second dielectric layer, and there is no barrier layer between the other side of the wire and the second dielectric layer.

Based on the above, the present invention provides an interconnection structure and a method for making an interconnection, which can solve the problem of voids or gaps formed inside the conductor due to the poor gap filling ability of the conductor material, and can improve the performance of the conductor. Conductivity.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail as follows.

Description of drawings

1A to 1I are flowcharts of a method for manufacturing an interconnect line according to a first embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100: first dielectric layer

101: mask layer

102: plug

104: second dielectric layer

104a: lower dielectric layer

104b: upper dielectric layer

106: Ditch

108: barrier layer

110: metal layer

110a: Part I

110b: Part II

110c: Part Three

111: metal wire

112: Dielectric material

D: Spacing

W: width

Detailed ways

The first embodiment of the present invention provides a method for fabricating an interconnection line. FIG. 1A to FIG. 1I are schematic cross-sectional flowcharts according to the first embodiment.

Referring to FIG. 1A , in the first embodiment, the method for fabricating an interconnect includes providing a substrate. The substrate may be any type of semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and various semiconductor elements, plugs and wiring layers communicating with each element may have been formed in the substrate. Since the substrate can have many changes, and no matter how it is changed, it falls within the scope of protection of the present invention, so it is not shown in the drawings.

A first dielectric layer 100 has been formed on the substrate, and at least two plugs 102 have been formed in the first dielectric layer 100 . The material of the first dielectric layer 100 is, for example, silicon dioxide (SiO ₂ ); the material of the plug 102 is, for example, polysilicon or tungsten. The plugs 102 will electrically connect the wires to be formed on the first dielectric layer 100 and the components formed under the first dielectric layer 100 . The formation methods of the first dielectric layer 100 and the plug 102 are well known to those skilled in the art, and will not be repeated here.

Next, a second dielectric layer 104 is formed on the first dielectric layer 100 . As shown in FIG. 1A , in this embodiment, the second dielectric layer 104 is a composite dielectric layer including two different dielectric materials. Specifically, the second dielectric layer 104 may include a lower dielectric layer 104a and an upper dielectric layer 104b, wherein the material of the lower dielectric layer 104a is different from that of the first dielectric layer 100, such as silicon nitride (SiN), The material of the upper dielectric layer 104b can be the same as that of the first dielectric layer 100, such as silicon dioxide. Certainly, the present invention is not limited thereto, and the second dielectric layer 104 may also be a dielectric layer formed of a single material. The method of forming the second dielectric layer 104 is also well known, for example, chemical vapor deposition (CVD) can be used, and other known methods will not be repeated here.

It should also be noted that the plug 102 extends from the first dielectric layer 100 to the second dielectric layer 104 . In this embodiment where the second dielectric layer 104 is a composite dielectric layer, the plug 102 is covered by the lower dielectric layer 104 a of the second dielectric layer 104 .

Referring to FIG. 1B , next, a patterned mask layer 101 is formed on the second dielectric layer 104 to define the positions of trenches to be formed. The mask layer 101 may be a photoresist (PR) or a hard mask, and its formation method may be a lithography process or a lithography process combined with a dielectric etching process.

Please refer to FIG. 1C, and then, a trench 106 is formed in the second dielectric layer 104. The method is, for example, a dry etching method. etch, and then etch the lower dielectric layer 104a until the plug 102 is exposed. Each trench 106 exposes exactly two plugs 102 . FIG. 1C shows a cross-sectional view of the ditch 106 . In other words, the extending direction (z direction) of the ditch 106 is substantially perpendicular to the paper and also perpendicular to the connection direction (x direction) of the two plugs 102 . At the same time, it should also be noted that in this embodiment, the width W of the trench 106 is very close to the distance D between the two plugs 102, but the former is slightly larger than the latter, so that the metal layer formed on the trench 106 can be roughly positioned at the center of the plug. Above the plug 102 , wires electrically connected to the plug 102 are formed. A more detailed description will be given below on this point.

After the trench 106 is formed, the mask layer 101 may be removed.

Referring to FIG. 1D , a barrier layer 108 is conformally formed on the substrate. The material of the barrier layer 108 needs to be selected so that it has better affinity with the second dielectric layer 104 and with the wire material to be filled in the trench 106, so that the wire material can be attached smoothly on the sidewall of the trench 106 . In addition, during the filling of the wire material, the source gas of the wire material may react with the material of the second dielectric layer 104 , and the barrier layer 108 can also prevent this phenomenon. In this regard, where the material of the second dielectric layer 104 is silicon dioxide and the material of the wires to be filled in the trench 106 is tungsten, the barrier layer 108 may be titanium/titanium nitride (Ti/TiN) The composite layer structure, and its formation method is, for example, first conformally forming a layer of titanium metal layer on the substrate, and then forming a layer of titanium nitride layer conformally covering the titanium metal layer. In addition, the method of forming the titanium metal layer and the titanium nitride layer may utilize a reactive sputtering method or a nitriding reaction method.

Despite the above benefits of forming the barrier layer 108, however, the conductivity of the barrier layer 108 is generally not as good as that of the wire material. Therefore, the formation of the barrier layer 108 may also increase the overall resistance of the wires, resulting in a decrease in device performance. This problem can be solved by the manufacturing method of the interconnection proposed by the present invention, the details of which are described below.

Referring to FIG. 1E , a metal layer 110 is conformally formed on the substrate. The material of the metal layer 110 is, for example, tungsten, and its forming method is, for example, a chemical vapor deposition process using tungsten hexafluoride (WF ₆ ) as a source gas. Wherein, the metal layer 110 formed in the trench 106 includes a first portion 110 a and a second portion 110 b formed on opposite side walls of the trench 106 , and a metal layer connecting the first portion 110 a and the second portion 110 b and formed at the bottom of the trench 106 The third part 110c. As described above, since the width of the ditch 106 is roughly equivalent to the distance between the two plugs 102, the first portion 110a and the second portion 110b formed on the sidewall of the ditch 106 are roughly positioned at each a plug 102 above.

Referring to FIG. 1F , next, the metal layer 110 above the second dielectric layer 104 is removed, and the third portion 110 c of the metal layer 110 between the two plugs 102 is removed at the same time. In the embodiment depicted in Figure IF, the removal method is dry etching. In addition to the third portion 110c, in addition, portions of the tops of the first portion 110a and the second portion 110b may also be removed. At this time, the remaining first portion 110 a forms a metal wire electrically connected to the corresponding plug 102 . Likewise, the remaining second portion 110 b forms a metal wire electrically connected to the corresponding plug 102 .

Referring to FIG. 1G, then, the barrier layer 108 above the second dielectric layer 104 is removed, and the barrier layer 108 between the two plugs 102 at the bottom of the trench 106 is removed at the same time, so as to avoid adjacent plugs 102 are short-circuited by the barrier layer 108 . The method of removing the barrier layer 108 may be dry etching in this embodiment.

Referring to FIG. 1H, next, a dielectric material 112 is filled between the first portion 110a and the second portion 110b. The dielectric material 112 may be the same material as that of the second dielectric layer 104; or, in an embodiment where the second dielectric layer 104 is a composite material layer, the dielectric material 112 may be the same material as that of the upper dielectric layer 110b. The same material as the material, such as silicon dioxide. The dielectric material 112 may be formed by chemical vapor deposition, and it may be filled to cover the first portion 110a and the second portion 110b.

Referring to FIG. 1I, then, a planarization process is performed to remove excess dielectric material 112, exposing the first portion 110a and the second portion 110b, which respectively become metal wires 111 electrically connected to the plug 102, Thus, the fabrication of the metal interconnection is completed. The planarization process is, for example, a chemical mechanical planarization (CMP) process.

Based on the manufacturing method described above, the present invention also provides an interconnection structure, which will be described below with reference to FIG. place.

Generally speaking, in the known method of making wires on the plugs, a ditch is firstly formed corresponding to each plug, and then each ditch is filled with wire material. Taking FIG. 1I as an example, a total of four trenches corresponding to one plug 102 are formed, and then the trenches are filled with wire material. With the miniaturization of semiconductor devices, the distance between the plugs is getting closer and closer, and the allowable width of the trench is getting smaller and smaller. When a small-sized trench is filled with a conductive material, voids or seams may be generated inside the final plug due to the limited gap-filling capability of the conductive material. These defects increase the resistance of the plug and may trap process gases and by-products such as WF ₃ , H ₂ , and HF, which can then diffuse out and cause metal corrosion, component damage, and reduced wafer reliability issues . The foregoing problems are particularly evident when the trench width is less than 40 nm.

On the contrary, the method adopted by the present invention is not to form a trench corresponding to a single plug, but to form a trench corresponding to two plugs, and then form a metal layer on the sidewall of the trench as a wire. As a result, the width of the trench is greatly increased. Taking FIG. 1I as an example, the width of the trench can be increased from approximately equal to the width of the plugs 102 to approximately equal to the distance between two plugs 102 . This largely addresses the limited gap-filling capability of the material.

In addition, looking at any plug 102 and its corresponding metal wire 111 in FIG. 1I, it can be found that on the opposite sides of the metal wire 111, only one side has a barrier layer between the second dielectric layer 104. 108 , there is no barrier layer 108 between the other side and the second dielectric layer 104 . Taking the leftmost metal wire 111 as an example, there is a barrier layer 108 between its left side and the second dielectric layer 104 , and there is no barrier layer 108 between its right side and the second dielectric layer 104 . Of course, this is a unique structure derived from the special process method of the present invention. Although on the side without the barrier layer 108, the contact between the metal wire 111 and the dielectric material 112 may be slightly poorer, but this will not affect the overall structural stability of the device. Moreover, since the metal wire 111 does not have a barrier layer 108 with poor conductivity on one side, the metal wire 111 of the present invention can have a higher conductivity than the known metal wire with barrier layers on both sides. ability to further improve component performance.

To sum up, the present invention provides an interconnect structure and a manufacturing method thereof, which can solve the problem of voids or gaps formed inside the wire due to the poor gap filling ability of the wire material, and can improve the conductivity of the wire. ability.

Although the present invention has been described above with examples, they are not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1. A method for making an internal connection, comprising: providing a substrate on which a first dielectric layer has been formed and two plugs have been formed in the first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench exposing the two plugs in the second dielectric layer; and A metal wire is respectively formed on each of the plugs. 2. The method for fabricating an interconnect as claimed in claim 1, wherein the extending direction of the trench is perpendicular to the connecting direction of the two plugs. 3. The method for manufacturing an interconnection wire as claimed in claim 1, wherein the method for forming a metal wire on each of the plugs respectively comprises: conformally forming a metal layer on the substrate; and The metal layer on the second dielectric layer and the metal layer between the two plugs are removed. 4. The method for manufacturing an interconnection wire as claimed in claim 1, wherein the method for forming a metal wire on each of the plugs respectively comprises: A metal layer is formed in the trench, the metal layer includes a first portion and a second portion formed on opposite side walls of the trench, and a third portion connecting the first portion and the second portion and formed at the bottom of the trench part; and Remove that third part. 5. The method of manufacturing an interconnection as claimed in claim 4, wherein after removing the third portion, the first portion forms a metal wire electrically connected to one of the two plugs, the The second part forms another metal wire electrically connected to the other of the two plugs. 6. The manufacturing method of interconnection as claimed in claim 4, further comprising: After removing the third portion, a dielectric material is filled between the first portion and the second portion. 7. The method for fabricating an interconnect as claimed in claim 1, wherein before forming a metal wire on each of the plugs, the fabricating method further comprises conformally forming a barrier layer on the substrate. 8. The method of fabricating an interconnect as claimed in claim 7, wherein the fabricating method further comprises removing the barrier layer on the second dielectric layer and the barrier layer between the two plugs. barrier layer. 9. The method for fabricating an interconnection as claimed in claim 1, wherein the second dielectric layer is a composite dielectric layer comprising two different dielectric materials. 10. An interconnection structure, comprising: a first dielectric layer; a second dielectric layer configured on the first dielectric layer; a plug disposed in the first dielectric layer and extending to the second dielectric layer; and A wire disposed in the second dielectric layer and located on the plug, characterized in that; The wire has two opposite sides, and a barrier layer is arranged between one side of the wire and the second dielectric layer, and there is no barrier layer between the other side of the wire and the second dielectric layer.