CN104576564A - Wafer level chip size packaging structure and manufacturing process thereof - Google Patents
Wafer level chip size packaging structure and manufacturing process thereof Download PDFInfo
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- CN104576564A CN104576564A CN201510038920.7A CN201510038920A CN104576564A CN 104576564 A CN104576564 A CN 104576564A CN 201510038920 A CN201510038920 A CN 201510038920A CN 104576564 A CN104576564 A CN 104576564A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000004806 packaging method and process Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 142
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 81
- 239000011241 protective layer Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 12
- 239000000203 mixture Substances 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 230000003064 anti-oxidating effect Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 3
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 11
- 238000003466 welding Methods 0.000 abstract 4
- 230000005611 electricity Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000006872 improvement Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a wafer level chip size packaging structure and a manufacturing process thereof. Firstly, a protective layer of certain thickness or a combination of the protective layer and a metal layer is laid on the front side of a wafer welding pad, then a first opening is formed in the back side of a wafer, and an insulating layer is laid in the first opening; secondly, a second opening is formed in the insulating layer at the bottom of the first opening, and finally metal wire arrangement layers are laid I the insulating layer and the second opening, and electricity of the wafer welding pad on the front side is led to the back side of the wafer. The protective layer of certain thickness or the combination of the protective layer and the metal layer is laid on the front side of the wafer welding pad, so that packaging strength of a chip is improved, the reliability problem caused by the fact that the second opening easily penetrates through the welding pad is avoided, meanwhile the difficulty of the process is reduced, a process window is added, and the reliability of the chip is improved.
Description
Technical field
The present invention relates to a kind of semiconductor package, specifically relate to a kind of wafer level chip scale package structure and manufacture craft thereof.
Background technology
Crystal wafer chip dimension encapsulation product is widely used in the product of portability, digitlization, high frequency and multifunction, as notebook computer, mobile phone, digital camera, video camera, audio-visual equipment etc.
At present, there is the general structure of the wafer of at least one chip unit 1 as shown in Figure 1, chip unit 1 comprises substrate 101, the front of substrate has element region 103, dielectric layer 102 and the weld pad 104 being positioned at element region 103 periphery, weld pad 104 electrical connecting element district 103, and weld pad is positioned at dielectric layer, weld pad is the front of weld pad towards the side of wafer frontside, weld pad is the back side of weld pad towards the side of substrate, the usual partial denudation in front of weld pad is in air, dielectric layer is had to be separated by between the back side of weld pad and substrate, this wafer is when the TSV encapsulation carrying out crystal wafer chip dimension, usual needs form the first opening at the back side of substrate, insulating barrier is equipped with in the first opening, then, the insulating barrier of the first open bottom forms the second opening by laser residence technique, finally, metal wiring layer and overcoat etc. is laid in insulating barrier and the second opening, but, when forming the second opening by laser residence technique, require that weld pad just exposes by the bottom of the second opening, can not weld pad be penetrated, and in the process of formation second opening, weld pad is easy to punch, if and penetrate weld pad, when follow-up laying metal wiring layer, have metal residual in the second opening part, the reliability of impact encapsulation, therefore, this chip-packaging structure and manufacture craft thereof, exist that packaging technology is harsher, technology difficulty be comparatively large, the integrity problem of the narrower and encapsulation of process window.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of wafer level chip scale package structure and manufacture craft thereof, effectively can reduce technology difficulty, increases process window, improves the reliability of chip package.
Technical scheme of the present invention is achieved in that
A kind of wafer level chip scale package structure, comprise the wafer with at least one chip unit, described chip unit comprises substrate and is positioned at the dielectric layer in front of described substrate, the front of described substrate is provided with element region, described element region periphery is provided with some weld pads, and described weld pad is positioned at described dielectric layer, the weld pad of described element region and its periphery is electrical connected, and described dielectric layer has the 3rd opening in weld pad front described in expose portion; The position that the back side of described substrate is relative with each described weld pad is formed with the first opening, the back side of described substrate and the inwall of described first opening are formed with insulating barrier, the insulating barrier of described first open bottom is formed with the second opening, and described second opening exposes the back side of described weld pad; Reinforced layer is formed in described 3rd opening.
As a further improvement on the present invention, described reinforced layer forms primarily of one deck overcoat composition or primarily of one deck overcoat and layer of metal layer, and described metal level is between the front of described weld pad and described overcoat.
As a further improvement on the present invention, when described reinforced layer is primarily of one deck overcoat and layer of metal layer composition, the material of described metal level is the alloy of titanium or aluminium or copper or nickel or cobalt or silver or its combination; The material of described overcoat be gold or other there is the material of anti-oxidation function.
As a further improvement on the present invention, when described reinforced layer is made up of one deck overcoat, the height of described overcoat is lower than described dielectric layer or concordant with described dielectric layer or higher than described dielectric layer.
As a further improvement on the present invention, when described reinforced layer is primarily of one deck overcoat and layer of metal layer composition, the total height of described metal level and described overcoat is lower than described dielectric layer or concordant with described dielectric layer or higher than described dielectric layer.
As a further improvement on the present invention, when described reinforced layer forms primarily of one deck overcoat, the bottom of described second opening just exposes the back side of described weld pad or penetrates described weld pad or punch described weld pad.
As a further improvement on the present invention, when described reinforced layer is primarily of one deck overcoat and layer of metal layer composition, the bottom of described second opening just exposes the back side of described weld pad or penetrates described weld pad or punch described weld pad or penetrate described metal level or punch described metal level.
As a further improvement on the present invention, be equipped with metal wiring layer on described insulating barrier He in described second opening, described metal wiring layer and described weld pad are electrically connected; Described metal wiring layer is equipped with protective layer.
A manufacture craft for wafer level chip scale package structure, comprises the steps:
A, prepare a wafer with at least one chip unit, described chip unit comprises substrate and is positioned at the dielectric layer in front of described substrate, the front of described substrate is provided with element region, described element region periphery is provided with some weld pads, and described weld pad is positioned at described dielectric layer, the weld pad of described element region and its periphery is electrical connected, and described dielectric layer has the 3rd opening in weld pad front described in expose portion;
B, in described 3rd opening in each described weld pad front, lay reinforced layer;
C, carry out thinning to the back side of described wafer;
D, position relative with the weld pad of each chip unit on the back side of described wafer carve the first opening, and the bottom-exposed of described first opening goes out described dielectric layer;
E, the dielectric layer between corresponding with it for the first open bottom weld pad to be removed;
F, step e formed the back side of described wafer and the inwall of each described first opening on lay one deck insulating barrier;
G, on the insulating barrier of described first open bottom, form the second opening, the bottom-exposed of described second opening goes out the weld pad of its correspondence.
As a further improvement on the present invention, further comprising the steps of:
H, step g formed described insulating barrier on and lay layer of metal wiring layer in described second opening, make described metal wiring layer be electrically connected the weld pad of its correspondence;
I, step H-shaped become metal wiring layer lay layer protective layer outward;
Reserved 4th opening on j, the protective layer that formed in step I, as the window that metal wiring layer is connected with external devices;
K, step j formed part or all of 4th opening part plant soldered ball (9);
L, to step k formed wafer cut, form single wafer level chip scale package structure.
The invention has the beneficial effects as follows: the invention provides a kind of wafer level chip scale package structure and manufacture craft thereof, first, the front of wafer weld pad is laid the combination of certain thickness overcoat or overcoat and metal level, then, form the first opening at wafer rear, in the first opening, lay insulating barrier, then, the insulating barrier of the first open bottom is formed the second opening, finally, metal wiring layer is laid in insulating barrier and the second opening, wafer frontside weld pad electrically exported to wafer rear, this encapsulating structure and manufacture craft thereof, in the process of formation second opening, because the combination of certain thickness overcoat or overcoat and metal level has been laid in the front in advance at weld pad, enhance the intensity of weld pad, weld pad is made to be not easy to be penetrated, and due to the existence of metal level, even if weld pad is penetrated, when follow-up laying metal wiring layer, metal residual is not had in the second opening part yet, therefore, because weld pad penetrates the integrity problem caused when can avoid the formation of the second opening, and can technology difficulty be reduced, increase process window.
Accompanying drawing explanation
Fig. 1 is the encapsulating structure schematic diagram of prior art;
Fig. 2 is the encapsulating structure schematic diagram of the embodiment of the present invention 1;
Fig. 3 is the encapsulating structure schematic diagram of the embodiment of the present invention 2;
Fig. 4 is A place structure for amplifying schematic diagram in Fig. 3;
Fig. 5 is the structural representation that in the embodiment of the present invention 2, second opening exposes the weld pad back side just;
Fig. 6 is the structural representation of the second opening just penetrating metal layer in the embodiment of the present invention 2;
Fig. 7 is the structural representation of total height lower than dielectric layer of metal level and overcoat in the embodiment of the present invention 2;
Fig. 8 is the structural representation of total height higher than dielectric layer of metal level and overcoat in the embodiment of the present invention 2;
The structural representation of Fig. 9 to be the shape of the first opening in the embodiment of the present invention 2 be straight hole of upper and lower equal diameters.
By reference to the accompanying drawings, make the following instructions:
1---chip unit 101---substrate
102---dielectric layer 103---element region
104---weld pad 105---the 3rd opening
2---metal level 3---overcoat
4---insulating barrier 5---metal wiring layer
6---first opening 7---second opening
8---protective layer 9---soldered ball
Embodiment
Embodiment 1
As shown in Figure 2, a kind of wafer level chip scale package structure, comprise the wafer with at least one chip unit 1, described chip unit 1 comprises substrate 101 and is positioned at the dielectric layer 102 in front of described substrate 101, the front of described substrate 101 is provided with element region 103, described element region 103 periphery is provided with some weld pads 104, and described weld pad 104 is positioned at described dielectric layer 102, described element region 103 is electrical connected with the weld pad 104 of its periphery, described dielectric layer 102 has the 3rd opening 105 in weld pad 104 front described in expose portion; The position that the back side of described substrate 101 is relative with each described weld pad 104 is formed with the first opening 6, the back side of described substrate 101 and the inwall of described first opening 6 are formed with insulating barrier 4, insulating barrier 4 bottom described first opening 6 is formed with the second opening 7, and described second opening 7 exposes the back side of described weld pad 104; Be equipped with metal wiring layer 5 on described insulating barrier 4 He in described second opening 7, described metal wiring layer 5 is electrically connected with described weld pad 104; Described metal wiring layer 5 is equipped with protective layer 8; Be formed with reinforced layer in described 3rd opening 105, and described reinforced layer forms primarily of one deck overcoat 3.
Wherein, optionally, the material of overcoat 3 be gold or other there is the material of anti-oxidation function; Optionally, the bottom of described second opening 7 just exposes the back side of described weld pad 104 or penetrates described weld pad 104 or punch described weld pad 104.Optionally, the material of dielectric layer 102 is silicon dioxide, silicon nitride, silicon oxynitride or aforesaid composition.Optionally, element region 103 is can the core parts region of practical function on wafer, core parts as the sensing elements such as light, heat, power, MEMS (micro electro mechanical system), integrated circuit electronic element etc., but not as limit.Optionally, weld pad 104 is the conductive pad be connected with the extraneous signal of telecommunication, as the I/O port of element region 103 signal of telecommunication.
In said structure, in the process of formation second opening 7, owing to having laid overcoat 3 in the front of weld pad 104 in advance, be equivalent to the intensity enhancing weld pad 104, weld pad 104 is made to be not easy by laser penetration, and due to the existence of overcoat 3, even if weld pad 104 is by laser penetration, when follow-up laying metal wiring layer 5, metal residual is not had in the second opening 7 place yet, therefore, by weld pad 104 front in the 3rd opening 105 forms overcoat 3, can avoid when formation the second opening 7 because weld pad 104 penetrates the integrity problem caused.And due to the existence of overcoat 3, without the need to considering whether laser punches weld pad 104, namely the bottom of the second opening 7 can expose the back side of described weld pad 104 just, can also penetrate described weld pad 104 or punch described weld pad 104; Therefore, by weld pad 104 front in the 3rd opening 105 forms overcoat 3, can technology difficulty be reduced, make packaging technology no longer harsh.In addition, based on the reduction of technology difficulty, when removing dielectric layer 102, process window can be increased by Controlling Technology condition.
Embodiment 2
As shown in Figure 3, a kind of wafer level chip scale package structure, comprise the wafer with at least one chip unit 1, described chip unit 1 comprises substrate 101 and is positioned at the dielectric layer 102 in front of described substrate 101, the front of described substrate 101 is provided with element region 103, described element region 103 periphery is provided with some weld pads 104, and described weld pad 104 is positioned at described dielectric layer 102, described element region 103 is electrical connected with the weld pad 104 of its periphery, described dielectric layer 102 has the 3rd opening 105 in weld pad 104 front described in expose portion; The position that the back side of described substrate 101 is relative with each described weld pad 104 is formed with the first opening 6, the back side of described substrate 101 and the inwall of described first opening 6 are formed with insulating barrier 4, insulating barrier 4 bottom described first opening 6 is formed with the second opening 7, and described second opening 7 exposes the back side of described weld pad 104; Be equipped with metal wiring layer 5 on described insulating barrier 4 He in described second opening 7, described metal wiring layer 5 is electrically connected with described weld pad 104; Described metal wiring layer 5 is equipped with protective layer 8; Be formed with reinforced layer in described 3rd opening 105, and described reinforced layer is made up of one deck overcoat 3 and layer of metal layer 2, described metal level 2 is between the front and described overcoat 3 of described weld pad 104.Optionally, the material of described metal level 2 is the alloy of titanium or aluminium or copper or nickel or cobalt or silver or its combination; The material of described overcoat 3 be gold or other there is the material of anti-oxidation function.
Optionally, the total height of described metal level 2 and described overcoat 3 is lower than described dielectric layer 102 or concordant with described dielectric layer 102 or higher than described dielectric layer 102.See Fig. 3, in this encapsulating structure, described metal level 2 is concordant with described dielectric layer 102 with the total height of described overcoat 3; See Fig. 7, in this encapsulating structure, the total height of described metal level 2 and described overcoat 3 is lower than described dielectric layer 102; See Fig. 8, in this encapsulating structure, the total height of described metal level 2 and described overcoat 3 is higher than described dielectric layer 102.
Optionally, the bottom of described second opening 7 just exposes the back side of described weld pad 104 or penetrates described weld pad 104 or punch described weld pad 104 or penetrate described metal level 2 or punch described metal level 2.See Fig. 3, in this encapsulating structure, the second opening 7 has just penetrated weld pad 104, but the metal level 2, Fig. 4 not entering laying is A place structure for amplifying schematic diagram in Fig. 3; See Fig. 5, in this encapsulating structure, the second opening 7 exposes the back side of described weld pad 104 just; See Fig. 6, the second opening 7 just penetrating metal layer 2 in this encapsulating structure, but do not enter the overcoat 3 of laying.
Optionally, the shape of described first opening 6 is straight hole or the upper and lower diameter inclined hole not etc. of upper and lower equal diameters.See Fig. 3, Fig. 5, Fig. 6, Fig. 7 and Fig. 8, in these encapsulating structures, the shape of the first opening 6 is the inclined hole that upper and lower diameter does not wait; See Fig. 9, in this encapsulating structure, the shape of the first opening 6 is the straight hole of upper and lower equal diameters.
In the above-mentioned encapsulating structure of the present invention, by weld pad 104 front in the 3rd opening 105 first being formed layer of metal layer 2 then at formation one deck overcoat 3, because metal has good intensity, therefore, in the process of formation second opening 7, the intensity of weld pad 104 can be strengthened, make weld pad 104 can not be easy to be penetrated, avoid when formation the second opening 7 because weld pad 104 penetrates the integrity problem caused.And due to the existence of metal level 2 and overcoat 3, without the need to considering whether laser punches weld pad 104, namely the bottom of the second opening 7 can expose the back side of described weld pad 104 just, can also penetrate described weld pad 104 or punch described weld pad 104, even can penetrate metal level 2 or punch metal level 2; Therefore, by weld pad 104 front in the 3rd opening 105 forms metal level 2 and overcoat 3, can technology difficulty be reduced, make packaging technology not in harshness.In addition, based on the reduction of technology difficulty, when removing dielectric layer 102, process window can be increased by Controlling Technology condition.
A manufacture craft for wafer level chip scale package structure, comprises the steps:
A, prepare a wafer with at least one chip unit 1, described chip unit 1 comprises substrate 101 and is positioned at the dielectric layer 102 in front of described substrate 101, the front of described substrate 101 is provided with element region 103, described element region 103 periphery is provided with some weld pads 104, and described weld pad 104 is positioned at described dielectric layer 102, described element region 103 is electrical connected with the weld pad 104 of its periphery, described dielectric layer 102 has the 3rd opening 105 in weld pad 104 front described in expose portion;
B, in described 3rd opening 105 in each described weld pad 104 front lay reinforced layer;
C, carry out thinning to the back side of described wafer;
D, position relative with the weld pad 104 of each chip unit 1 on the back side of described wafer carve the first opening 6, and the bottom-exposed of described first opening 6 goes out described dielectric layer 102;
E, the dielectric layer 102 between weld pad 104 corresponding with it bottom the first opening 6 to be removed;
F, step e formed the back side of described wafer and the inwall of each described first opening 6 on lay one deck insulating barrier 4;
G, insulating barrier 4 bottom described first opening 6 form the second opening 7, and the bottom-exposed of described second opening 7 goes out the weld pad 104 of its correspondence;
H, laying layer of metal wiring layer 5 on the described insulating barrier 4 that step g is formed and described second opening 7 in, make described metal wiring layer 5 be electrically connected the weld pad 104 of its correspondence;
I, the metal wiring layer 5 outer laying layer protective layer 8 become in step H-shaped;
J, the 4th opening that reserved metal wiring layer 5 is connected with external devices on the protective layer 8 of step I formation;
K, step j formed part or all of 4th opening part plant soldered ball 9;
L, to step k formed wafer cut, form single wafer level chip scale package structure.
Preferably, described reinforced layer forms primarily of one deck overcoat 3 and layer of metal layer 2, and described metal level 2 is between the front and described overcoat 3 of described weld pad 104.
Optionally, the method for the formation of described metal level 2 is chemical plating or plating or physical vapour deposition (PVD).
Above embodiment is with reference to accompanying drawing, to a preferred embodiment of the present invention will be described in detail.Those skilled in the art by carrying out amendment on various forms or change to above-described embodiment, but when not deviating from essence of the present invention, drops within protection scope of the present invention.
Claims (10)
1. a wafer level chip scale package structure, it is characterized in that: comprise the wafer with at least one chip unit (1), described chip unit comprises substrate (101) and is positioned at the dielectric layer (102) in front of described substrate, the front of described substrate is provided with element region (103), described element region periphery is provided with some weld pads (104), and described weld pad is positioned at described dielectric layer, the weld pad of described element region and its periphery is electrical connected, and described dielectric layer has the 3rd opening (105) in weld pad front described in expose portion; The position that the back side of described substrate is relative with each described weld pad is formed with the first opening (6), the back side of described substrate and the inwall of described first opening are formed with insulating barrier (4), the insulating barrier of described first open bottom is formed with the second opening (7), described second opening exposes the back side of described weld pad; Reinforced layer is formed in described 3rd opening.
2. wafer level chip scale package structure according to claim 1, it is characterized in that: described reinforced layer is primarily of one deck overcoat (3) composition or primarily of one deck overcoat (3) and layer of metal layer (2) composition, described metal level is between the front of described weld pad and described overcoat.
3. wafer level chip scale package structure according to claim 2, is characterized in that: when described reinforced layer is primarily of one deck overcoat and layer of metal layer composition, the material of described metal level is the alloy of titanium or aluminium or copper or nickel or cobalt or silver or its combination; The material of described overcoat be gold or other there is the material of anti-oxidation function.
4. wafer level chip scale package structure according to claim 2, is characterized in that: when described reinforced layer is made up of one deck overcoat, and the height of described overcoat is lower than described dielectric layer or concordant with described dielectric layer or higher than described dielectric layer.
5. wafer level chip scale package structure according to claim 2, it is characterized in that: when described reinforced layer is primarily of one deck overcoat and layer of metal layer composition, the total height of described metal level and described overcoat is lower than described dielectric layer or concordant with described dielectric layer or higher than described dielectric layer.
6. wafer level chip scale package structure according to claim 2, is characterized in that: when described reinforced layer forms primarily of one deck overcoat, and the bottom of described second opening just exposes the back side of described weld pad or penetrates described weld pad or punch described weld pad.
7. wafer level chip scale package structure according to claim 2, it is characterized in that: when described reinforced layer is primarily of one deck overcoat and layer of metal layer composition, the bottom of described second opening just exposes the back side of described weld pad or penetrates described weld pad or punch described weld pad or penetrate described metal level or punch described metal level.
8. wafer level chip scale package structure according to claim 1, is characterized in that: be equipped with metal wiring layer (5) on described insulating barrier He in described second opening, described metal wiring layer and described weld pad are electrically connected; Described metal wiring layer is equipped with protective layer (8).
9. a manufacture craft for wafer level chip scale package structure, is characterized in that, comprises the steps:
A, prepare a wafer with at least one chip unit, described chip unit comprises substrate and is positioned at the dielectric layer in front of described substrate, the front of described substrate is provided with element region, described element region periphery is provided with some weld pads, and described weld pad is positioned at described dielectric layer, the weld pad of described element region and its periphery is electrical connected, and described dielectric layer has the 3rd opening in weld pad front described in expose portion;
B, in described 3rd opening in each described weld pad front, lay reinforced layer;
C, carry out thinning to the back side of described wafer;
D, position relative with the weld pad of each chip unit on the back side of described wafer carve the first opening, and the bottom-exposed of described first opening goes out described dielectric layer;
E, the dielectric layer between corresponding with it for the first open bottom weld pad to be removed;
F, step e formed the back side of described wafer and the inwall of each described first opening on lay one deck insulating barrier;
G, on the insulating barrier of described first open bottom, form the second opening, the bottom-exposed of described second opening goes out the weld pad of its correspondence.
10. the manufacture craft of wafer level chip scale package structure according to claim 9, is characterized in that: further comprising the steps of:
H, step g formed described insulating barrier on and lay layer of metal wiring layer in described second opening, make described metal wiring layer be electrically connected the weld pad of its correspondence;
I, step H-shaped become metal wiring layer lay layer protective layer outward;
Reserved 4th opening on j, the protective layer that formed in step I, as the window that metal wiring layer is connected with external devices;
K, step j formed part or all of 4th opening part plant soldered ball (9);
L, to step k formed wafer cut, form single wafer level chip scale package structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510038920.7A CN104576564A (en) | 2015-01-26 | 2015-01-26 | Wafer level chip size packaging structure and manufacturing process thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510038920.7A CN104576564A (en) | 2015-01-26 | 2015-01-26 | Wafer level chip size packaging structure and manufacturing process thereof |
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| CN104576564A true CN104576564A (en) | 2015-04-29 |
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| CN201510038920.7A Pending CN104576564A (en) | 2015-01-26 | 2015-01-26 | Wafer level chip size packaging structure and manufacturing process thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN106129031A (en) * | 2016-07-07 | 2016-11-16 | 华天科技（昆山）电子有限公司 | Chip-packaging structure and method for packing thereof |
| CN106129031B (en) * | 2016-07-07 | 2020-05-22 | 华天科技（昆山）电子有限公司 | Chip packaging structure and packaging method thereof |
| CN106229272A (en) * | 2016-08-23 | 2016-12-14 | 苏州科阳光电科技有限公司 | Wafer stage chip encapsulation method and structure |
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| CN110660765A (en) * | 2019-09-23 | 2020-01-07 | 上海朕芯微电子科技有限公司 | CSP (chip scale package) packaging structure and CSP packaging method for triode separator |
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| CN110634900A (en) * | 2019-09-27 | 2019-12-31 | 华天科技（昆山）电子有限公司 | Wafer level packaging method and packaging structure of image sensor with FSI structure |
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