CN104576705B - A kind of array base palte and preparation method, display device - Google Patents

Abstract

The invention discloses a kind of array base palte and preparation method, display device, under conditions of existing process difficulty is not increased, to reduce the voltage drop between array base palte viewing area and non-display area, improves display quality.The array base palte, including underlay substrate, underlay substrate is divided into viewing area and non-display area, thin film transistor (TFT) is provided with underlay substrate, flatness layer is provided with thin film transistor (TFT), organic luminous layer is provided with flatness layer, array base palte also includes the Top electrode being arranged on organic luminous layer, and wherein at least part is more than the thickness of the Top electrode positioned at viewing area positioned at the thickness of the Top electrode of non-display area.

Description

Array substrate, manufacturing method, and display device

technical field

The present invention relates to the technical field of organic light-emitting display, in particular to an array substrate, a manufacturing method, and a display device.

Background technique

In the prior art, a display technology using thin-film transistors as control elements and Organic Light Emitting Diode (OLED) as a light-emitting medium has been widely used due to its advantages of high definition, wide viewing angle, and easy realization of curved and flexible displays.

Contents of the invention

Embodiments of the present invention provide an array substrate, a manufacturing method, and a display device, which are used to reduce the voltage drop between the display area and the non-display area of the array substrate and improve display quality without increasing the difficulty of the existing process.

An array substrate provided by an embodiment of the present invention includes a base substrate, the base substrate includes a display area and a non-display area, and a thin film transistor, an organic light-emitting layer, and an organic light-emitting layer are arranged on the base substrate. The upper electrode above the layer, wherein at least part of the upper electrode located in the non-display area has a thickness greater than the thickness of the upper electrode located in the display area.

In the array substrate provided by the embodiments of the present invention, since the array substrate includes an upper electrode disposed on the organic light-emitting layer, at least a part of the thickness of the upper electrode located in the non-display area is greater than that of the upper electrode located in the display area. The thickness of the upper electrode layer, that is, the embodiment of the present invention uses partitions to set the thickness of the upper electrode layer, while ensuring the light transmittance of the display area, effectively reducing the resistivity of the upper electrode in the non-display area, and reducing the poor contact of the electrical contact area Therefore, the uniformity of the display and the production yield of the product can be improved.

Preferably, the thin film transistor includes: a semiconductor active layer, a gate insulating layer, a gate, an insulating layer, a source and a drain sequentially located on the substrate; or,

The thin film transistor includes: a gate, a gate insulating layer, a semiconductor active layer, a source and a drain which are sequentially located on the substrate.

In this way, the thin film transistor can adopt a top-gate structure or a bottom-gate structure, which is more flexible and convenient in actual production.

Preferably, a buffer layer is provided between the base substrate and the thin film transistor.

In this way, the arrangement of the buffer layer can function as a flat base substrate, and at the same time prevent impurity atoms in the base substrate from diffusing into the thin film transistor.

Preferably, it also includes a flat layer and a pixel electrode arranged on the base substrate, the flat layer is located between the thin film transistor and the organic light-emitting layer, the pixel electrode is located on the flat layer, and passes through the flat layer The via hole on the layer is connected to the exposed source or drain of the thin film transistor, and the organic light emitting layer is located on the pixel electrode.

Preferably, an auxiliary electrode is also included, the auxiliary electrode is located in the non-display area of the base substrate, and is located in the same layer as the pixel electrode, the upper electrode is located on the auxiliary electrode and is electrically connected to the auxiliary electrode, The thickness of the upper electrode on the auxiliary electrode is greater than the thickness of the upper electrode on the pixel electrode.

In this way, the arrangement of the auxiliary electrode can further reduce the resistivity of the upper electrode.

Preferably, the upper electrode is an anode, or the upper electrode is a cathode.

In this way, both positive voltage and negative voltage can be applied to the upper electrode, which is more convenient and simple in the actual process.

Preferably, the material of the upper electrode is a single-layer film of indium tin oxide or indium zinc oxide, or a composite film of indium tin oxide and indium zinc oxide.

In this way, the material selection of the upper electrode is more convenient and simple.

An embodiment of the present invention also provides a display device, which includes the above-mentioned array substrate.

Since the display device of the embodiment of the present invention includes the above-mentioned array substrate, the display uniformity of the display device of the embodiment of the present invention is better.

The embodiment of the present invention also provides a method for fabricating an array substrate, including fabricating a thin film transistor, fabricating an organic light-emitting layer, and fabricating an upper electrode. The thickness of the upper electrode in the non-display area is greater than the thickness of the upper electrode in the display area of the array substrate.

According to the manufacturing method of the array substrate provided by the embodiment of the present invention, since the thickness of the upper electrode obtained by the manufacturing method is at least partially located in the non-display area of the array substrate is greater than that located in the display area of the array substrate, the upper electrode obtained in the embodiment of the present invention In the case of ensuring the light transmittance of the display area, the resistivity of the upper electrode in the non-display area can be effectively reduced, and the occurrence of poor contact in the electrical contact area can be reduced, thereby improving the display uniformity of the array substrate and the production of products. yield.

Preferably, the patterning process uses a half-tone mask or a gray-tone mask to make the upper electrode, specifically including:

forming a transparent conductive film on the organic light-emitting layer;

Form a photoresist on the transparent conductive film, expose and develop through a half-tone mask or a gray tone mask to form a photoresist full coverage area, a photoresist partial coverage area and a no photoresist coverage area , wherein, the photoresist full coverage area corresponds to the non-display area of the array substrate, and the photoresist partial coverage area corresponds to the display area of the array substrate;

By etching, removing the transparent conductive film in the non-photoresist coverage area, and removing the photoresist in the photoresist partial coverage area, exposing the transparent conductive film in the photoresist partial coverage area;

Removing the exposed part of the thickness of the transparent conductive film by etching to form an upper electrode located in the display area of the array substrate;

The remaining photoresist is removed to form an upper electrode located in the non-display area of the array substrate, and the thickness of the upper electrode located in the non-display area is greater than that of the upper electrode located in the display area.

In this way, it is more convenient and simple to use a halftone mask or a gray tone mask to make the upper electrode in the actual manufacturing process.

Description of drawings

1 is a schematic cross-sectional structure diagram of an array substrate;

2 is a schematic cross-sectional structure diagram of another array substrate that reduces the resistivity of the upper electrode;

3 is a schematic cross-sectional structure diagram of another array substrate that reduces the resistivity of the upper electrode;

4 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present invention;

FIG. 5 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;

6 is a schematic cross-sectional structure diagram of an array substrate provided with auxiliary electrodes provided by an embodiment of the present invention;

FIG. 7 is a flow chart of a method for fabricating an upper electrode on an array substrate according to an embodiment of the present invention;

8 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present invention after depositing a transparent conductive film;

FIG. 9 is a schematic diagram of a cross-sectional structure of the transparent conductive film deposited in FIG. 8 provided by an embodiment of the present invention when a photolithography process is performed.

Detailed ways

As shown in Figure 1, the main structure of the array substrate includes: a base substrate 10, a buffer layer 11 disposed on the base substrate 10, a semiconductor active layer 12 disposed on the buffer layer 11, a semiconductor active layer 12 disposed on the The gate insulating layer 13 on the gate insulating layer 13, the gate 14 disposed on the gate insulating layer 13, the insulating layer 15 disposed on the gate 14, the source 16 and the drain 17 disposed on the insulating layer 15, disposed on the source The flat layer 18 on the electrode 16 and the drain electrode 17, the pixel electrode 19 arranged on the flat layer 18, the organic light-emitting limiting layer 110 arranged on the pixel electrode 19, the organic light-emitting layer 111 arranged on the organic light-emitting limiting layer 110, An upper electrode 112 disposed on the organic light emitting layer 111 .

In the prior art, in order to improve the light utilization efficiency of the organic light-emitting layer 111, the upper electrode 112 usually uses a transparent conductive material, and the transparent conductive material generally has a higher resistivity than a single conductive metal material; in addition, in order to improve the display brightness of the emission display , it is also necessary to increase the light transmittance of the transparent conductive material, and the increase of the light transmittance is usually realized by thinning the transparent conductive layer. The reduction of the thickness of the transparent conductive layer further increases its resistivity. In a large-size display, a large voltage drop will occur between the display area and the non-display area, which will affect the emission current injection of the light-emitting layer and cause display quality. deteriorating.

As shown in FIG. 2, in order to reduce the voltage drop between the display area and the non-display area of the array substrate, a layer of metal wiring layer 20 is added in the non-display area, and the metal wiring layer 20 is electrically connected with the upper electrode 112 to reduce the voltage drop between the display area and the non-display area. Small resistance, which in turn reduces the voltage drop between the display area and the non-display area. In addition, as shown in FIG. 3 , the resistance is reduced by connecting the conductive ink 30 to the upper electrode 112 , thereby reducing the voltage drop between the display area and the non-display area.

To sum up, there will be a large voltage drop between the display area and the non-display area of the array substrate, which will affect the light emission of the light-emitting layer and cause the display quality to deteriorate. At present, when reducing the voltage between the display area and the non-display area, it is necessary to The newly added conductive metal wiring layer and conductive ink increase the manufacturing process steps and increase the difficulty of the manufacturing process. At the same time, because the newly added conductive metal wiring layer will occupy the display area, the aperture ratio of the display is reduced, which is not conducive to high quality Production of display screens.

Embodiments of the present invention provide an array substrate, a manufacturing method, and a display device, which are used to reduce the voltage drop between the display area and the non-display area of the array substrate and improve display quality without increasing the difficulty of the existing process.

In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The array substrate provided by specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 4, the specific embodiment of the present invention provides an array substrate, including a base substrate 10, the base substrate 10 is divided into a display area 41 and a non-display area 42, and a thin film transistor 43 is arranged on the base substrate 10. The thin film transistor 43 is provided with an organic light-emitting limiting layer 110, and the organic light-emitting limiting layer 110 is provided with an organic light-emitting layer 111. The array substrate also includes an upper electrode 112 arranged on the organic light-emitting layer 111, at least part of which is located in the non-display area 42 The thickness of the upper electrode 112 is greater than the thickness of the upper electrode 112 located in the display area 41 . The upper electrode in the specific embodiment of the present invention can be used as the anode of the organic light-emitting diode, and can also be used as the cathode of the organic light-emitting diode, that is, in the actual process, either a positive voltage can be applied to the upper electrode, or a negative voltage can be applied to the upper electrode. Voltage. Preferably, the material of the upper electrode in the specific embodiment of the present invention is a single-layer film of indium tin oxide or indium zinc oxide, or a composite film of indium tin oxide and indium zinc oxide.

Preferably, in the specific embodiment of the present invention, a buffer layer is provided between the base substrate and the thin film transistor. The setting of the buffer layer can play the role of a flat base substrate, and at the same time can prevent impurity atoms in the base substrate from diffusing into the thin film transistor. middle.

The thin film transistor in the specific embodiment of the present invention may be a thin film transistor with a top gate structure, or a thin film transistor with a bottom gate structure, and of course a thin film transistor with other structures. The specific embodiment of the present invention is not limited to the specific structure of the thin film transistor Make a limit.

Preferably, the thin film transistor in the specific embodiment of the present invention includes: a semiconductor active layer, a gate insulating layer, a gate, an insulating layer, a source and a drain sequentially located on the substrate; or, the specific embodiment of the present invention The thin film transistor in TFT includes: a gate, a gate insulating layer, a semiconductor active layer, a source and a drain which are sequentially located on a substrate.

Specifically, as shown in FIG. 4 , a thin film transistor 43 in a specific embodiment of the present invention includes a semiconductor active layer 12 on the base substrate 10, a gate insulating layer 13 on the semiconductor active layer 12, and a gate insulating layer 13 on the gate. A gate 14 on the insulating layer 13 , an insulating layer 15 on the gate 14 , a source 16 and a drain 17 on the insulating layer 15 . In the specific embodiment of the present invention, when the layer in contact with the bottom surface of the organic light-emitting layer 111 is used as the cathode, if the work function of the material of the source electrode 16 is small, it can be directly used as the cathode layer, and the organic light-emitting layer 111 is directly connected to the source electrode 16. There is no need to make pixel electrodes, which makes the manufacturing process simpler. The organic light-emitting limiting layer 110 in the specific embodiment of the present invention functions to limit the position of the organic light-emitting layer 111 .

Specifically, as shown in FIG. 5 , the array substrate in the specific embodiment of the present invention further includes a pixel electrode 19 disposed on the planar layer 18 , and the pixel electrode 19 is exposed to the thin film transistor through a via hole etched on the planar layer 18 . The output source electrode 16 is connected, and the organic light emitting layer 111 is located on the pixel electrode 19 . The organic light-emitting layer 111 is induced to emit light by an electrical signal applied to the pixel electrode 19 and the upper electrode 112. When the upper electrode 112 is used as the cathode of the organic light emitting diode, the pixel electrode 19 is used as the anode of the organic light emitting diode, and the voltage between the pixel electrode 19 and the upper electrode 112 is controlled through a circuit structure such as a thin film transistor on the array substrate, thereby controlling the organic light emitting layer. 111 glow effects. In the specific embodiment of the present invention, the material of the upper electrode is a single-layer film of indium tin oxide or indium zinc oxide, or a composite film of indium tin oxide and indium zinc oxide. In the specific embodiment of the present invention, the upper electrode located in the non-display area 42 The thickness of 112 is greater than the thickness of the upper electrode 112 located in the display area 41 . Therefore, in the specific embodiment of the present invention, the upper electrode 112 is arranged in partitions, and the film thickness of the upper electrode 112 in the display light-transmitting area in contact with the organic light-emitting layer 111 is relatively thin to improve the light transmittance; in the non-display area The film thickness of the upper electrode 112 is thicker, so as to reduce the resistivity of the upper electrode, and improve the display quality and product yield without increasing the difficulty of the existing process.

As shown in FIG. 6 , the array substrate in the specific embodiment of the present invention further includes an auxiliary electrode 60 located on the same layer as the pixel electrode 19, the auxiliary electrode 60 is located on the non-display area 42 of the base substrate 10, and the upper electrode 112 is located on the The auxiliary electrode 60 is electrically connected to the auxiliary electrode 60 , and the thickness of the upper electrode 112 located on the auxiliary electrode 60 is greater than the thickness of the upper electrode 112 located above the pixel electrode 19 . The setting of the auxiliary electrode 60 can further reduce the resistivity of the upper electrode 112 in the non-display area. Since the film thickness of the upper electrode 112 in the non-display area is thicker, when the upper electrode 112 is electrically connected with the auxiliary electrode 60, it is not easy to cause due to The upper electrode breakage caused by the deeper contact hole and the thinner upper electrode 112 can reduce the poor contact of electrical properties and improve the product yield. Certainly, the auxiliary electrode 60 in the specific embodiment of the present invention can also adopt the same design method as the metal wiring layer 20 in FIG. When deposited on a thicker auxiliary electrode, it is not easy to break in the edge area of the auxiliary electrode, thereby reducing the poor contact of electrical properties.

A specific embodiment of the present invention also provides a display device including the above-mentioned array substrate, and the display device may be an OLED display device or the like.

A specific embodiment of the present invention also provides a method for manufacturing an array substrate, including manufacturing a thin film transistor, a flat layer, an organic light-emitting layer, and an upper electrode, wherein at least part of the array substrate is located in the non-display area. The thickness of the upper electrode is greater than the thickness of the upper electrode located in the display area of the array substrate.

Preferably, as shown in Figure 7, the specific embodiment of the present invention uses a half-tone mask or a gray-tone mask to make the upper electrode, specifically including:

S701, forming (for example, by depositing) a transparent conductive film on the organic light-emitting layer;

S702. Form (for example, by coating) a photoresist on the transparent conductive film, and perform exposure and development through a mask (for example, a halftone mask or a gray tone mask) to form a complete photoresist. a coverage area, a photoresist partial coverage area, and a photoresist-free coverage area, wherein the photoresist full coverage area corresponds to the non-display area of the array substrate, and the photoresist partial coverage area corresponds to the display area of the array substrate;

S703. By etching, remove the transparent conductive film in the area not covered by the photoresist, and remove the photoresist in the partially covered area of the photoresist, exposing the transparent conductive film in the partially covered area of the photoresist;

S704, removing the exposed part of the thickness of the transparent conductive film by etching to form an upper electrode located in the display area of the array substrate;

S705 , removing the remaining photoresist to form an upper electrode located in the non-display area of the array substrate, the thickness of the upper electrode located in the non-display area is greater than the thickness of the upper electrode located in the display area.

The manufacturing method of the array substrate provided by the specific embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 8 , in a specific embodiment of the present invention, a buffer layer 11 is first fabricated on a base substrate 10. The base substrate 10 can be a glass substrate or a flexible substrate, and the specific manufacturing process of the buffer layer 11 is the same as that of the prior art. , which will not be repeated here. Then make semiconductor active layer 12 on buffer layer 11, semiconductor active layer 12 can be amorphous silicon film, also can be the polysilicon film that crystallization is made to amorphous silicon film, the specific manufacturing process of semiconductor active layer 12 and The prior art is the same and will not be repeated here. Then make gate insulating layer 13 on semiconductor active layer 12, gate insulating layer 13 can be silicon dioxide film (SiO2), silicon nitride film (SiNx), silicon nitride oxide film (SiO2Nx), gate insulating layer The specific manufacturing process of 13 is the same as that of the prior art, and will not be repeated here. Next, the gate 14 is fabricated on the gate insulating layer 13, and the gate 14 is a single-layer film of metals such as metal molybdenum (Mo), metal aluminum (Al), metal nickel (Ni), or a composite film composed of multiple metals. , the specific manufacturing process of the gate 14 is the same as that of the prior art, and will not be repeated here. Then make insulating layer 15 on gate 14, insulating layer 15 can be silicon dioxide film (SiO2), silicon nitride film (SiNx), silicon oxynitride film (SiO2Nx), the concrete manufacturing process of insulating layer 15 is the same as existing The technology is the same and will not be repeated here. Next, the source electrode 16 and the drain electrode 17 are formed on the insulating layer 15. The specific manufacturing process of the source electrode 16 and the drain electrode 17 is the same as that of the prior art, and will not be repeated here. Next, a flat layer 18 is formed on the source electrode 16 and the drain electrode 17. The specific manufacturing process of the flat layer 18 is the same as that of the prior art, and will not be repeated here. Next, the pixel electrode 19 is fabricated on the flat layer 18, and the specific fabrication process of the pixel electrode 19 is the same as that of the prior art, and will not be repeated here. Next, an organic light emission limiting layer 110 is fabricated on the pixel electrode 19 . The specific fabrication process of the organic light emitting limiting layer 110 is the same as that of the prior art, and will not be repeated here. Next, the organic light-emitting layer 111 is fabricated on the organic light-emitting limiting layer 110. The specific fabrication process of the organic light-emitting layer 111 is the same as that of the prior art, and will not be repeated here. Next, a layer of transparent conductive film 80 is deposited on the organic light-emitting layer 111 , and the upper electrode of the specific embodiment of the present invention is formed after patterning the transparent conductive film 80 .

In the specific embodiment of the present invention, in order to reduce the resistivity of the upper electrode, it is necessary to make an upper electrode with a thicker film thickness, and in order to improve the light transmittance of the upper electrode, it is necessary to make an upper electrode with a thinner film thickness. To reduce the resistivity of the upper electrode without affecting the light transmittance, the upper electrode is arranged in partitions, and the film thickness of the upper electrode is made thinner in the display light-transmitting area in contact with the organic light-emitting layer to improve the light transmittance. In the non-display area, the film thickness of the upper electrode is made thicker to reduce the resistivity of the upper electrode.

Specifically, as shown in FIG. 9, the specific embodiment of the present invention uses a halftone mask or a gray tone mask to make the upper electrode, such as the specific embodiment of the present invention uses a halftone mask 91 to make the upper electrode, halftone The mask plate 91 includes a semi-transparent region 911 , a light-shielding region 912 and a fully transparent region (not shown in the figure). During specific implementation, the photoresist 90 is coated on the transparent conductive film 80, and the exposure and development are carried out through the half-tone mask 91 to form a photoresist full coverage area, a photoresist partial coverage area and no photoresist coverage area. (not shown in the figure), wherein, the photoresist full coverage area corresponds to the non-display area 42 of the array substrate, the photoresist partial coverage area corresponds to the display area 41 of the array substrate, and the non-photoresist coverage area corresponds to the array substrate. Reserve the area for the upper electrode. The photoresist 90 of the specific embodiment of the present invention takes positive photoresist as an example, the photoresist corresponding to the display area 41 is irradiated with light through the semi-transparent area 911 of the halftone mask 91, and the photoresist corresponding to the non-display area 42 The photoresist is irradiated with light through the light-shielding region 912 of the halftone mask plate 91. Of course, the photoresist 90 in the specific embodiment of the present invention can also be a negative photoresist. If it is a negative photoresist, it is not The display area 42 corresponds to the fully transparent area of the halftone mask 91 .

Then by etching, remove the transparent conductive film in the non-photoresist coverage area, and remove the photoresist in the photoresist partial coverage area, exposing the transparent conductive film in the photoresist partial coverage area; then by etching, remove The exposed part of the thickness of the transparent conductive film forms the upper electrode located in the display area of the array substrate. Since a part of the transparent conductive film in the display area is etched away, the thickness of the transparent conductive film located in the display area is relatively thin; finally remove the remaining light Resist to form the upper electrode located in the non-display area of the array substrate. Since the transparent conductive film in the non-display area has not been etched, the thickness of the transparent conductive film located in the non-display area is relatively thick, which is obtained by the specific embodiment of the present invention. The thickness of the upper electrode in the non-display area is greater than that in the display area. The upper electrode 112 finally formed in the specific embodiment of the present invention is shown in FIG. 5 .

To sum up, the specific embodiments of the present invention provide an array substrate and a manufacturing method. The upper electrode facing the light-displaying surface in the array substrate is partitioned to form regions of the upper electrode with different thicknesses. The film thickness of the upper electrode in the display light-transmitting area is thinner to increase the light transmittance, and the film thickness of the upper electrode in the non-display area is thicker to reduce its resistivity, and at the same time it can reduce and assist Poor contact in the electrode wiring contact area can improve display quality and product yield without increasing the difficulty of the existing process.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (9)

1. a kind of array base palte, including underlay substrate, the underlay substrate includes viewing area and non-display area, the underlay substrate On be provided with thin film transistor (TFT), pixel electrode, organic luminous layer and the Top electrode being arranged on the organic luminous layer, it is special Sign is, in addition to auxiliary electrode；Wherein at least part is more than positioned at the thickness of the Top electrode of the non-display area and is located at The thickness of the Top electrode of the viewing area；The Top electrode positioned at the non-display area and the institute positioned at the viewing area Top electrode is stated to be integrally formed；The auxiliary electrode is located at the non-display area of underlay substrate, is located at same layer with the pixel electrode, The Top electrode is located on the auxiliary electrode and electrically connected with the auxiliary electrode, the Top electrode on the auxiliary electrode Thickness be more than the thickness of the Top electrode above the pixel electrode.

2. array base palte according to claim 1, it is characterised in that the thin film transistor (TFT) includes：It is sequentially located at described Semiconductor active layer, gate insulator, grid, insulating barrier, source electrode and drain electrode on underlay substrate；Or,

The thin film transistor (TFT) includes：Be sequentially located at grid on the underlay substrate, gate insulator, semiconductor active layer, Source electrode and drain electrode.

3. array base palte according to claim 2, it is characterised in that between the underlay substrate and the thin film transistor (TFT) It is provided with cushion.

4. array base palte according to claim 3, it is characterised in that also include the flatness layer being arranged on underlay substrate, Between the thin film transistor (TFT) and organic luminous layer, the pixel electrode is located on the flatness layer flatness layer, and The source electrode or drain electrode exposed by the via on flatness layer and thin film transistor (TFT) connects, and the organic luminous layer is positioned at described On pixel electrode.

5. array base palte according to claim 1, it is characterised in that the Top electrode is anode, or the Top electrode is Negative electrode.

6. array base palte according to claim 5, it is characterised in that the material of the Top electrode is tin indium oxide or oxidation The monofilm of indium zinc, or be tin indium oxide and the composite membrane of indium zinc oxide.

7. a kind of display device, it is characterised in that the display device includes the array base described in any claims of claim 1-6 Plate.

8. a kind of preparation method of array base palte, including the making of thin film transistor (TFT), the making of pixel electrode, organic luminous layer Making and the making of Top electrode, it is characterised in that when making pixel electrode, make and aid in layer in the non-display area of underlay substrate Electrode；In the making of the Top electrode, by patterning processes make to be at least partially disposed at array base palte non-display area it is described on The thickness of electrode is more than the thickness of the Top electrode positioned at array base palte viewing area；And make positioned at array base palte non-display area The Top electrode is integrally formed with the Top electrode positioned at array base palte viewing area, the Top electrode and auxiliary electrode electricity Connection, the thickness of the Top electrode on the auxiliary electrode are more than the thickness of the Top electrode above the pixel electrode.

9. according to the method for claim 8, it is characterised in that the patterning processes use intermediate tone mask plate or gray tone Mask plate makes the Top electrode, specifically includes：

Transparent conductive film is formed on organic luminous layer；

Photoresist is formed on the transparent conductive film, is exposed, shown by intermediate tone mask plate or gray tone mask plate Shadow, form photoresist and area, photoresist part of footprint and the unglazed photoresist area of coverage is completely covered, wherein, the photoresist is complete The area of coverage corresponds to the non-display area of array base palte, and photoresist part of footprint corresponds to the viewing area of array base palte；

By etching, the transparent conductive film of the unglazed photoresist area of coverage is removed, and remove the light of photoresist part of footprint Photoresist, expose the transparent conductive film of photoresist part of footprint；

By etching, the transparent conductive film of the segment thickness exposed is removed, is formed positioned at array base palte viewing area Top electrode；

Remaining photoresist is removed, the Top electrode positioned at array base palte non-display area is formed, positioned at the Top electrode of the non-display area Thickness be more than positioned at the viewing area Top electrode thickness.