CN104572574A - GigE (gigabit Ethernet) vision protocol-based Ethernet controller IP (Internet protocol) core and method - Google Patents

Abstract

The invention discloses an Ethernet controller IP core based on a Gigabit Ethernet visual protocol, which is composed of a control module, a PHY management interface module, a sending control module, a flow control module, and a receiving control module, implemented by FPGA, and following Avalon? Memory-Mapped interface specification and GMII interface specification. The present invention is based on GigE? The dedicated IP core designed for the characteristics of the Vision protocol can realize the reception and automatic storage of GigE camera images. While realizing image acquisition, it overcomes the shortcomings of traditional Ethernet controllers such as large resource usage, high CPU usage, and low image acquisition efficiency. , using the characteristics of FPGA parallel processing to improve data receiving speed and system real-time performance. Under the same test conditions, using this patent to realize image acquisition will reduce FPGA resource consumption by more than half compared with Altera's triple-speed Ethernet IP core.

Description

Ethernet Controller IP Core and Method Based on Gigabit Ethernet Vision Protocol

technical field

The invention relates to an image acquisition system, in particular to a gigabit ethernet control unit in an embedded image acquisition system based on gigabit ethernet vision (GigEVision) protocol.

Background technique

At present, the image acquisition equipment is mainly divided into two directions, one is an image acquisition card based on a personal computer (Personal Computer, PC), and the other is an image acquisition system based on an embedded microprocessor.

Due to the low bandwidth of the external controller interface (Peripheral Component Interconnect, PCI) bus interface and the use of a shared bus structure, the image acquisition card products based on the PCI bus have basically been eliminated. Although the performance of the new-generation PCI Express bus has been greatly improved compared with the traditional PCI bus, it still cannot solve the problems of poor real-time performance, poor stability and high cost of the PC system. Therefore, PC-based image acquisition card products It has been difficult to meet the needs of modern industrial testing. At present, the mainstream image acquisition devices are mainly image acquisition systems based on embedded microprocessors.

With the acceleration of information technology development, people's demand for video image transmission bandwidth is also increasing. The current mainstream camera interface standards such as Camera Link interface, IEEE1394 interface, and USB interface can no longer meet people's requirements for image information ingestion speed. The difference is that the Gigabit Ethernet (GigE) interface uses Gigabit Ethernet as the data transmission interface. While realizing image data transmission, it does not require additional acquisition equipment and has absolute bandwidth advantages.

However, the current image acquisition system based on common Gigabit Ethernet controllers mainly has the following two important problems:

One is that in order to implement the GigE Vision protocol, the design must use a general-purpose Ethernet controller. Such an Ethernet controller designed for general functions often has a complex structure and consumes a large amount of resources. Second, the CPU usage is too high. In order to receive image data, software must be used to filter Ethernet protocol (Internet Protocol, IP), user datagram protocol (User Datagram Protocol, UDP) and GigE Vision protocol data layer by layer, which will inevitably increase the central processing unit (Central Processing Unit). , CPU) processing burden, increasing the CPU usage.

The application number is 201010603189.5, and the invention patent name is "A Machine Vision System Based on FPGA and DSP". The system uses FPGA internal hardware circuit to realize image acquisition and preprocessing, and uses DSP to realize system logic control and advanced image processing. The image acquisition module of the system has the following defects:

(1) The Ethernet controller uses a 10/100/1000M triple-speed Ethernet media access controller. Although it is powerful, its implementation needs to consume more than 4,800 logic units, more than 5,300 register resources, and more than 19,000 bytes of storage resources. , resource consumption is huge, increasing the cost of hardware development;

(2) The software uses the μC/OS system for task scheduling, and the software protocol stack provided by the system is used for IP and UDP protocol packets and analysis, which has high software complexity, heavy system burden, and poor real-time performance;

(3) The implementation of the GigE Vision protocol is completed by software. Due to the real-time limitation of the embedded system, it will inevitably affect the judgment of packet loss, resulting in the loss and damage of image data.

The application number is 201310328995.X, and the patent name of the invention is "an embedded parallel multi-channel digital image acquisition system based on GigE interface". , and transmit image data to the upper computer according to the command of the upper computer, the focus is on collecting multiple image signals and uploading them to the PC for processing. The system has the following drawbacks:

(1) Its network data transmission and reception adopts a general-purpose Ethernet controller, and the realization of IP, UDP and other network protocols still requires software implementation, which has a large system burden and high CPU usage;

(2) The received network data needs to be transported in real time by the system arbitration module before it can be read by the GigE protocol analysis module. The image data analyzed by the GigE protocol analysis module must be read by the system arbitration module and then stored in the corresponding memory. This mechanism allows a large amount of data to be transmitted back and forth on the bus, which greatly increases the bus occupancy rate, increases the complexity of the system arbitration module, and affects the real-time performance of the system;

(3) Although the system uses hardware resources to analyze the GigE interface data packets, it has not optimized the hardware for the GVSP protocol, and the retransmission mechanism of the data packets still needs to be implemented by software. It is difficult to achieve high real-time performance and affect the image. Data integrity and frame rate of image reception.

Contents of the invention

Purpose of the invention:

In order to overcome the shortcomings of traditional Ethernet controllers such as large resource occupation, high CPU usage, and low image acquisition efficiency, the present invention optimizes traditional Ethernet controllers and designs a dedicated IP core according to the characteristics of the GigE Vision protocol. The present invention uses hardware logic to realize the encapsulation and analysis of IP, Address Resolution Protocol (Address Resolution Protocol, ARP), UDP, and Gigabit Ethernet Vision Control Protocol (GigE Vision Control Protocol, GVCP). Simultaneously, the present invention utilizes the characteristic of parallel processing of FPGA, under the situation that does not have CPU assistance, controls Avalon Memory-Mapped main interface, according to the ID of Gigabit Ethernet Vision Stream Protocol (GigE Vision Stream Protocol, GVSP) packet, automatically The image data is stored in the memory space specified by the user, which improves the data receiving speed and the real-time performance of the system.

Technical solutions:

An Ethernet controller IP core based on the GigE Vision protocol is an intellectual property core in a Field Programmable Gate Array (Field Programmable Gate Array, FPGA), and is specifically composed of a MAC control module, a PHY management interface module, a transmission control module, It is composed of flow control module and receiving control module, implemented by FPGA, connected with NIOS processor through Avalon Memory-Mapped slave interface, connected with image storage RAM through Avalon Memory-Mapped master interface, and connected with PHY management interface and thousand Gigabit Media Independent Interface (GMII) is connected to the physical layer (PHY).

The MAC control module includes a register unit, a module control unit and a bus control unit, receives bus information sent by the NIOS processor, and controls other modules;

The PHY management interface module is used to access PHY registers, automatically generate MDC clock and MDIO data according to PHY access control signals and PHY management interface timing specifications, control the PHY management interface, access PHY registers, and generate PHY access feedback signals;

The sending control module includes a first dual-port RAM, a protocol packet module, a second dual-port RAM and a GMII sending module, and automatically sends corresponding Ethernet data packets according to sending control signals, ARP sending control signals and packet loss and resending control signals, and generates send a feedback signal;

The flow control module includes an image storage control module and a flow detection module. According to the storage control signal and the flow control signal, the GVSP data is read through the GVSP data read bus, the image data is written into the image storage RAM, and a storage feedback signal is generated. Detect packet loss, control packet loss and resend control signals;

The receiving control module includes a third dual-port RAM, a fourth dual-port RAM, a fifth dual-port RAM, a protocol analysis module, an asynchronous FIFO and a GMII receiving module, receives Ethernet data packets, analyzes them according to the receiving control signal, and generates a receiving module. Feedback signal and flow control signal, and send parsed data through receiving data reading bus and GVSP data reading bus respectively.

Preferably, the register unit is used to store control information, status information, local network address information and camera network address information; the module control unit generates PHY access control signals, sends control signals, Receive control signals and storage control signals; the bus control unit analyzes the address and control signals from the Avalon Memory-Mapped slave interface, and realizes the CPU's access to different address spaces in the IP core, including register units, the first dual-port RAM, The third dual-port RAM and the fourth dual-port RAM.

Preferably, the first dual-port RAM receives and buffers the sending data by sending the data into the bus, and converts the sending data from the clock domain where the system is located to the clock domain where the GMII sending module is located; the protocol packet module includes an IP protocol packet module, a UDP protocol packet module , GVCP protocol packet module and ARP protocol packet module, according to the sending control signal, automatically send the data packet network protocol, and store the packet header data in the second dual-port RAM; the GMII sending module includes a CRC-32 generation module, which converts the first The data of the port RAM and the second dual-port RAM are combined into an Ethernet frame and sent; the CRC-32 generation module automatically generates a 32-bit CRC check code.

Preferably, the flow detection module reads the fifth dual-port RAM, obtains the image data packet ID number and image data according to the GVSP protocol, detects the packet loss situation, automatically calculates the ID number of the lost data packet, and generates a packet loss retransmission control signal; The storage control module controls the main interface of Avalon Memory-Mapped according to the ID number of the image data packet and the storage control signal, automatically calculates the storage address, and stores the image data in the image storage RAM.

Preferably, the GMII receiving module is embedded with a CRC-32 checking module, receives the network data packet, writes it in the asynchronous FIFO, and checks it; the asynchronous FIFO buffers the received Ethernet data, and receives the data from the GMII where the clock is located The clock domain is converted to the clock domain where the protocol analysis module is located; the protocol analysis module includes an ARP protocol analysis module, an IP protocol analysis module, a UDP protocol analysis module, a GVCP protocol analysis module, and a GVSP protocol analysis module. Data are respectively stored in different dual-port RAMs; the third dual-port RAM buffers received GVCP data; the fifth dual-port RAM buffers received GVSP data; and the fourth dual-port RAM buffers other data received.

The image data transmission method of the Ethernet controller IP core based on the GigE Vision protocol of the present invention is:

The bus control unit reads the Avalon bus command, and controls the reading and writing of the register unit, the first dual-port RAM, the third dual-port RAM and the fourth dual-port RAM according to the read and write signals and address information.

When sending Ethernet data,

[1] The bus control unit (1.3) writes the sending data into the first dual-port RAM (3.1) according to the bus address, and writes the control command into the register unit (1.1);

[2] The module control unit (1.2) detects the register unit (1.1) in real time, and after detecting the sending command, generates a corresponding sending control signal (8);

[3] The protocol packet module (3.2) reads the sending control signal (8), generates the corresponding protocol packet header, and stores the packet header data in the second dual-port RAM (3.3);

[4] GMII sending module (3.4) reads the data in the first dual-port RAM (3.1) and the second dual-port RAM (3.3), forms Ethernet frame and sends;

[5] At the same time, the sending control module (3) generates a sending feedback signal (10);

[6] The module control unit (1.2) detects and sends the feedback signal (10) in real time, and writes the feedback information into the register unit (1.1);

The Ethernet data receiving process of the entire IP core is:

(1) The GMII receiving module (5.6) receives the broadcast data packet or the data packet sent to the local MAC address in real time, and writes the data into the asynchronous FIFO (5.5);

(2) The protocol analysis module (5.4) reads the data in the asynchronous FIFO (5.5), and analyzes the protocol of the data packet;

(3) if the packet is an ARP request packet, the ARP protocol analysis module (5.4.1) generates an ARP request signal according to the request data, and the request sends the control module (3) to send the ARP response packet;

(4) if the data packet is an IP data packet, the IP protocol analysis module (5.4.5) further analyzes the protocol of the data packet, and judges whether the data packet is a UDP data packet;

(5) if the data packet is a UDP data packet, the UDP protocol analysis module (5.4.4) judges the destination port number, and judges whether the data packet is a GVCP data packet or a GVSP data packet;

(6) If the data packet is a GVCP data packet, the GVCP analysis module (24) parses the data packet, writes the GVCP data into the third dual-port RAM (5.1), and generates a corresponding receiving feedback signal (12);

(7) if the data packet is a GVSP data packet, the GVSP analysis module (25) parses the data packet, writes the GVSP data into the fifth dual-port RAM (5.3), and generates a flow control signal (19);

(8) protocol analysis module (5.4) writes other data packets into the fourth dual-port RAM (5.2), and generates corresponding receiving feedback signals (12);

(9) After the flow control module (4) receives the flow control signal (19), the control flow detection module (4.2) reads the fifth dual-port RAM (5.3);

(10) flow detection module (4.2) obtains Block ID, Packet ID and image data of GVSP packet in the data read, and according to Block ID and Packet ID, packet loss situation is judged, if find packet loss, then generate Packet loss retransmission control signal (15);

(11) image storage control module (4.1) obtains image storage first address from storage control signal (14), calculates the storage address of image data in this data packet according to the Packet ID of image data and the length of image data, and controls The Avalon Memory-Mapped main interface writes the image data into the image storage RAM; when a complete image data is written, the image storage control module (4.1) generates a storage feedback signal (13).

Compared with the prior art, the present invention has the following advantages:

1. The present invention designs a lightweight Ethernet controller for the GigE Vision protocol, compatible with GigE Vision 1.0 and GigE Vision 2.0 protocols, and implements protocol filtering and analysis on hardware logic, and the flat design greatly reduces the complexity of the Ethernet controller , reduce the consumption of hardware logic, and reduce the cost of the system while increasing the image transmission speed.

2. The present invention uses hardware logic to automatically package or analyze network data based on the GigE Vision protocol, so that the package and filtering of network data does not require software intervention, thereby greatly reducing the burden on the software system.

3. The present invention automatically stitches and stores image data, and the image data receiving process can be completely separated from the CPU and run independently, thereby reducing the CPU usage to the greatest extent.

4. Using the present invention to develop, the user does not need to build a multi-tasking software environment, and does not need to grasp the specific content of the composition of the Ethernet frame, the IP protocol, the UDP protocol, and the GigE Vision protocol, and does not need to care about the processing method of the GVSP data. The user only needs to add the IP core of the present invention to the system, and simply configure the registers to realize the access of the GigE camera and the acquisition of images, thereby reducing the development difficulty of the image acquisition system to the greatest extent, and realizing Large-scale promotion and application.

Description of drawings

Fig. 1 is the hardware system block diagram of the embodiment of the present invention;

Fig. 2 is the system block diagram of the embodiment of the present invention;

Fig. 3 is the interface diagram of the present invention;

Fig. 4 is a structural block diagram of the present invention;

Fig. 5 is the processing flowchart of the present invention;

Fig. 6 is the flow chart of the sending operation of the embodiment of the present invention;

Fig. 7 is a flow chart of the receiving operation of the embodiment of the present invention.

Detailed ways

Referring to Figure 1, an Ethernet controller IP core based on the GigE Vision protocol is implemented using an FPGA system. The main hardware used in the implementation includes FPGA modules, EPCS management modules, power management modules, SSRAM, PHY chips and their modules, and GigE Camera, the specific chip used is:

[1] The FPGA adopted by the implementation system adopts the EP2S60F672C3N chip of the Stratix II series of Altera Company;

[2] The SSRAM adopted by the implementation system is the CY7C1380D chip of Cypress Company;

[3] The PHY chip used in the implementation system is the 88E1111 chip of Marvell;

[4] The GigE camera used in the implementation system is the acA640-90gc camera of Basler Company.

With reference to Fig. 2, the IP module that implementation case adopts on FPGA comprises NIOS II microprocessor, external RAM module interface, image storage module, Ethernet controller IP core and other modules based on GigE Vision protocol of the present invention.

Referring to Figure 3, the interfaces of the Ethernet controller IP core based on the GigE Vision protocol implemented in this implementation case include Avalon Memory-Mapped master interface, Avalon Memory-Mapped slave interface, PHY management interface and GMII interface.

The Avalon Memory-Mapped main interface signal provided by the GVSP receiving module is a chip select signal, a request waiting signal, a write enable signal, a read enable signal, a 32-bit address signal, a 32-bit read data signal and a 32-bit write data signal.

The Avalon Memory-Mapped slave interface signals are system clock signal, 125MHz GMII sending clock, system reset signal, chip select signal, read enable signal, write enable signal, 14-bit address signal, 32-bit write data signal and 32-bit bit read data signal.

The PHY management interface signals are 2MHz MDC signals and MDIO signals.

Described GMII sending interface signal is 125MHz GMII sending clock, sending enable signal, sending error signal, sending data signal, receiving clock, receiving data valid signal, receiving error signal, receiving data signal, carrier sense signal and conflict detection signal .

Referring to Figure 4, the Ethernet controller IP core based on the GigE Vision protocol implemented in this implementation case includes a control module 1, a PHY management interface module 2, a sending control module 3, a flow control module 4, and a receiving control module 5. The Memory-Mapped slave interface is connected to the CPU, the AvalonMemory-Mapped master interface is connected to the image storage RAM, and the PHY management interface and GMII interface are connected to the PHY.

The control module 1 includes a register unit 1.1, a module control unit 1.2 and a bus control unit 1.3, receives bus information sent by the NIOS processor, and controls other modules. Register unit 1.1 is used to store control information, status information, local network address information and camera network address information; module control unit 1.2 accesses feedback signal 7, sends feedback signal 10, receives feedback signal 12 and stores feedback signal according to register information and PHY 13 generate PHY access control signal 6, send control signal 8, receive control signal 11 and store control signal 14; bus control unit 1.3 obtains Avalon Memory-Mapped slave interface information, operates register unit 1.1, first dual-port RAM 3.1, third Dual-port RAM 5.1 or fourth dual-port RAM 5.2.

The MAC control module 1 has the function of receiving an interrupt request. The module control unit 1.2 generates an interrupt signal according to the received feedback signal 12 and the stored feedback signal 13. The CPU judges the interrupt type by reading the receiving status register.

The register unit 1.1 includes MAC control register, MAC status register, interrupt control register, interrupt status register, PHY control register, PHY read data register, PHY write data register, send control register, receive control register, flow control register, this Machine MAC address register, local IP address register, GVCP port number register, GVSP port number register, camera MAC address register and camera IP address register.

Described bus control unit 1.3 resolves the address and the control signal from the Avalon Memory-Mapped slave interface, realizes that CPU accesses different address spaces in the IP core, wherein the distribution of addresses is as shown in Table 1:

Table 1 The address assignment of the bus control unit (1.3) to different access spaces of the IP core

The PHY access control signal 6 is a PHY access enable signal, a 5-bit PHY register address signal, a 32-bit PHY register write data signal, and a 32-bit PHY register read data signal.

The PHY access feedback signal 7 is a busy signal of the PHY management interface module.

The sending control signal 8 is the 48-bit MAC address of the machine and the camera, the 32-bit IP address of the machine and the camera, the 16-bit GVCP port number of the machine, the sending enable signal, the 16-bit sending protocol type, and the 9-bit sending data length (unit: byte).

The sending feedback signal 10 is a busy signal of the sending control module.

The receiving control signal 11 is the 48-bit MAC address of the machine and the camera, the 32-bit IP address of the machine and the camera, the 16-bit GVCP port number of the machine and the 16-bit GVSP port number of the machine.

The receiving feedback signal 12 is a receiving completion signal, 16-bit receiving protocol type, 11-bit GVSP data address and 11-bit receiving data length (unit: byte).

The storage control signal 14 is a storage enable signal and a 32-bit image storage first address.

The storage feedback signal 13 is an image storage completion signal.

The PHY management interface module 2 is used to access the PHY registers, automatically generates the MDC clock and MDIO data according to the PHY access control signal 6 and the PHY management interface timing specification, controls the PHY management interface, accesses the PHY registers, and generates the PHY access feedback signal 7 .

Sending control module 3 includes first dual-port RAM 3.1, protocol packet module 3.2, second dual-port RAM 3.3 and GMII sending module 3.4, according to sending control signal 8, ARP sending control signal 17 and packet loss retransmission control signal 15 automatically Send the corresponding Ethernet data packet and generate the sending feedback signal 10; the first dual-port RAM 3.1 receives and buffers the sending data by writing the sending data into the bus 9, and converts the sending data from the clock domain where the system is located to the clock where the GMII sending module 3.4 is located Domain; Protocol packet module 3.2 comprises IP protocol packet module 3.2.1, UDP protocol packet module 3.2.2, GVCP protocol packet module 3.2.3 and ARP protocol packet module 3.2.4, sends control signal 17 according to sending control signal 8, ARP And packet loss retransmission control signal 15, for sending data packet network protocol automatically, the packet header data is stored in the second dual-port RAM 3.3; the second dual-port RAM 3.3 is used to store the generated packet header data; GMII sending module 3.4 includes CRC-32 generation module 3.4.1, combines the data of the first dual-port RAM3.1 and the second dual-port RAM 3.3 into an Ethernet frame and sends it; CRC-32 generation module 3.4.1 automatically generates a 32-bit CRC check code ;

The sending control module (3) has an ARP protocol automatic response function, and can automatically send an ARP response data packet according to the ARP sending control signal (17), and record the MAC address and IP address of the host computer.

The sending control module (3) has a GVSP data packet resending request function, can resend the control signal (15) when the packet is lost, automatically generate a data packet resending command, and request the camera to resend the corresponding GVSP data packet.

Described first dual-port RAM 9 uses FPGA on-chip storage block to realize, and the first dual-port RAM 9 write port uses system clock, and data bit width is 32 bits, and read port uses GMII to send clock, and data is wide and is 8 bits.

The ARP transmission control signal 17 is an ARP transmission request signal, a 48-bit host MAC address and a 32-bit host IP address.

The packet loss retransmission control signal 15 is a retransmission request signal, a 16-bit GVSP port number, and a 24-bit minimum ID and maximum ID of the retransmission data packet.

Described flow control module 4 comprises image storage control module 4.1 and flow detection module 4.2, reads GVSP data by GVSP data reading bus 18, writes image data in the image storage RAM, generates storage feedback signal 13, detects missing Packet situation, control packet loss retransmission control signal 15. The flow detection module 4.2 reads the fifth dual-port RAM 5.3, obtains the image data packet ID number and image data according to the GVSP protocol, detects packet loss, and generates a packet loss retransmission control signal 15. The image storage control module 4.1 controls the Avalon Memory-Mapped main interface according to the image data packet ID number, and writes the image data in the image storage RAM.

Described receiving control module 5 comprises the 3rd dual-port RAM 5.1, the 4th dual-port RAM 5.2, the 5th dual-port RAM 5.3, protocol analysis module 5.4, asynchronous FIFO 5.5 and GMII receiving module 5.6, receive Ethernet packet, according to The reception control signal 11 parses it and generates a reception feedback signal 12 and a flow control signal 19 . GMII receiving module 5.6 is embedded with CRC-32 checking module 5.6.1, receives network data packets, writes them into asynchronous FIFO 5.5, and checks them; asynchronous FIFO 5.5 caches received Ethernet data, and sends data from GMII The clock domain where the receiving clock is located is converted to the clock domain where the protocol analysis module is located; the third dual-port RAM 5.1 buffers the received GVCP data; the fifth dual-port RAM 5.3 buffers the received GVSP data; the fourth dual-port RAM 5.2 buffers other data received; Protocol analysis module 5.4 comprises ARP agreement analysis module 5.4.1, IP agreement analysis module 5.4.5, UDP agreement analysis module 5.4.4, GVCP agreement analysis module 5.4.2 and GVSP agreement analysis module 5.4.3, according to receiving control signal 11 Read the asynchronous FIFO 5.5, analyze the received data, and store the analyzed data in different dual-port RAMs, the third dual-port RAM 5.1 buffers the received GVCP data; the fifth dual-port RAM 5.3 buffers the received GVSP data; the fourth dual-port RAM 5.2 buffers other data received. The data buffered by the third dual-port RAM 5.1 and the fourth dual-port RAM 5.2 are sent to the MAC control module 1 through the receiving data read bus 16, and the data buffered by the fifth dual-port RAM 5.3 is sent to the flow control through the GVSP data read bus 18 Module 4.

The third dual-port RAM 5.1, the fourth dual-port RAM 5.2 and the fifth dual-port RAM 5.3 are implemented using FPGA on-chip storage blocks, the write port uses GMII to send the clock, the data bit width is 32 bits, and the read port uses the system clock. The data is 8 bits wide.

The asynchronous FIFO 5.5 is implemented using FPGA on-chip storage blocks, the write port uses GMII receiving clock, the data bit width is 32 bits, and the read port uses GMII sending clock, and the data width is 8 bits.

Referring to Figure 5, the workflow of the Ethernet controller IP core based on the GigE Vision protocol implemented in this implementation case is:

Avalon Memory-Mapped from the analysis of the interface:

[1] Bus control unit 1.3 monitors Avalon Memory-Mapped slave interface; detects chip select signal, read/write signal and address signal;

[2] When the chip select signal is valid, the bus control unit 1.3 judges the resource that the CPU needs to access according to the read/write signal and the address signal, and enables the read/write of the corresponding resource, and analyzes the address at the same time, so that the CPU can access space to operate.

Send ethernet data:

[1] The module control unit 1.2 detects the sending feedback signal 10 in real time, and writes the sending status into the register unit 1.1 for the CPU to read;

[2] The module control unit 1.2 detects the register unit 1.1 in real time, and generates a corresponding sending control signal 8 after detecting the sending command;

[3] The protocol packet module 3.2 reads the sending control signal 8, generates a corresponding protocol packet header, and stores the packet header data in the second dual-port RAM3.3;

[4] GMII sending module 3.4 reads the data in the first dual-port RAM3.1 and the second dual-port RAM3.3, forms Ethernet frame and sends;

[5] At the same time, the sending control module 3 generates a sending feedback signal 10;.

Receive Ethernet data:

[1] The GMII receiving module 5.6 receives the broadcast data packet or the data packet sent to the local MAC address in real time, and writes the data into the asynchronous FIFO 5.5;

[2] The protocol analysis module 5.4 reads the data in the asynchronous FIFO 5.5, and analyzes the protocol of the data packet;

[3] If the data packet is an ARP request packet, the ARP protocol analysis module 5.4.1 generates an ARP request signal according to the request data, and requests the sending control module 3 to send the ARP response packet;

[4] If the data packet is an IP data packet, the IP protocol analysis module 5.4.5 further analyzes the protocol of the data packet, and judges whether the data packet is a UDP data packet;

[5] If the data packet is a UDP data packet, the UDP protocol analysis module 5.4.4 judges the destination port number, and judges whether the data packet is a GVCP data packet or a GVSP data packet;

[6] If the data packet is a GVCP data packet, the GVCP parsing module 5.4.2 parses the data packet, writes the GVCP data into the third dual-port RAM 5.1, and generates a corresponding receiving feedback signal 12;

[7] If the data packet is a GVSP data packet, the GVSP analysis module 5.4.3 parses the data packet, writes the GVSP data into the fifth dual-port RAM 5.3, and generates a flow control signal 19;

[8] The protocol analysis module 5.4 writes other data packets into the fourth dual-port RAM 5.2, and generates a corresponding receiving feedback signal 12;

[9] After the flow control module 4 receives the flow control signal 19, the control flow detection module 4.2 reads the fifth dual-port RAM 5.3;

[10] The flow detection module 4.2 obtains the Block ID, PacketID and image data of the GVSP packet in the read data, and judges the packet loss situation according to the Block ID and Packet ID. Send control signal 15;

[11] The image storage control module 4.1 obtains the first address of the image storage from the storage control signal 14, calculates the storage address of the image data in the data packet according to the Packet ID of the image data and the length of the image data, and controls the Avalon Memory-Mapped master The interface writes the image data into the image storage RAM; when a complete image data is written, the image storage control module 4.1 generates a storage feedback signal 13 .

Referring to Figure 6, the operation flow required for the CPU to send Ethernet data is:

[1] Read the sending status register to judge whether the sending control module 3 is in the sending state, if the sending control module 3 is in the sending state, then wait;

[2] If the waiting time is too long, an error message will be sent back, and the CPU needs to reconfigure the IP core;

[3] If the sending control module 3 is in an idle state, the CPU writes the sending data into the address space where the first dual-port RAM 3.1 is located, and writes the control command into the corresponding register space;

[4] After the IP core receives the send command, it starts to send the data packet and sends it.

Referring to Fig. 7, the operation process required for the CPU to receive Ethernet data or image data is:

[1] The CPU judges the receiving status by querying the receiving status register or interrupting, and calls the receiving processing function;

[2] The CPU reads the receiving status register to obtain the received data type, and the data type is divided into GVCP data, single image data or other network data;

[3] If it is GVCP data, the CPU reads the GVCP data as needed and performs corresponding operations;

[4] If it is image data, the CPU processes the image according to actual needs and performs corresponding operations;

[5] If it is other data, the CPU reads the data as needed and performs corresponding operations.

In this implementation case, the Ethernet controller IP core based on the GigE Vision protocol consumes more than 2000 logic units, more than 1500 register resources and more than 8000 bytes of storage resources. Under high-speed image conditions, the image receiving rate reached 90 frames per second, and the CPU usage rate was less than 1%. Under the same test conditions, using Altera's triple-speed Ethernet IP core to realize this function consumed more than 4800 logic units, More than 5,300 register resources and about 19,000 bytes of storage resources. In addition, image reception requires additional DMA resources, and the analysis of GVSP data packets needs to be completed by users through software, which leads to high development costs and large resource usage.

The above is only a specific example of the present invention and does not constitute any limitation to the present invention. Therefore, any changes that those skilled in the art can conceive should fall within the protection scope of the present application.

Claims (10)

1., based on an ethernet controller IP kernel for GigE Vision agreement, it is characterized in that:

Whole IP kernel is made up of MAC control module (1), PHY management interface module (2), transmission control module (3), flow control module (4), reception control module (5), use hardware logic to realize package and the parsing of IP, ARP, UDP and GigE Vision agreement, follow Avalon Memory-Mapped interface specification and gmii interface specification;

MAC control module (1) comprises register cell (1.1), module control unit (1.2) and bus control unit (1.3), receives the bus message that NIOS processor sends, controls other modules;

PHY management interface module (2) is for accessing PHY register, according to PHY access control signal (6) and PHY management interface timing sequence specification, automatic generation MDC clock and MDIO data, control PHY management interface, access PHY register, generates PHY and accesses feedback signal (7);

Send control module (3) and comprise the first two-port RAM (3.1), agreement package module (3.2), the second two-port RAM (3.3) and GMII sending module (3.4), according to transmit control signal (8), ARP transmits control signal (17) and packet loss retransmits control signal (15) the corresponding Ethernet data bag of transmission automatically, generates and sends feedback signal (10);

Flow control module (4) comprises image storage control module (4.1) and stream detection module (4.2), according to storage control signal (14), flow control signals (19), GVSP data are read by GVSP data read bus (18), view data being write image stores in RAM, and generate store feedback signal (13), detect packet drop simultaneously, control packet loss and retransmit control signal (15);

Receive control module (5) and comprise the 3rd two-port RAM (5.1), the 4th two-port RAM (5.2), the 5th two-port RAM (5.3), protocol resolution module (5.4), asynchronous FIFO (5.5) and GMII receiver module (5.6), receive Ethernet data bag, according to reception control signal (11), it is resolved, generate receiving feedback signals (12) and flow control signals (19), and respectively by receiving the data of data read bus (16) and GVSP data read bus (18) transmission parsing.

2. the ethernet controller IP kernel based on GigE Vision agreement according to claim 1, is characterized in that register cell (1.1) is for depositing control information, state information, native network address information and camera network address information; The feedback information of the information that module control unit (1.2) is deposited according to register cell (1.1) and reception, generates PHY access control signal (6), transmit control signal (8), reception control signal (11) and storage control signal (14); Bus control unit (1.3) is resolved from the address of interface and control signal from Avalon Memory-Mapped, realize the access of CPU to address spaces different in IP kernel, comprise register cell (1.1), the first two-port RAM (3.1), the 3rd two-port RAM (5.1) and the 4th two-port RAM (5.2).

3. the ethernet controller IP kernel based on GigE Vision agreement according to claim 1, it is characterized in that the first two-port RAM (3.1) receives transmission data and buffer memory by sending data write bus (9), transmission data are transformed into GMII sending module (3.4) place clock zone from system place clock zone; Agreement package module (3.2) comprises IP agreement package module (3.2.1), udp protocol package module (3.2.2), GVCP agreement package module (3.2.3) and ARP agreement package module (3.2.4), according to transmit control signal (8), automatically for sending data packet procotol, first data will be wrapped stored in the second two-port RAM (3.3); GMII sending module (3.4) comprises CRC-32 generation module (3.4.1), and the data assemblies of the first two-port RAM (3.1) and the second two-port RAM (3.3) is become ethernet frame and sends; CRC-32 generation module (3.4.1) generates 32 CRC check codes automatically.

4. the ethernet controller IP kernel based on GigE Vision agreement according to claim 1, it is characterized in that stream detection module (4.2) reads the 5th two-port RAM (5.3), No. ID, view data bag and view data is obtained according to GVSP agreement, detect packet drop, No. ID of automatic calculating lost data packets, generates packet loss and retransmits control signal (15); Image storage control module (4.1) is according to No. ID, view data bag and storage control signal (14), and control Avalon Memory-Mapped main interface, automatic calculating memory addresses, is stored into image and stores in RAM by view data.

5. the ethernet controller IP kernel based on GigE Vision agreement according to claim 1, it is characterized in that the embedded CRC-32 inspection module (5.6.1) of GMII receiver module (5.6), receiving network data bag, write in asynchronous FIFO (5.5), and it is verified; Data are transformed into protocol resolution module place clock zone from GMII receive clock place clock zone by the Ethernet data that asynchronous FIFO (5.5) buffer memory receives; Protocol resolution module (5.4) comprises ARP protocol resolution module (5.4.1), IP protocol resolution module (5.4.5), udp protocol parsing module (5.4.4), GVCP protocol resolution module (5.4.2) and GVSP protocol resolution module (5.4.3), reception data are resolved, and by the data of parsing respectively stored in different two-port RAMs; The GVCP data that 3rd two-port RAM (5.1) buffer memory receives; The GVSP data that 5th two-port RAM (5.3) buffer memory receives; Other data that 4th two-port RAM (5.2) buffer memory receives.

6. the ethernet controller IP kernel based on GigE Vision agreement according to claim 1, it is characterized in that, described transmission control module (3) has ARP agreement automatic answer function, can receive and resolve host computer send ARP request data package, and the corresponding arp reply packet of transmission is replied automatically, and the MAC Address of host computer and IP address are carried out record.

7. the ethernet controller IP kernel based on GigE Vision agreement according to claim 1, it is characterized in that, described transmission control module (3) has GVSP data packet retransmission request function, GVSP packet packet drop can be detected in real time, and when finding packet loss, the request of automatic transmission data packet retransmission, corresponding GVSP packet retransmitted by request camera.

8. the ethernet controller IP kernel based on GigE Vision agreement according to claim 1, it is characterized in that, described MAC control module (1) has receive interruption request function, module control unit (1.2) produces interrupt signal according to receiving feedback signals (12), store feedback signal (13), and CPU judges interrupt type by reading accepting state register.

9. the ethernet controller IP kernel based on GigE Vision agreement according to claim 1, it is characterized in that, described register cell (1.1) comprises MAC control register, mac state register, interrupt control register, interrupt status register, PHY control register, PHY read data register, PHY write data register, transmit control register, receive control register, current control register, the machine MAC Address register, local IP address register, GVCP port numbers register, GVSP port numbers register, camera MAC Address register and camera IP address register.

10. the image data transfer method based on the ethernet controller IP kernel of GigE Vision agreement, it is characterized in that, described IP kernel is made up of MAC control module (1), PHY management interface module (2), transmission control module (3), flow control module (4), reception control module (5), and described MAC control module (1) comprises register cell (1.1), module control unit (1.2) and bus control unit (1.3); Send control module (3) and comprise the first two-port RAM (3.1), agreement package module (3.2), the second two-port RAM (3.3) and GMII sending module (3.4); Agreement package module (3.2) comprises IP agreement package module (3.2.1), udp protocol package module (3.2.2), GVCP agreement package module (3.2.3) and ARP agreement package module (3.2.4); GMII sending module (3.4) comprises CRC-32 generation module (3.4.1); Flow control module (4) comprises image storage control module (4.1) and stream detection module (4.2); Receive control module (5) and comprise the 3rd two-port RAM (5.1), the 4th two-port RAM (5.2), the 5th two-port RAM (5.3), protocol resolution module (5.4), asynchronous FIFO (5.5) and GMII receiver module (5.6); Protocol resolution module (5.4) comprises ARP protocol resolution module (5.4.1), IP protocol resolution module (5.4.5), udp protocol parsing module (5.4.4), GVCP protocol resolution module (5.4.2) and GVSP protocol resolution module (5.4.3); GMII receiver module (5.6) comprises CRC-32 inspection module (5.6.1);

The Ethernet data transmission flow of whole IP kernel is:

［ 1 ］ bus control unit (1.3) is according to bus address, transmission data is write in the first two-port RAM (3.1), control command is write in register cell (1.1);

［ 2 ］ module control unit (1.2) detected register unit (1.1) in real time, detects after sending order, generates and transmit control signal (8) accordingly;

［ 3 ］ agreement package module (3.2) reads and transmits control signal (8), generates corresponding protocol package first, and will wrap first data stored in the second two-port RAM (3.3);

［ 4 ］ GMII sending module (3.4) reads the data in the first two-port RAM (3.1) and the second two-port RAM (3.3), forms ethernet frame and sends;

［ 5 ］ at the same time, send control module (3) and produce transmission feedback signal (10);

［ 6 ］ module control unit (1.2) detects in real time and sends feedback signal (10), and feedback information is write register cell (1.1);

The Ethernet data of whole IP kernel receives flow process and is:

(1) GMII receiver module (5.6) real-time reception broadcast data packet or be sent to the packet of local mac address, and data are write asynchronous FIFO (5.5);

(2) protocol resolution module (5.4) reads the data in asynchronous FIFO (5.5), resolves the agreement of packet;

(3) if packet is ARP request data package, ARP protocol resolution module (5.4.1), according to request msg, produces ARP request signal, and request sends control module (3) and sends arp reply packet;

(4) if packet is IP packet, IP protocol resolution module (5.4.5) is resolved the agreement of packet further, judges whether this packet is UDP message bag;

(5) if packet is UDP message bag, udp protocol parsing module (5.4.4) judges destination slogan, judges whether this packet is GVCP packet or GVSP packet;

(6) if packet is GVCP packet, GVCP parsing module (24) resolution data bag, by GVCP data write the 3rd two-port RAM (5.1), and produces corresponding receiving feedback signals (12);

(7) if packet is GVSP packet, GVSP parsing module (25) resolution data bag, by GVSP data write the 5th two-port RAM (5.3), and produces flow control signals (19);

(8) protocol resolution module (5.4) is by other packets write the 4th two-port RAM (5.2), and produces corresponding receiving feedback signals (12);

(9), after flow control module (4) receives flow control signals (19), control-flow detection module (4.2) reads the 5th two-port RAM (5.3);

(10) Block ID, Packet ID and view data that detection module (4.2) obtains GVSP packet in the data read is flowed, and according to Block ID and Packet ID, packet drop is judged, if discovery packet loss, then produce packet loss and retransmit control signal (15);

(11) image storage control module (4.1) obtains image and stores first address from storage control signal (14), calculate the memory address of view data in this packet according to the Packet ID of view data and the length gauge of view data, and view data is write image storage RAM by control Avalon Memory-Mapped main interface; When after the view data that write one is complete, image storage control module (4.1) then produces store feedback signal (13).