CN104599620B - Phase inverter, grid integrated drive and the driving method of grid integrated drive electronics - Google Patents

Abstract

The invention discloses an inverter of a gate integrated driving circuit, which comprises transistors T1v-T5v and a coupling capacitor C1v, the second electrode of T1v and the second electrode of T3v are connected to a positive level VDD, and the gate of T1v and the first electrode are both Connect the second electrode of T2v, the gate of T3v, the first electrode of T5v and one end of C1v; the gate of T2v and the gate of T4v are connected to the control signal, the gate of T5v and the second electrode are connected to the feedback signal RSTv, the first electrode of T2v One electrode and the first electrode of T4v are connected to the first negative level, and the second electrodes of T3v and T4v are connected to the other end of C1v to form an inverter output node QBv. The invention also discloses a gate integrated driving circuit comprising the above-mentioned inverter and a driving method thereof. The invention realizes low power consumption, low noise and good anti-interference ability, and the pull-up transistor and the inverter of the output stage act quickly, and can realize working at a higher frequency.

Description

Inverter of gate integrated drive circuit, gate integrated driver and driving method

technical field

The invention relates to gate drive technology of flat panel displays, in particular to an inverter of a gate integrated drive circuit, a gate integrated driver and a driving method.

Background technique

In recent years, oxide thin film transistors have received great attention, which have the characteristics of high mobility, good consistency and stable electrical properties, and the preparation cost is low. Integrating the gate driving circuit on the display is beneficial to reduce the cost of the display device and realize the thin and light design of the display device with a narrow frame. However, only N-type oxide thin film transistors can be used in circuit design, and when the gate-source voltage is zero and the source-drain voltage is greater than zero, it cannot be completely turned off, and leakage current still flows.

In the gate drive circuit, the module circuit that provides the control signal of the pull-down transistor of the output stage is called an inverter. The traditional inverter is composed of a diode-connected transistor and a large-sized pull-down transistor. When the traditional inverter outputs a low level, there is a large DC loop, and due to the voltage drop on the pull-down transistor, the output of the inverter cannot reach the minimum level. The clock-controlled inverter, which consists of a pull-down transistor and a clock-controlled pull-up transistor, will bring large dynamic power consumption due to the use of a clock signal, and when the clock signal goes low, the pull-up transistor will be completely turned off. At this time, for the circuit using oxide TFTs, the pull-down transistor still has a leakage current flowing. In order to keep the output of the inverter at a high level, a larger capacitor is required to maintain the voltage, which increases the circuit size. area.

In a gate drive circuit, the more clock lines there are, the greater the load capacitance on the clock lines, the higher the frequency, the greater the dynamic power consumption, and if the clock loads differ greatly, it is easy to cause clock drift. Since the circuit maintains a low-level output time much longer than a high-level output time, multiple clocks will increase circuit noise and cause large fluctuations in the output voltage.

Contents of the invention

One of the objectives of the present invention is to provide an inverter for a gate integrated drive circuit, so as to overcome the above shortcomings and deficiencies of the inverter module in the gate integrated drive circuit, and to enhance the noise suppression capability.

The second object of the present invention is to provide a gate integrated driver including the above-mentioned inverter to achieve low power consumption, low noise and good anti-interference ability. work at higher frequencies. The circuit driving principle is simple, the clock control lines are few, the sequence is simple, the circuit structure is simple, and the occupied area is small.

The third object of the present invention is to provide a driving method for the above gate integrated driving circuit.

The object of the present invention is achieved through the following technical solutions:

The inverter of the gate integrated drive circuit includes transistors T1v, T2v, T3v, T4v, T5v and coupling capacitor C1v, the second electrode of the transistor T1v and the second electrode of T3v are connected to the positive level VDD, the gate of the transistor T1v and The first electrodes are all connected to the second electrode of the transistor T2v, the gate of the transistor T3v, the first electrode of the transistor T5v and one end of the capacitor C1v; the gate of the transistor T2v and the gate of the transistor T4v are connected to the control signal control, and the gate of the transistor T5v The feedback signal RSTv is connected to the second electrode, the first electrode of the transistor T2v and the first electrode of the transistor T4v are connected to the first negative level VSSL, the first electrode of the transistor T3v and the second electrode of T4v are connected to the other end of the capacitor C1v, forming an inverse Phaser output node QBv;

The first electrode is a source, and the second electrode is a drain; or

The second electrode is a source, and the first electrode is a drain.

The transistors are all N-type depletion thin film transistors.

An integrated gate driver, including a multi-level gate drive circuit unit; the first output signal COUT of the gate drive circuit unit of the current level is used as the input control signal VIH of the gate drive circuit unit of the next level and the gate drive of the upper level The feedback signal RST of the circuit unit, and the second output signal OUT are used as the driving signal of the scanning line and the input signal VIL of the gate driving circuit unit of the next stage;

Each gate drive circuit unit includes transistors T1~T18 and coupling capacitors C1~C3, an input control signal VIH, an input signal VIL, a clock signal CLK, a feedback signal RST, an initialization signal INIT, and a first output signal COUT , the second output signal OUT, the positive level VDD, the first negative level VSSL and the second negative level VSS;

The gate of the transistor T1, the gate of the transistor T7, and the gate of the transistor T9 are respectively connected to the input control signal VIH, the second electrode of the transistor T1 is connected to the input signal VIL, the first electrode of the transistor T1, and the second electrode of the transistor T2 1. The gate of the transistor T11 is connected to one end of the coupling capacitor C2 to form a node Q; the first electrode of the transistor T2 is connected to the second electrode of the transistor T3 and the second electrode of the transistor T4 to form a node B; the gate of the transistor T2 and the terminal of the transistor T3 The gate, the gate of the transistor T12, the gate of the transistor T14, the gate of the transistor T16, the first electrode of the transistor T8, the second electrode of the transistor T9, the second electrode of the transistor T10 and one end of the coupling capacitor C1 are connected to form a reverse phase device output node QB; the second electrode of the transistor T5, the second electrode of the transistor T8, the second electrode of the transistor T13, the second electrode of the transistor T15, and the second electrode of the transistor T18 are respectively connected to the positive level VDD, and the transistor The gate of T5, the first electrode of the transistor T5, the second electrode of the transistor T6, the second electrode of the transistor T7, the gate of the transistor T8, the first electrode of the transistor T17, the first electrode of the transistor T18 and the coupling capacitor C1 One end is connected to form a node A; the first electrode of the transistor T3, the first electrode of the transistor T6, the first electrode of the transistor T7, the first electrode of the transistor T9, the first electrode of the transistor T10, the first electrode of the transistor T12, The first electrode of the transistor T14 is connected to the first negative level VSSL; the gate of the transistor T4, the first electrode of the transistor T4, the gate of the transistor T6, the gate of the transistor T10, the gate of the transistor T13, the first electrode of the transistor T11 electrode, the second electrode of the transistor T12 is connected to the other end of the coupling capacitor C2 to form a node COUT; the second electrode of the transistor T11 is connected to the clock signal CLK; the first electrode of the transistor T13, the second electrode of the transistor T14, and the gate of the transistor T15 The first electrode of the transistor T15 is connected with the second electrode of T16 to form the node OUT; the first electrode of the transistor T16 is connected with the second negative level VSS; the gate of the transistor T17, the second The electrodes are connected to the feedback signal RST; the gate of the transistor T18 is connected to the initialization signal INIT; the other end of the coupling capacitor C3 is connected to the node OUT;

The first electrode is a source, and the second electrode is a drain; or

The second electrode is a source, and the first electrode is a drain.

The transistors are all N-type depletion thin film transistors.

The driving method of each level of gate driving circuit unit includes the following steps:

Initialization process: INIT signal is high level, the positive power supply charges point A to VDD, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the QB point is pulled up to VDD, and the transistors T2, T3, T12, T14 and T16 are turned on, the coupling capacitor C2 is discharged through the transistors T2, T3 and T12, and the coupling capacitor C3 is discharged through the transistors T14 and T16, the transistors T11, T13 and T15 are turned off, and the output signals COUT and OUT are respectively pulled down to the first A negative level VSSL and a second negative level VSS;

Signal writing stage: when the clock control line CLK is at low level, when the input control signal VIH and input signal VIL are at high level, transistors T1, T7 and T9 are turned on, and points A and QB are quickly pulled down to the first negative level VSSL, transistors T2, T3, T12, T14 and T16 are turned off, point Q starts to be charged to VDD, the charge is stored in the coupling capacitor C2, and the output signals COUT and OUT maintain the corresponding low level;

Drive signal output stage: input control signal VIH and input signal VIL change from high to low, because the negative level of the input control signal is lower than the input signal, so the transistor T1 is completely turned off, and the transistors T7 and T9 are turned off due to the input control signal becoming low Turn off, at this time, the clock control line CLK changes from low to high, due to the bootstrap effect of the coupling capacitor C2, the voltage at point Q rises higher, the node COUT quickly becomes VDD, and the voltage at point B rises, so that the transistor T2 is completely turned off Off, the charge of the coupling capacitor C2 is kept, and the transistors T6 and T10 are turned on at the same time, and the node QB continues to be kept at the first negative level; the voltage of the node COUT rises, so that the transistor T13 is turned on, and the DOUT point starts to charge, when the transistor T15 is turned on At the same time, due to the bootstrapping of the coupling capacitor C3, the node DOUT rises to a level higher than VDD, and because the gate-source voltage of the transistor T13 is equal, the potential of the DOUT point is in the drive signal It can be maintained in the output stage. At this time, the high level output by the OUT point reaches VDD, realizing the full swing output of the circuit;

Pull-down stage: the clock signal CLK changes from high to low, the node COUT of the gate drive circuit unit of this stage is also quickly pulled down to the first negative level, and the transistors T4, T6, T10 and T13 are quickly turned off. At the same time, due to the lower gate The output signal COUT of the pole drive circuit unit changes from low to high, the voltage at point A rises, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the voltage at point QB rises. Due to the bootstrap of the coupling capacitor C1, the voltage at point QB also rapidly Rising to close to VDD, at this time transistors T2, T3, T12, T14 and T16 are turned on, node Q, node COUT and node DOUT are pulled down to the first negative level, and node OUT is pulled down to the second negative level;

Low-level hold stage: the feedback signal RST is pulled low, and the voltage of node A starts to drop. Before the next input control signal VIH and input signal VIL arrive, the charge of capacitor C1 is kept, so the QB point can be kept at a high level stably. level, the transistors T2, T3, T12, T14 and T16 are turned on and kept in the deep linear region, and the output signals COUT and OUT are kept stable at low level.

An integrated gate driver, including a multi-level gate drive circuit unit; the first output signal COUT of the gate drive circuit unit of the current level is used as the input control signal VIH of the gate drive circuit unit of the next level and the gate drive of the upper level The feedback signal RST of the circuit unit, and the second output signal OUT are used as the driving signal of the scanning line and the input signal VIL of the gate driving circuit unit of the next stage;

Each gate drive circuit unit includes transistors T1~T17 and coupling capacitors C1~C3, an input control signal VIH, an input signal VIL, a clock signal CLK, a feedback signal RST, a first output signal COUT, and a second output signal OUT, positive level VDD, first negative level VSSL and second negative level VSS;

The gate of the transistor T1, the gate of the transistor T7, and the gate of the transistor T9 are respectively connected to the input control signal VIH, the second electrode of the transistor T1 is connected to the input signal VIL, the first electrode of the transistor T1, and the second electrode of the transistor T2 1. The gate of the transistor T11 is connected to one end of the coupling capacitor C2 to form a node Q; the first electrode of the transistor T2 is connected to the second electrode of the transistor T3 and the second electrode of the transistor T4 to form a node B; the gate of the transistor T2 and the terminal of the transistor T3 The gate, the gate of the transistor T12, the gate of the transistor T14, the gate of the transistor T16, the first electrode of the transistor T8, the second electrode of the transistor T9, the second electrode of the transistor T10 and one end of the coupling capacitor C1 are connected to form a reverse phase device output node QB; the second electrode of the transistor T5, the second electrode of the transistor T8, the second electrode of the transistor T13, the second electrode of the transistor T15 are connected to the positive level VDD, the gate of the transistor T5, the transistor T5 The first electrode, the second electrode of the transistor T6, the second electrode of the transistor T7, the gate of the transistor T8, the first electrode of the transistor T17 and the other end of the coupling capacitor C1 are connected to form node A; the first electrode of the transistor T3, The first electrode of the transistor T6, the first electrode of the transistor T7, the first electrode of the transistor T9, the first electrode of the transistor T10, the first electrode of the transistor T12, and the first electrode of the transistor T14 are connected to the first negative level VSSL; the transistor The gate of T4, the first electrode of the transistor T4, the gate of the transistor T6, the gate of the transistor T10, the gate of the transistor T13, the first electrode of the transistor T11, the second electrode of the transistor T12 are connected to the other end of the coupling capacitor C2 , forming a node COUT; the second electrode of the transistor T11 is connected to the clock signal CLK; the first electrode of the transistor T13, the second electrode of the transistor T14, the gate of the transistor T15 and one end of the coupling capacitor C3 are connected to form a node DOUT; the second electrode of the transistor T15 One electrode is connected to the second electrode of T16 to form a node OUT; the first electrode of the transistor T16 is connected to the second negative level VSS; the gate and second electrode of the transistor T17 are connected to the feedback signal RST; the other end of the coupling capacitor C3 is connected to the node OUT connect;

The first electrode is a source, and the second electrode is a drain; or

The second electrode is a source, and the first electrode is a drain.

The transistors are all N-type depletion thin film transistors.

The driving method of each level of gate driving circuit unit includes the following steps:

Signal writing stage: when the clock control line CLK is at low level, when the input control signal VIH and input signal VIL are at high level, transistors T1, T7 and T9 are turned on, and points A and QB are quickly pulled down to the first negative level VSSL, transistors T2, T3, T12, T14 and T16 are turned off, point Q starts to be charged to VDD, the charge is stored in the coupling capacitor C2, and the output signals COUT and OUT maintain the corresponding low level;

Drive signal output stage: input control signal VIH and input signal VIL change from high to low, because the negative level of the input control signal is lower than the input signal, so the transistor T1 is completely turned off, and the transistors T7 and T9 are turned off due to the input control signal becoming low Turn off, at this time, the clock control line CLK changes from low to high, due to the bootstrap effect of the coupling capacitor C2, the voltage at point Q rises higher, the node COUT quickly becomes VDD, and the voltage at point B rises, so that the transistor T2 is completely turned off Off, the charge of the coupling capacitor C2 is kept, and the transistors T6 and T10 are turned on at the same time, and the node QB continues to be kept at the first negative level; the voltage of the node COUT rises, so that the transistor T13 is turned on, and the DOUT point starts to charge, when the transistor T15 is turned on At the same time, due to the bootstrapping of the coupling capacitor C3, the node DOUT rises to a level higher than VDD, and because the gate-source voltage of the transistor T13 is equal, the potential of the DOUT point is in the drive signal It can be maintained in the output stage. At this time, the high level output by the OUT point reaches VDD, realizing the full swing output of the circuit;

Pull-down stage: the clock signal CLK changes from high to low, the node COUT of the gate drive circuit unit of this stage is also quickly pulled down to the first negative level, and the transistors T4, T6, T10 and T13 are quickly turned off. At the same time, due to the lower gate The output signal COUT of the pole drive circuit unit changes from low to high, the voltage at point A rises, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the voltage at point QB rises. Due to the bootstrap of the coupling capacitor C1, the voltage at point QB also rapidly Rising to close to VDD, at this time transistors T2, T3, T12, T14 and T16 are turned on, node Q, node COUT and node DOUT are pulled down to the first negative level, and node OUT is pulled down to the second negative level;

Low-level hold stage: the feedback signal RST is pulled low, and the voltage of node A starts to drop. Before the next input control signal VIH and input signal VIL arrive, the charge of capacitor C1 is kept, so the QB point can be kept at a high level stably. level, the transistors T2, T3, T12, T14 and T16 are turned on and kept in the deep linear region, and the output signals COUT and OUT are kept stable at low level.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

(1) The inverter of the present invention is made up of transistor T1v-T5v and electric capacity C1v, by utilizing the leakage current of transistor T1v to make the electric charge of electric capacity C1v be kept during the low level of gate drive circuit, make the inverter in After the feedback signal ends, it can still output a higher level, and at the same time, the bootstrap function of the capacitor C1v is used to enable the output of the inverter to switch quickly, meet the high frequency requirements, and reduce the power consumption of the gate integrated drive circuit.

(2) The gate integrated drive circuit of the present invention adopts the inverter of the present invention, which greatly reduces the DC power consumption of the traditional diode-connected inverter module, and simultaneously avoids the AC power consumption of the clock-controlled inverter, And each gate integrated circuit only needs one clock line, which effectively reduces the capacitive load of the clock line, significantly reduces the power consumption of the circuit, and reduces the impact of clock jumps on the circuit; realizes low power consumption, low noise and good Anti-interference ability, the output stage pull-up transistor and the output level jump of the inverter are relatively rapid, and can work at a higher frequency. The circuit driving principle is simple, the clock control lines are few, the sequence is simple, the circuit structure is simple, and the occupied area is small.

Description of drawings

FIG. 1 is a circuit diagram of an inverter of a gate integrated drive circuit according to Embodiment 1 of the present invention.

FIG. 2 is a cascaded block diagram of gate integrated drive circuit units according to Embodiment 1 of the present invention.

FIG. 3 is a circuit diagram of a gate integrated driving circuit unit according to Embodiment 1 of the present invention.

FIG. 4 is a timing diagram of the gate integrated drive circuit according to Embodiment 1 of the present invention.

FIG. 5 is a circuit diagram of a gate integrated driving circuit unit according to Embodiment 2 of the present invention.

detailed description

The present invention will be described in further detail below in conjunction with the examples, but the embodiments of the present invention are not limited thereto.

Example 1

As shown in FIG. 1 , the inverter of the integrated gate drive circuit of this embodiment includes transistors T1v, T2v, T3v, T4v, T5v and coupling capacitor C1v, and the drain of transistor T1v is connected to the positive electrode of T3v. Flat VDD, the gate and source of transistor T1v are connected to the drain of transistor T2v, the gate of transistor T3v, the source of transistor T5v and one end of capacitor C1v; the gate of transistor T2v and the gate of transistor T4v are connected to the control signal control , the gate and drain of the transistor T5v are connected to the feedback signal RSTv, the source of the transistor T2v and the source of the transistor T4v are connected to the first negative level VSSL, the source of the transistor T3v and the drain of the transistor T4v are connected to the other end of the capacitor C1v, forming Inverter output node QBv.

The transistors are all N-type depletion thin film transistors.

The working process of the inverter of the present embodiment is as follows:

When the control signal control is at a high level and the feedback signal RSTv is at a low level, the inverter output node QBv is quickly pulled down to the first negative level VSSL; when the control signal control is at a low level and the feedback signal RSTv is at a high level, the The inverter output node QBv is pulled high to the positive level VDD. When the control signal control and the feedback signal RSTv are at low level at the same time, the leakage current of the large-sized transistor T1v is used to keep the charge of the capacitor C1v, and the voltage of the output node QB of the inverter is kept slightly lower than the positive level VDD.

Example 2

As shown in Figure 2, the integrated gate driver of this embodiment includes multi-level gate drive circuit units: a first-level gate drive circuit unit 11, a second-level gate drive circuit unit 12, and a third-level gate drive circuit unit. The circuit unit 13, the gate drive circuit unit 14 of the fourth stage, the gate drive circuit unit of each stage includes two input terminals VIH and VIL, three power supply terminals VDD, VSSL and VSS, wherein the voltage of VSSL is more negative than VSS, A clock signal input terminal CLK, the highest level of the clock signal is VDD, the lowest level is VSSL, two output terminals COUT and OUT, an initialization terminal INIT and a feedback terminal RST.

As shown in Figure 3, each gate drive circuit unit includes transistors T1~T18 and coupling capacitors C1~C3, an input control signal VIH, an input signal VIL, a clock signal CLK, a feedback signal RST, and an initialization signal INIT , the first output signal COUT, the second output signal OUT, the positive level VDD, the first negative level VSSL and the second negative level VSS.

The gate of the transistor T1, the gate of the transistor T7, and the gate of the transistor T9 are respectively connected to the input control signal VIH, the drain of the transistor T1 is connected to the input signal VIL, the source of the transistor T1, the drain of the transistor T2, and the transistor T11 The gate of the transistor T2 is connected to one end of the coupling capacitor C2 to form a node Q, the source of the transistor T2 is connected to the drain of the transistor T3 and the drain of the transistor T4 to form a node B, the gate of the transistor T2, the gate of the transistor T3, and the gate of the transistor T12 The gate, the gate of the transistor T14, the gate of the transistor T16, the source of the transistor T8, the drain of the transistor T9, the drain of the transistor T10 and one end of the coupling capacitor C1 are connected to form an inverter output node QB; the transistor T5 The drain, the drain of the transistor T8, the drain of the transistor T13, the drain of the transistor T15, and the drain of the transistor T18 are respectively connected to the positive level VDD, the gate of the transistor T5, the source of the transistor T5, and the transistor T6 The drain, the drain of the transistor T7, the gate of the transistor T8, the source of the transistor T17, the source of the transistor T18 and the other end of the coupling capacitor C1 are connected to form node A; the source of the transistor T3 and the source of the transistor T6 , the source of the transistor T7, the source of the transistor T9, the source of the transistor T10, the source of the transistor T12, and the source of the transistor T14 are connected to the first negative level VSSL; the gate of the transistor T4, the source of the transistor T4, The gate of the transistor T6, the gate of the transistor T10, the gate of the transistor T13, the source of the transistor T11, the drain of the transistor T12 and the other end of the coupling capacitor C2 are connected to form a node COUT; the drain of the transistor T11 is connected to the clock signal CLK The source of the transistor T13, the drain of the transistor T14, the gate of the transistor T15 and one end of the coupling capacitor C3 are connected to form a node DOUT; the source of the transistor T15 is connected to the drain of T16 to form a node OUT; the source of the transistor T16 is connected to the first end of the coupling capacitor C3 The two negative levels are connected to VSS; the gate of transistor T17 and the drain of transistor T17 are connected to feedback signal RST; the gate of transistor T18 is connected to initialization signal INIT; the other end of coupling capacitor C3 is connected to node OUT.

The transistors are all N-type depletion thin film transistors.

In the gate integrated driving circuit of this embodiment, the driving method of each level of gate driving circuit unit includes the following steps:

Initialization process: INIT signal is high level, the positive power supply charges point A to VDD, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the QB point is pulled up to VDD, and the transistors T2, T3, T12, T14 and T16 are turned on, the coupling capacitor C2 is discharged through the transistors T2, T3 and T12, and the coupling capacitor C3 is discharged through the transistors T14 and T16, the transistors T11, T13 and T15 are turned off, and the output signals COUT and OUT are respectively pulled down to the first A negative level VSSL and a second negative level VSS; prevent the circuit from entering an unknown state. After the circuit enters a stable state, the initialization signal becomes low. After that, unless the circuit needs to be set, the initialization signal can remain low.

Signal writing stage: when the clock control line CLK is at low level, when the input control signal VIH and input signal VIL are at high level, transistors T1, T7 and T9 are turned on, and points A and QB are quickly pulled down to the first negative level VSSL, transistors T2, T3, T12, T14 and T16 are turned off, point Q starts to be charged to VDD, the charge is stored in the coupling capacitor C2, and the output signals COUT and OUT maintain the corresponding low level;

Drive signal output stage: input control signal VIH and input signal VIL change from high to low, because the negative level of the input control signal is lower than the input signal, so the transistor T1 is completely turned off, and the transistors T7 and T9 are turned off due to the input control signal becoming low Turn off, at this time, the clock control line CLK changes from low to high, due to the bootstrap effect of the coupling capacitor C2, the voltage at point Q rises higher, the node COUT quickly becomes VDD, and the voltage at point B rises, so that the transistor T2 is completely turned off Off, the charge of the coupling capacitor C2 is kept, and the transistors T6 and T10 are turned on at the same time, and the node QB continues to be kept at the first negative level; the voltage of the node COUT rises, so that the transistor T13 is turned on, and the DOUT point starts to charge, when the transistor T15 is turned on At the same time, due to the bootstrapping of the coupling capacitor C3, the node DOUT rises to a level higher than VDD, and because the gate-source voltage of the transistor T13 is equal, the potential of the DOUT point is in the drive signal It can be maintained in the output stage. At this time, the high level output by the OUT point reaches VDD, realizing the full swing output of the circuit;

Pull-down stage: the clock signal CLK changes from high to low, the node COUT of the gate drive circuit unit of this stage is also quickly pulled down to the first negative level, and the transistors T4, T6, T10 and T13 are quickly turned off. At the same time, due to the lower gate The output signal COUT of the pole drive circuit unit changes from low to high, the voltage at point A rises, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the voltage at point QB rises. Due to the bootstrap of the coupling capacitor C1, the voltage at point QB also rapidly Rising to close to VDD, at this time transistors T2, T3, T12, T14 and T16 are turned on, node Q, node COUT and node DOUT are pulled down to the first negative level, and node OUT is pulled down to the second negative level;

Low-level hold stage: the feedback signal RST is pulled low, and the voltage of node A starts to drop. Before the next input control signal VIH and input signal VIL arrive, the charge of capacitor C1 is kept, so the QB point can be kept at a high level stably. level, the transistors T2, T3, T12, T14 and T16 are turned on and kept in the deep linear region, and the output signals COUT and OUT are kept stable at low level.

The timing diagram of the gate integrated driving circuit of this embodiment is shown in FIG. 4 .

The input signals VIH and VIL of the first-stage gate drive circuit unit can be provided by the same input signal with a swing of VDD-VSSL, and then the output signal COUT of each stage gate drive circuit unit is the gate drive circuit of the next stage. The unit provides the input control signal VIH, the output signal OUT provides the input signal VIL for the gate drive circuit unit of the next stage, and the output signal COUT of the gate drive circuit unit of each stage provides the feedback signal RST for the unit circuit of the previous stage, and finally The feedback signal of the first-level gate drive circuit unit can be provided by the initialization signal INIT, or the inverter of the last-level gate drive circuit unit can turn off transistors T6, T7, T9 and T10, so that the node QB output is slightly The level lower than the positive level VDD makes the output signal OUT of the gate driving circuit pulled down to the second negative level VSS.

The gate integrated drive circuit is controlled by cascaded clock signals CLK1 and CLK2, both of which are square waves with a duty cycle of 50%, and CLK1 lags behind CLK2 by half a clock period. ,

The first-level gate drive circuit unit 11 of the gate integrated driver clock signal input terminal CLK is connected to the clock control line CLK1, and the output signals COUT and OUT generated when CLK1 becomes high level are the next-level unit gate drive circuit unit The input control signal VIH and the input signal VIL are provided, so the signal input terminal CLK of the second-level gate drive circuit unit is connected to the second clock control line CLK2, and the signal input terminal CLK of the third-level gate drive circuit unit is connected to the first clock control line CLK1 , and so on. Two clock signal control lines constitute a driving mode in the form of a pipeline, and each gate drive circuit unit only needs one clock signal control line. The clock signal input terminal of the first scan drive circuit 11 is CLK1, and the input control signal VIH and the input signal VIL first jumps to high level, and maintains a pulse time. When the next pulse time arrives, the input signal jumps from high to low, and the clock control line CLK1 jumps from low level to high level, and maintains a pulse. Time, output high level, when the next pulse time arrives, the clock control line CLK1 changes from high to low, and the output also changes from high to low.

The integrated gate driver can design the number of stages of integrated gate drive circuit units according to needs, and connect them according to the above connection relationship. The first output signal COUT of the gate drive circuit unit of this stage is used as the input control signal VIH of the gate drive circuit unit of the next stage and the feedback signal RST of the gate drive circuit unit of the previous stage, and the second output signal OUT is used as the input signal of the scanning line The driving signal and the input signal VIL of the gate driving circuit unit of the next stage.

In the gate integrated drive circuit of this embodiment, because the load capacitance on the clock signal CLK is very small, and because the pipeline sequence is adopted, the clock frequency is twice as slow as the circuit operating frequency, and there is only one clock control line for each stage of the circuit, so it can be achieve very low dynamic power consumption. And because of the new inverter module circuit proposed in this paper, the static leakage current generated is very small, and the inverter does not need a clock signal to control, reducing dynamic power consumption, so the overall circuit can achieve very low power consumption.

Example 3

Compared with the embodiment 2, the integrated gate driving circuit of this embodiment removes the eighteenth transistor and omits the initialization process. Due to the new inverter module circuit used in the gate drive circuit, the QB point can automatically maintain a stable voltage slightly lower than VDD even if there is no initialization process. Therefore, the output signal of the circuit can still be maintained in the absence of input. stable low level.

As shown in Figure 5, the integrated gate drive circuit of this embodiment includes a multi-level gate drive circuit unit; the first output signal COUT of the gate drive circuit unit of this level is used as the input control signal of the gate drive circuit unit of the next level VIH and the feedback signal RST of the gate drive circuit unit of the upper stage, the second output signal OUT is used as the drive signal of the scanning line and the input signal VIL of the gate drive circuit unit of the next stage;

Each gate drive circuit unit includes transistors T1~T17 and coupling capacitors C1~C3, an input control signal VIH, an input signal VIL, a clock signal CLK, a feedback signal RST, a first output signal COUT, and a second output signal OUT, positive level VDD, first negative level VSSL and second negative level VSS;

The gate of the transistor T1, the gate of the transistor T7, and the gate of the transistor T9 are respectively connected to the input control signal VIH, the drain of the transistor T1 is connected to the input signal VIL, the source of the transistor T1, the drain of the transistor T2, and the transistor T11 The gate of the transistor T2 is connected to one end of the coupling capacitor C2 to form a node Q, the source of the transistor T2 is connected to the drain of the transistor T3 and the drain of the transistor T4 to form a node B, the gate of the transistor T2, the gate of the transistor T3, and the gate of the transistor T12 The gate, the gate of the transistor T14, the gate of the transistor T16, the source of the transistor T8, the drain of the transistor T9, the drain of the transistor T10 and one end of the coupling capacitor C1 are connected to form an inverter output node QB; the transistor T5 The drain, the drain of the transistor T8, the drain of the transistor T13, and the drain of the transistor T15 are connected to the positive level VDD, the gate of the transistor T5, the source of the transistor T5, the drain of the transistor T6, and the drain of the transistor T7 Pole, the gate of transistor T8, the source of transistor T17 and the other end of coupling capacitor C1 are connected to form node A; the source of transistor T3, the source of transistor T6, the source of transistor T7, the source of transistor T9, The source of the transistor T10, the source of the transistor T12, and the source of the transistor T14 are connected to the first negative level VSSL; the gate of the transistor T4, the first electrode of the transistor T4, the gate of the transistor T6, the gate of the transistor T10, The gate of the transistor T13, the source of the transistor T11, the drain of the transistor T12 are connected to the other end of the coupling capacitor C2 to form a node COUT; the drain of the transistor T11 is connected to the clock signal CLK; the source of the transistor T13, the drain of the transistor T14 The gate of the transistor T15 is connected to one end of the coupling capacitor C3 to form a node DOUT; the source of the transistor T15 is connected to the drain of T16 to form a node OUT; the source of the transistor T16 is connected to the second negative level VSS; the gate of the transistor T17, the drain The pole is connected to the feedback signal RST; the other end of the coupling capacitor C3 is connected to the node OUT.

The transistors are all N-type depletion thin film transistors.

In the gate integrated drive circuit, the transistors T5, T6, T7, T8, T9, T10, T17 and the coupling capacitor C1 constitute the inverter of the present invention, wherein the transistor T5 is much larger than the size of the transistors T6, T7 and T17 In this way, at the moment when the circuit is powered on, the current flowing through the transistor T5 is greater than the sum of the leakage currents of the transistors T6, T7 and T17, so the voltage of the node A will rise slowly. When the voltage reaches a specific voltage value, the current flowing through transistor T5 is equal to the current of transistor T6, T7 and T17, and the voltage at point A remains stable. When affected by noise, T5 will be The current will be automatically adjusted according to the voltage at point A to keep the charge of capacitor C1 stable, so that node A can be stabilized at a specific voltage value, so node QB can also be kept at a stable voltage.

The driving method of the integrated gate driving circuit of this embodiment, the driving method of each level of gate driving circuit unit includes the following steps:

Signal writing stage: when the clock control line CLK is at low level, when the input control signal VIH and input signal VIL are at high level, transistors T1, T7 and T9 are turned on, and points A and QB are quickly pulled down to the first negative level VSSL, transistors T2, T3, T12, T14 and T16 are turned off, point Q starts to be charged to VDD, the charge is stored in the coupling capacitor C2, and the output signals COUT and OUT maintain the corresponding low level;

Drive signal output stage: input control signal VIH and input signal VIL change from high to low, because the negative level of the input control signal is lower than the input signal, so the transistor T1 is completely turned off, and the transistors T7 and T9 are turned off due to the input control signal becoming low Turn off, at this time, the clock control line CLK changes from low to high, due to the bootstrap effect of the coupling capacitor C2, the voltage at point Q rises higher, the node COUT quickly becomes VDD, and the voltage at point B rises, so that the transistor T2 is completely turned off Off, the charge of the coupling capacitor C2 is kept, and the transistors T6 and T10 are turned on at the same time, and the node QB continues to be kept at the first negative level; the voltage of the node COUT rises, so that the transistor T13 is turned on, and the DOUT point starts to charge, when the transistor T15 is turned on At the same time, due to the bootstrapping of the coupling capacitor C3, the node DOUT rises to a level higher than VDD, and because the gate-source voltage of the transistor T13 is equal, the potential of the DOUT point is in the drive signal It can be maintained in the output stage. At this time, the high level output by the OUT point reaches VDD, realizing the full swing output of the circuit;

Pull-down stage: the clock signal CLK changes from high to low, the node COUT of the gate drive circuit unit of this stage is also quickly pulled down to the first negative level, and the transistors T4, T6, T10 and T13 are quickly turned off. At the same time, due to the lower gate The output signal COUT of the pole drive circuit unit changes from low to high, the voltage at point A rises, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the voltage at point QB rises. Due to the bootstrap of the coupling capacitor C1, the voltage at point QB also rapidly Rising to close to VDD, at this time transistors T2, T3, T12, T14 and T16 are turned on, node Q, node COUT and node DOUT are pulled down to the first negative level, and node OUT is pulled down to the second negative level;

Low-level hold stage: the feedback signal RST is pulled low, and the voltage of node A starts to drop. Before the next input control signal VIH and input signal VIL arrive, the charge of capacitor C1 is kept, so the QB point can be kept at a high level stably. level, the transistors T2, T3, T12, T14 and T16 are turned on and kept in the deep linear region, and the output signals COUT and OUT are kept stable at low level.

In the above embodiments, the source and drain of the transistor can be interchanged.

The above-mentioned embodiment is a preferred implementation mode of the present invention, but the implementation mode of the present invention is not limited by the above-mentioned embodiment, such as the source and drain of the transistor can be adjusted, etc., and any other does not deviate from the spirit of the present invention Changes, modifications, substitutions, combinations, and simplifications made under the essence and principle should all be equivalent replacement methods, and all are included in the protection scope of the present invention.

Claims (6)

1. An integrated gate driver, characterized in that it includes a multi-level gate drive circuit unit; the first output signal COUT of the gate drive circuit unit of this level is used as the input control signal VIH and the input control signal VIH of the gate drive circuit unit of the next level The feedback signal RST of the gate drive circuit unit of the upper stage, and the second output signal OUT are used as the drive signal of the scanning line and the input signal VIL of the gate drive circuit unit of the next stage; Each gate drive circuit unit includes transistors T1~T18 and coupling capacitors C1~C3, an input control signal VIH, an input signal VIL, a clock signal CLK, a feedback signal RST, an initialization signal INIT, and a first output signal COUT , the second output signal OUT, the positive level VDD, the first negative level VSSL and the second negative level VSS; The gate of the transistor T1, the gate of the transistor T7, and the gate of the transistor T9 are respectively connected to the input control signal VIH, the second electrode of the transistor T1 is connected to the input signal VIL, the first electrode of the transistor T1, and the second electrode of the transistor T2 1. The gate of the transistor T11 is connected to one end of the coupling capacitor C2 to form a node Q; the first electrode of the transistor T2 is connected to the second electrode of the transistor T3 and the second electrode of the transistor T4 to form a node B; the gate of the transistor T2 and the terminal of the transistor T3 The gate, the gate of the transistor T12, the gate of the transistor T14, the gate of the transistor T16, the first electrode of the transistor T8, the second electrode of the transistor T9, the second electrode of the transistor T10 and one end of the coupling capacitor C1 are connected to form a reverse phase device output node QB; the second electrode of the transistor T5, the second electrode of the transistor T8, the second electrode of the transistor T13, the second electrode of the transistor T15, and the second electrode of the transistor T18 are respectively connected to the positive level VDD, and the transistor The gate of T5, the first electrode of the transistor T5, the second electrode of the transistor T6, the second electrode of the transistor T7, the gate of the transistor T8, the first electrode of the transistor T17, the first electrode of the transistor T18 and the coupling capacitor C1 One end is connected to form a node A; the first electrode of the transistor T3, the first electrode of the transistor T6, the first electrode of the transistor T7, the first electrode of the transistor T9, the first electrode of the transistor T10, the first electrode of the transistor T12, The first electrode of the transistor T14 is connected to the first negative level VSSL; the gate of the transistor T4, the first electrode of the transistor T4, the gate of the transistor T6, the gate of the transistor T10, the gate of the transistor T13, the first electrode of the transistor T11 electrode, the second electrode of the transistor T12 is connected to the other end of the coupling capacitor C2 to form a node COUT; the second electrode of the transistor T11 is connected to the clock signal CLK; the first electrode of the transistor T13, the second electrode of the transistor T14, and the gate of the transistor T15 The first electrode of the transistor T15 is connected with the second electrode of T16 to form the node OUT; the first electrode of the transistor T16 is connected with the second negative level VSS; the gate of the transistor T17, the second The electrodes are connected to the feedback signal RST; the gate of the transistor T18 is connected to the initialization signal INIT; the other end of the coupling capacitor C3 is connected to the node OUT; The first electrode is a source, and the second electrode is a drain; or The second electrode is a source, and the first electrode is a drain. 2. The integrated gate driver according to claim 1, wherein the transistors are all N-type depletion-type thin film transistors. 3. The driving method of the gate integrated driver according to claim 1 or 2, wherein the driving method of each level of gate driving circuit unit comprises the following steps: Initialization process: INIT signal is high level, the positive power supply charges point A to VDD, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the QB point is pulled up to VDD, and the transistors T2, T3, T12, T14 and T16 are turned on, the coupling capacitor C2 is discharged through the transistors T2, T3 and T12, and the coupling capacitor C3 is discharged through the transistors T14 and T16, the transistors T11, T13 and T15 are turned off, and the output signals COUT and OUT are respectively pulled down to the first A negative level VSSL and a second negative level VSS; Signal writing stage: when the clock signal CLK is at low level, when the input control signal VIH and input signal VIL are at high level, transistors T1, T7 and T9 are turned on, and points A and QB are quickly pulled down to the first negative level VSSL , the transistors T2, T3, T12, T14 and T16 are turned off, the Q point starts to be charged to VDD, the charge is stored in the coupling capacitor C2, and the output signals COUT and OUT maintain the corresponding low level; Drive signal output stage: input control signal VIH and input signal VIL change from high to low, because the negative level of the input control signal is lower than the input signal, so the transistor T1 is completely turned off, and the transistors T7 and T9 are turned off due to the input control signal becoming low Turn off, at this time, the clock signal CLK changes from low to high, due to the bootstrap effect of the coupling capacitor C2, the voltage at point Q rises higher, the node COUT quickly becomes VDD, and the voltage at point B rises, so that the transistor T2 is completely turned off , the charge of the coupling capacitor C2 is kept, while the transistors T6 and T10 are turned on, and the node QB continues to be kept at the first negative level; the voltage of the node COUT rises, so that the transistor T13 is turned on, and the DOUT point starts to charge, when the transistor T15 is turned on At the same time, due to the bootstrapping of the coupling capacitor C3, the node DOUT rises to a level higher than VDD, and because the gate-source voltage of the transistor T13 is equal, the potential of the DOUT point is in the drive signal output It can be maintained in the stage, at this time, the high level of the OUT point output reaches VDD, and the full swing output of the circuit is realized; Pull-down stage: the clock signal CLK changes from high to low, the node COUT of the gate drive circuit unit of this stage is also quickly pulled down to the first negative level, and the transistors T4, T6, T10 and T13 are quickly turned off. At the same time, due to the lower gate The output signal COUT of the pole drive circuit unit changes from low to high, the voltage at point A rises, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the voltage at point QB rises. Due to the bootstrap of the coupling capacitor C1, the voltage at point QB also rapidly Rising to close to VDD, at this time transistors T2, T3, T12, T14 and T16 are turned on, node Q, node COUT and node DOUT are pulled down to the first negative level, and node OUT is pulled down to the second negative level; Low-level hold stage: the feedback signal RST is pulled low, and the voltage of node A starts to drop. Before the next input control signal VIH and input signal VIL arrive, the charge of capacitor C1 is kept, so the QB point can be kept at a high level stably. level, the transistors T2, T3, T12, T14 and T16 are turned on and kept in the deep linear region, and the output signals COUT and OUT are kept stable at low level. 4. An integrated gate driver, characterized in that it includes a multi-level gate drive circuit unit; the first output signal COUT of the gate drive circuit unit of this level is used as the input control signal VIH and the input control signal VIH of the gate drive circuit unit of the next level The feedback signal RST of the gate drive circuit unit of the upper stage, and the second output signal OUT are used as the drive signal of the scanning line and the input signal VIL of the gate drive circuit unit of the next stage; Each gate drive circuit unit includes transistors T1~T17 and coupling capacitors C1~C3, an input control signal VIH, an input signal VIL, a clock signal CLK, a feedback signal RST, a first output signal COUT, and a second output signal OUT, positive level VDD, first negative level VSSL and second negative level VSS; The gate of the transistor T1, the gate of the transistor T7, and the gate of the transistor T9 are respectively connected to the input control signal VIH, the second electrode of the transistor T1 is connected to the input signal VIL, the first electrode of the transistor T1, and the second electrode of the transistor T2 1. The gate of the transistor T11 is connected to one end of the coupling capacitor C2 to form a node Q; the first electrode of the transistor T2 is connected to the second electrode of the transistor T3 and the second electrode of the transistor T4 to form a node B; the gate of the transistor T2 and the terminal of the transistor T3 The gate, the gate of the transistor T12, the gate of the transistor T14, the gate of the transistor T16, the first electrode of the transistor T8, the second electrode of the transistor T9, the second electrode of the transistor T10 and one end of the coupling capacitor C1 are connected to form a reverse phase device output node QB; the second electrode of the transistor T5, the second electrode of the transistor T8, the second electrode of the transistor T13, the second electrode of the transistor T15 are connected to the positive level VDD, the gate of the transistor T5, the transistor T5 The first electrode, the second electrode of the transistor T6, the second electrode of the transistor T7, the gate of the transistor T8, the first electrode of the transistor T17 and the other end of the coupling capacitor C1 are connected to form node A; the first electrode of the transistor T3, The first electrode of the transistor T6, the first electrode of the transistor T7, the first electrode of the transistor T9, the first electrode of the transistor T10, the first electrode of the transistor T12, and the first electrode of the transistor T14 are connected to the first negative level VSSL; the transistor The gate of T4, the first electrode of the transistor T4, the gate of the transistor T6, the gate of the transistor T10, the gate of the transistor T13, the first electrode of the transistor T11, the second electrode of the transistor T12 are connected to the other end of the coupling capacitor C2 , forming a node COUT; the second electrode of the transistor T11 is connected to the clock signal CLK; the first electrode of the transistor T13, the second electrode of the transistor T14, the gate of the transistor T15 and one end of the coupling capacitor C3 are connected to form a node DOUT; the second electrode of the transistor T15 One electrode is connected to the second electrode of T16 to form a node OUT; the first electrode of the transistor T16 is connected to the second negative level VSS; the gate and second electrode of the transistor T17 are connected to the feedback signal RST; the other end of the coupling capacitor C3 is connected to the node OUT connect; The first electrode is a source, and the second electrode is a drain; or The second electrode is a source, and the first electrode is a drain. 5. The integrated gate driver according to claim 4, wherein the transistors are all N-type depletion-type thin film transistors. 6. The driving method of the gate integrated driver according to claim 4 or 5, wherein the driving method of each level of gate driving circuit unit comprises the following steps: Signal writing stage: when the clock signal CLK is at low level, when the input control signal VIH and input signal VIL are at high level, transistors T1, T7 and T9 are turned on, and points A and QB are quickly pulled down to the first negative level VSSL , the transistors T2, T3, T12, T14 and T16 are turned off, the Q point starts to be charged to VDD, the charge is stored in the coupling capacitor C2, and the output signals COUT and OUT maintain the corresponding low level; Drive signal output stage: input control signal VIH and input signal VIL change from high to low, because the negative level of the input control signal is lower than the input signal, so the transistor T1 is completely turned off, and the transistors T7 and T9 are turned off due to the input control signal becoming low Turn off, at this time, the clock signal CLK changes from low to high, due to the bootstrap effect of the coupling capacitor C2, the voltage at point Q rises higher, the node COUT quickly becomes VDD, and the voltage at point B rises, so that the transistor T2 is completely turned off , the charge of the coupling capacitor C2 is kept, while the transistors T6 and T10 are turned on, and the node QB continues to be kept at the first negative level; the voltage of the node COUT rises, so that the transistor T13 is turned on, and the DOUT point starts to charge, when the transistor T15 is turned on At the same time, due to the bootstrapping of the coupling capacitor C3, the node DOUT rises to a level higher than VDD, and because the gate-source voltage of the transistor T13 is equal, the potential of the DOUT point is in the drive signal output It can be maintained in the stage, at this time, the high level of the OUT point output reaches VDD, and the full swing output of the circuit is realized; Pull-down stage: the clock signal CLK changes from high to low, the node COUT of the gate drive circuit unit of this stage is also quickly pulled down to the first negative level, and the transistors T4, T6, T10 and T13 are quickly turned off. At the same time, due to the lower gate The output signal COUT of the pole drive circuit unit changes from low to high, the voltage at point A rises, the charge is stored in the coupling capacitor C1, the transistor T8 is turned on, and the voltage at point QB rises. Due to the bootstrap of the coupling capacitor C1, the voltage at point QB also rapidly Rising to close to VDD, at this time transistors T2, T3, T12, T14 and T16 are turned on, node Q, node COUT and node DOUT are pulled down to the first negative level, and node OUT is pulled down to the second negative level; Low-level hold stage: the feedback signal RST is pulled low, and the voltage of node A starts to drop. Before the next input control signal VIH and input signal VIL arrive, the charge of capacitor C1 is kept, so the QB point can be kept at a high level stably. level, the transistors T2, T3, T12, T14 and T16 are turned on and kept in the deep linear region, and the output signals COUT and OUT are kept stable at low level.