CN104615557A - Multi-core fine grit synchronous DMA transmission method used for GPDSP - Google Patents

Abstract

A multi-core fine-grained synchronous DMA transmission method for GPDSP, each direct storage access component DMA participating in the multi-core fine-grained synchronous transmission will send a local frame transmission end signal to the global synchronization register after transmitting a frame of data; Integrate the end signals from multiple cores into a global frame transmission end signal; each direct storage access component DMA checks whether the core list parameters configured by itself to participate in synchronous transmission are consistent with the received global frame transmission end signal; if consistent, It indicates that all DMAs participating in the direct storage access component have completed the transmission of the previous frame of data, and can start moving the data of the next frame; , these participating direct memory access components DMA continue to wait until the matching is successful. The invention can effectively improve the row hit rate of the SDRAM, significantly improve the utilization rate of memory access bandwidth and DMA transmission efficiency.

Description

A DMA transmission method for multi-core fine-grained synchronization for GPDSP

technical field

The present invention mainly relates to the general purpose digital signal processor (General Purpose Digital Signal Processor, GPDSP) field, specifically refers to a kind of multi-core fine-grained synchronous transmission method suitable for direct memory access component DMA (Direct Memory Access, DMA) in GPDSP, with Improve DDR write access efficiency.

Background technique

General purpose digital signal processor GPDSP (General Purpose Digital Signal Processor, GPDSP) is a new architecture that can not only maintain the basic characteristics of embedded DSP and the advantages of high performance and low power consumption, but also efficiently support general scientific computing. It can simultaneously Provide efficient support for 64-bit high-performance computers and embedded high-precision signal processing. The application fields of GPDSP include scientific computing, communication voice, graphics and images, and wearable devices, etc. These fields put forward higher requirements for the system performance of GPDSP chips. However, the "storage wall" problem caused by the serious imbalance between GPDSP computing performance and memory access performance has become the main obstacle to continue to improve GPDSP processing performance.

Direct memory access (Direct Memory Access, DMA) is an important technology to alleviate the "storage wall" problem in the GPDSP structure. DMA can quickly perform in-core storage space and out-of-core storage in the background without the intervention of the computing core. Data movement between storage spaces. DMA overlaps the access operation of the external storage space with the calculation operation of the program, which to a certain extent hides the impact of the memory access operation on the calculation performance. In addition, DMA also supports a variety of flexible and configurable transmission modes, which can meet the needs of various algorithms and programs such as FFT, FIR, and HPL (High Performance Linpack) for different data transmission methods.

In order to effectively hide the latency of memory access operations, DMA needs to provide higher and higher data transfer speeds to meet the ever-increasing computing performance requirements of DSPs. The data transfer speed of DMA is largely limited by the efficiency of accessing the storage space outside the DDR core. Therefore, a very important task of DMA design is to try to improve the DDR access efficiency during the data transfer process. DSP core storage widely uses DDR3SDRAM components, DDR3SDRAM uses a three-dimensional structure, which is composed of multiple banks, each bank is composed of multiple storage rows, and each storage row contains multiple storage cell columns. The access of DDR3SDRAM is addressed according to the bank number, row address, and column address. First, select the bank to be accessed according to the bank number, and then read the storage line specified by the bank’s upstream address into the row cache. Finally, according to the column address from Some memory cell columns are read from the row cache.

There are three main cases of row access of DDR3 SDRAM storage unit: row empty, row missing and row hit. "Row empty" means that there is currently no active storage row in the bank to be accessed. At this time, the controller needs to send a "row activation" command to read the storage row to be accessed into the row cache before accessing. "Row missing" means that the currently active storage row in the bank is different from the storage row to be accessed. At this time, the controller needs to execute two commands to read the storage row into the row cache: the "precharge" command is used to turn off The current active row, the "Row Activation" command is used to open the storage row that needs to be accessed. "Row hit" means that the accessed row is currently active, that is, the storage row is already in the row cache. At this time, the controller does not need to send any commands, and can directly access the column. Therefore, among the three cases, the access latency of "row hit" is the lowest, and that of "row miss" is the largest. If DMA data transmission can effectively increase the row hit rate of DDR SDRAM, the memory access delay can be greatly reduced, and the data transmission efficiency can also be significantly improved.

In a multi-core processor, when a computing task is divided into multiple subtasks to be executed on multiple processing cores, the data accessed by these processing cores is continuous in the DDR address space. That is to say, if these cores can efficiently and synchronously transmit DDR data, a large part of the data they access may continuously fall in the same DDR SDRAM row, and a higher DDR SDRAM row hit rate is obtained. However, the traditional DMA structure does not provide the function of multi-core synchronous data transfer. At this time, due to the different execution states of each processing core, when their respective DMAs transfer data to DDR SDRAM, the data may arrive out of order, reducing the The row hit rate of DDR SDRAM limits the data transfer efficiency of DMA.

Contents of the invention

The technical problem to be solved by the present invention is: for the technical problems existing in the prior art, the present invention provides a multi-core GPDSP that can effectively improve the line hit rate of SDRAM, improve the utilization rate of memory access bandwidth and DMA transmission efficiency. Fine-grained synchronized DMA transfer method.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

A DMA transmission method for multi-core fine-grained synchronization of GPDSP, each direct storage access component DMA participating in multi-core fine-grained synchronous transmission will send a local frame transmission end signal to the global synchronization register after transmitting a frame of data; The global synchronization register integrates the end signals from multiple cores into a multi-bit wide global frame transmission end signal; each direct storage access component DMA checks whether the core list parameters configured by itself to participate in multi-core fine-grained synchronous transmission are consistent with the received The global frame transmission end signal is consistent; if consistent, it indicates that all DMA components participating in direct storage access have completed the transmission of the previous frame of data, and can start moving the next frame of data; if not consistent, it indicates that there is still participation in direct storage access The component DMA has not completed the transfer of the last frame of data, and these participating direct storage access component DMAs continue to wait until the matching is successful.

As a further improvement of the present invention: the global synchronization register directly sends the global frame transmission end signal to the DMA controller of each core through a connection.

As a further improvement of the present invention: before starting the multi-core fine-grained synchronous transmission, configure basic transmission parameters and determine which cores participate in the multi-core fine-grained synchronous transmission.

As a further improvement of the present invention: the direct storage access unit DMA is connected to the scalar memory SM, the vector memory AM, the ET debugging unit and the node access controller NAC through a dedicated bus; the active data transmission request of the direct storage access unit DMA passes through Two general-purpose channels are sent out, and four dedicated channels are used to process data transmission requests passively received by the direct storage access component DMA.

As a further improvement of the present invention: the direct storage access unit DMA describes the data to be transmitted in a two-dimensional data block format, the two-dimensional data block is composed of multiple data frames, and each data frame is composed of multiple data with continuous addresses Composed of units, the size of the data unit is equal to the bit width of the chip.

As a further improvement of the present invention: the global synchronization register is located outside the GPDSP core, and each GPDSP core has a 1-bit signal line LOver output to the global synchronization register, and the signal line Lover is used to transmit the direct storage access components of each GPDSP core The local frame transmission end signal of DMA; the global synchronization register integrates the LOver signal input from all GPDSP cores into a global frame transmission end signal GOver, and the G global frame transmission end signal Over signal is input to each GPDSP core.

As a further improvement of the present invention: the specific flow of the transmission method is:

S1: Start multi-core fine-grained synchronous transmission;

S2: Send a read request; judge whether it is the last data of the frame, if not, return and resend the read request; if yes, execute step S3;

S3: judge whether it is the last frame, if no, execute step S4; if yes, end multi-core fine-grained synchronous transmission;

S4: Set the local frame transmission end signal, which is used to set the corresponding bit of the global synchronization register; match the global frame transmission end signal, that is, the input global frame transmission end signal and the configured core list participating in the fine-grained synchronous transmission Parameters are matched; if the matching is successful, then step S5 is performed, and if the matching is unsuccessful, then return to re-matching the global frame transmission end signal, which means that there is still participation in the direct storage access component DMA that has not completed the transmission of the previous frame of data. A direct storage access component DMA needs to continue to wait until the matching is successful;

S5: After clearing the local frame transmission end signal, return to step S2; that is, each direct storage access component DMA pulls its own local frame transmission end signal low, and can start the transmission of the next frame of data at the same time;

S6: Execute repeatedly according to the above method until the transmission of all data frames is completed.

Compared with prior art, advantage of the present invention is: the multi-core fine-grained synchronous DMA transfer method for GPDSP of the present invention overcomes the deficiency that the traditional DMA transfer method of multi-core processor exists when DDR SDRAM is written, By synchronizing the same frame when multiple cores write external memory at the same time, the line hit rate of SDRAM can be effectively improved, and the utilization rate of memory access bandwidth and the transmission efficiency of DMA can be significantly improved.

Description of drawings

FIG. 1 is a schematic diagram of the overall framework of the GPDSP node in a specific application example of the present invention.

Fig. 2 is a schematic diagram of the overall structure of the DMA in a specific application example of the present invention.

Fig. 3 is a schematic diagram of a two-dimensional data block transferred by DMA in a specific application example of the present invention.

Fig. 4 is a schematic flow chart of the method of the present invention in a specific application example.

FIG. 5 is a schematic diagram of the connection relationship between the DMA controller and the global synchronization register in a specific application example of the present invention.

FIG. 6 is a schematic diagram of the interface sequence between the DMA controller and the global synchronization register in a specific application example of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

In a specific application example of the present invention, a DMA controller and a global synchronization register are included. The DMA controller exists in the core of the General Purpose Digital Signal Processor (GPDSP), the DMA global register exists outside the core of the GPDSP, and all DMA controllers are directly connected to the global synchronization register. When the DMA controller of the present invention moves data, one end of the transmission is the storage resource in the GPDSP core, and the other end is the storage resource DDR SDRAM outside the core. Before starting the direct storage access component DMA each time, the peripheral configuration bus (PBUS) will write the transmission parameters into the DMA parameter RAM, and the parameters describe the data transmitted by the direct storage access component DMA as a two-dimensional data block. The two-dimensional data block is composed of multiple data frames, and each data frame is composed of multiple data units. That is, each core contains a DMA controller, and all cores share a global synchronization register. The global synchronization register GSynReg is located on the top layer of the chip and is connected to all DMAs. The global synchronization register GSynReg allocates one bit for each DMA. Each DMA can set and clear its own corresponding bit. At the same time, each DMA can read all the global synchronization registers GSynReg. bit value.

The global synchronous register is connected with all direct storage access parts DMA, and receives the frame transmission end signal of multiple cores. The global synchronization register integrates these end-of-frame transmission signals into a multi-bit signal and sends it to each core of the GPDSP. The GPDSP core judges whether all GPDSP cores participating in fine-grained synchronous data transmission have completed the transmission of the previous frame of data according to this multi-bit signal. If completed, all cores participating in multi-core fine-grained synchronous data transmission can read the next frame of data. Otherwise, each GPDSP core continues to wait until all GPDSP cores participating in multi-core fine-grained synchronous data transmission transactions have completed the transmission of the last frame of data.

The basic principle of the method of the present invention is: before starting the multi-core fine-grained synchronous transmission, in addition to configuring the basic transmission parameters, it is also necessary to configure the parameter SynCoreList specifying which cores participate in the multi-core fine-grained synchronous transmission. The bit width of SynCoreList is the same as the number of chip cores. If the jth bit is set to high level, it means that core j participates in multi-core fine-grained synchronous transmission. Each direct memory access component DMA that participates in multi-core fine-grained synchronous transmission will send a one-bit local frame transmission end signal to the global synchronization register GSynReg after transmitting a frame of data, which is used to set the corresponding bit of the global synchronization register . The global synchronization register integrates the end signals from multiple cores into a multi-bit wide global end-of-frame signal, which is wired directly to each core's DMA controller. Each direct memory access component DMA checks whether the parameters of the list of cores configured by itself to participate in the multi-core fine-grained synchronous transmission are consistent with the received global frame transmission end signal. If they are consistent, it indicates that all DMAs participating in the direct memory access unit have completed the transmission (movement) of the previous frame of data, and they can start to move the data of the next frame. If they are inconsistent, it means that there are still participating direct storage access parts DMAs that have not completed the transfer of the previous frame of data. Therefore, these participating direct storage access parts DMAs continue to wait until the matching is successful, that is, until all participating DMAs have completed the previous frame Data movement. Execute repeatedly in the above manner until the transmission of all data frames is completed.

For example, assuming that the DMA set of direct memory access units participating in inter-core synchronization is [DMA ₀ , DMA ₁ ,…,DMA _k ], each direct memory access unit DMA must wait for all participating inter-core The synchronous direct storage access component DMA completes the transfer of the previous frame of data. For example, the condition for DMA _i (0<=i<=k) to start transferring the second frame is that DMA ₀ , DMA ₁ , . . . , DMA _k have all completed transferring the first frame. For the case where a large task is divided into multiple processing cores for parallel execution, when configuring DMA parameters, it can basically ensure that each frame of data synchronously transmitted by multiple cores is written to the same row of DDR SDRAM. At this time, compared with the traditional DMA transmission method, the technical solution of the present invention can reduce the number of line feeds of DDR SDRAM, significantly improve the line hit rate of DDR SDRAM, thereby achieving the purpose of improving the efficiency of DMA data transmission.

As shown in FIG. 4 , it is a flow chart of performing multi-core fine-grained inter-core synchronous transmission in a specific application example of the present invention. As shown in the figure, the specific process of the present invention in specific application is:

S1: Start multi-core fine-grained synchronous transmission;

S2: Send a read request; judge whether it is the last data of the frame, if not, return and resend the read request; if yes, execute step S3;

S3: judge whether it is the last frame, if no, execute step S4; if yes, end multi-core fine-grained synchronous transmission;

S4: Set the local frame transmission end signal, which is used to set the corresponding bit of the global synchronization register; match the global frame transmission end signal, that is, the input global frame transmission end signal and the configured core list participating in the fine-grained synchronous transmission Parameters are matched; if the matching is successful, then step S5 is performed, and if the matching is unsuccessful, then return to re-matching the global frame transmission end signal, which means that there is still participation in the direct storage access component DMA that has not completed the transmission of the previous frame of data. A direct storage access component DMA needs to continue to wait until the matching is successful.

S5: After clearing the local frame transmission end signal, return to step S2; that is, each direct memory access unit DMA pulls its own local frame transmission end signal low, and at the same time can start the transmission of the next frame of data.

S6: Execute repeatedly according to the above method until the transmission of all data frames is completed.

As shown in FIG. 1 , it is a schematic diagram of the overall framework of the GPDSP node in a specific application example of the present invention. Each GPDSP core contains a scalar processor unit SPU and a vector processing unit VPU. The scalar processing unit SPU contains a scalar memory SM for storing scalar operands. The vector processing unit contains a memory SM for storing vector operands. Vector memory AM. The direct storage access component DMA is also located in the GPDSP core, and it is mainly used to complete the data transmission between the core storage resources AM, SM and the external storage resource DDR3SDRAM. According to the configuration of the system, the access to DDR3SDRAM can go through the global Cache first, and then reach the DDR3SDRAM, or it can directly reach the DDR3SDRAM without going through the global Cache.

As shown in FIG. 2 , it is a schematic diagram of the overall structure of the direct storage access unit DMA in a specific application example of the present invention. Direct storage access unit DMA is connected with scalar memory SM, vector memory AM, ET debugging unit and node access controller NAC through a dedicated bus. The active data transmission request of the direct storage access unit DMA is sent through two general channels, and the four dedicated channels are used to process the data transmission requests passively received by the direct storage access unit DMA. Before each direct memory access unit DMA actively transmits data, it needs to receive transmission configuration parameters from the scalar processing unit SPU, and these configuration parameters are used to indicate the format, source address, destination address, etc. of the data block to be moved. In order to support multi-core fine-grained synchronous data transmission, it is also necessary to configure parameters specifying which cores participate in fine-grained synchronous transmission.

The direct storage access component DMA describes the data to be transmitted in a two-dimensional data block format, as shown in FIG. 3 , which is a schematic diagram of a two-dimensional data block transmitted by DMA in a specific application example of the present invention. A two-dimensional data block is composed of multiple data frames, and addresses between adjacent data frames can be continuous or discontinuous. Each data frame is composed of multiple data units with consecutive addresses, and the size of the data unit is equal to the bit width of the chip, that is, 64 bits. The data block in FIG. 3 includes K data frames, and each data frame includes m data units.

As shown in FIG. 5 , it is a schematic diagram of the connection relationship between the DMA controller and the global synchronization register in a specific application example of the present invention. The global synchronization register GSynReg is located outside the GPDSP core. Each GPDSP core has a 1-bit signal line LOver output to the global synchronization register GSynReg. The LOver signal line transmits the local frame transmission end signal of the direct storage access component DMA of each GPDSP core. The global synchronization register GSynReg integrates the LOver signals input from K+1 GPDSP cores into a K+1-bit global frame transmission end signal GOver, and the GOver signal is input to each GPDSP core.

As shown in FIG. 6 , it is a schematic diagram of the interface sequence between the DMA controller and the global synchronization register in a specific application example of the present invention. In this embodiment, assuming that 12 cores participate in multi-core fine-grained synchronous data transmission, assuming that the value of the global synchronization register GSynReg is 12'hFFE at Cycle 0, and a certain direct storage access unit DMA transfers a frame of data, the direct storage access unit The DMA will set the local frame transmission end signal LOver. The local frame transmission end signal LOver is first passed to the global synchronization register GSynReg, and the global synchronization register combines the LOver signals of multiple cores into a multi-bit global frame transmission end signal GOver and sends it to each direct storage access component DMA. Assuming that the above signal transmission process requires a total of N cycles, after N cycles, the direct storage access component DMA receives the global frame synchronization end signal with a value of 12'hFFF, which successfully matches the core list signal participating in the fine-grained synchronous transmission, and directly The storage access unit DMA pulls down the local frame transmission end signal LOver, and starts to transmit the next frame of data. In order to prevent multiple matchings, no matching operation is performed within N cycles after the direct memory access component DMA pulls down the local frame transmission end signal LOver. This cycle repeats until the transmission of all data frames is completed.

The above are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (7)

1. A kind of DMA transmission method of the multi-core fine-grained synchronization that is used for GPDSP, it is characterized in that, each direct storage access part DMA that participates in multi-core fine-grained synchronous transmission will send a local frame transmission end signal after having transmitted a frame of data Send to the global synchronization register; the global synchronization register integrates the end signals from multiple cores into a multi-bit wide global frame transmission end signal; each direct storage access component DMA checks the cores configured by itself to participate in the multi-core fine-grained synchronous transmission Whether the list parameter is consistent with the received global frame transmission end signal; if consistent, it indicates that all participating direct storage access components DMA have completed the transmission of the previous frame of data, and can start to move the next frame of data; if not consistent, it indicates There are still participating direct storage access components DMA that have not completed the transfer of the last frame of data, and these participating direct storage access components DMA continue to wait until the matching is successful. 2. the DMA transmission method that is used for the multi-core fine-grained synchronization of GPDSP according to claim 1, is characterized in that, described global synchronous register directly sends global frame transmission end signal to the DMA controller of each core by wiring . 3. the DMA transfer method for the multi-core fine-grained synchronous transmission of GPDSP according to claim 1, is characterized in that, before starting the multi-core fine-grained synchronous transmission, configure basic transmission parameters and determine which cores participate in the multi-core fine-grained synchronous transmission. 4. the DMA transmission method that is used for the multicore fine-grained synchronization of GPDSP according to claim 1, is characterized in that, described direct storage access part DMA is with scalar memory SM, vector memory AM, ET debugging part and node by dedicated bus The access controller NAC is connected; the active data transmission request of the direct storage access unit DMA is sent through two general channels, and the four dedicated channels are used to process the data transmission requests passively received by the direct storage access unit DMA. 5. the DMA transmission method that is used for the multi-core fine-grained synchronization of GPDSP according to claim 1, is characterized in that, described direct storage access part DMA describes the data that needs to transmit with two-dimensional data block format, and described two-dimensional data A block is composed of multiple data frames, and each data frame is composed of multiple data units with consecutive addresses, and the size of the data unit is equal to the bit width of the chip. 6. the DMA transmission method that is used for the multicore fine-grained synchronization of GPDSP according to claim 1, is characterized in that, described global synchronous register is positioned at outside the GPDSP core, and each GPDSP core has 1 bit signal line LOver to export to global synchronous Register, the signal line Lover is used to transmit the local frame transmission end signal of the direct storage access part DMA of each GPDSP core; the global synchronization register integrates the LOver signal input from all GPDSP cores into a global frame transmission end signal GOver , the G global frame transmission end signal Over signal is input to each GPDSP core. 7. according to the DMA transmission method of the multi-core fine-grained synchronization that is used for GPDSP according to any one of claims 1～6, it is characterized in that, the concrete process of described transmission method is: S1: Start multi-core fine-grained synchronous transmission; S2: Send a read request; judge whether it is the last data of the frame, if not, return and resend the read request; if yes, execute step S3; S3: judge whether it is the last frame, if no, execute step S4; if yes, end multi-core fine-grained synchronous transmission; S4: Set the local frame transmission end signal, which is used to set the corresponding bit of the global synchronization register; match the global frame transmission end signal, that is, the input global frame transmission end signal and the configured core list participating in the fine-grained synchronous transmission Parameters are matched; if the matching is successful, then step S5 is performed, and if the matching is unsuccessful, then return to re-matching the global frame transmission end signal, which means that there is still participation in the direct storage access component DMA that has not completed the transmission of the previous frame of data. A direct storage access component DMA needs to continue to wait until the matching is successful; S5: After clearing the local frame transmission end signal, return to step S2; that is, each direct storage access component DMA pulls its own local frame transmission end signal low, and can start the transmission of the next frame of data at the same time; S6: Execute repeatedly according to the above method until the transmission of all data frames is completed.