CN104617098B - Three-dimensional stacked semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a three-dimensional stacked semiconductor structure and a manufacturing method thereof. The three-dimensional stacked semiconductor structure comprises: a plurality of stacked layers formed on a substrate, at least one contact hole formed vertically in one of the stacked layers, a conductor formed in the contact hole, and a charge capture layer formed at least on the sidewalls of the stacked layers. One of the stacked layers comprises a multi-layer column including a plurality of insulating layers and a plurality of conductive layers alternately stacked, and a dielectric layer formed on the multi-layer column. The contact hole passes through the dielectric layer, the insulating layers and the conductive layers of the corresponding stacked layers. The conductor in the contact hole connects the conductive layers of the corresponding stacked layers. The upper surface of the conductor is higher than the upper surface of the multi-layer column of the corresponding stacked layer.

Description

Three-dimensional stacked semiconductor structure and manufacturing method thereof

technical field

The present invention relates to a three-dimensional stacked semiconductor structure and its manufacturing method, and more particularly to a three-dimensional stacked semiconductor structure with a conductive strip connecting source contacts and its manufacturing method.

Background technique

A great feature of non-volatile memory element design is the ability to preserve the integrity of the data state when the memory element loses or removes power. Currently, many different types of non-volatile memory devices have been proposed in the industry. However, related companies are still developing new designs or combining existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND gate (NAND) flash memory structures have been proposed. However, there are still some problems to be solved in the conventional 3D stacked memory structure.

FIG. 1 is a perspective view of a 3D stacked semiconductor structure. FIG. 1 shows a 3D NAND memory array structure as an example for illustration. The 3D stacked semiconductor structure includes an array region 11 and a fan-out region 13 . The multi-layer array is formed on an insulating layer, and includes a plurality of word lines 125-1WL, . . . , 125-N WL, which are isotropically formed with a plurality of stacks. The plurality of stacks includes semiconductor strips 112 , 113 , 114 , 115 . The semiconductor strips in the same plane are electrically coupled together through a ladder structure (also called a bit line structure). The stepped structures 102B, 103B, 104B, 105B terminate the semiconductor strips (eg, semiconductor strips 102 , 103 , 104 , 105 ). As shown, the ladder structures 102B, 103B, 104B, 105B are electrically connected to different bit lines for connection to decoding circuits for selecting planes within the array. The stacked semiconductor strips 102, 103, 104, 105 have a source line end to bit line end orientation. The stacked semiconductor strips 102, 103, 104, 105 are terminated at one end by the ladder structures 102B, 103B, 104B, 105B, through the SSL gate structure 109, the ground selection line GSL127, the word lines 125-NWL to 125-1WL, the ground Select line GSL126 is terminated at the other end by a source line (shaded by the rest of the figure). The stacked semiconductor strips 112, 113, 114, 115 are terminated at one end by the ladder structures 112A, 113A, 114A, 115A, through the SSL gate structure 119, the ground selection line GSL126, the word lines 125-1WL to 125-N WL, The ground select line GSL 127 is terminated at the other end by the source line 128 .

Take a source line 128 as an example. The source line 128 includes an insulating layer (such as an oxide layer) and a conductive layer (such as polysilicon used as a gate material) stacked alternately, and has a contact hole perpendicular to the stacked structure and a conductive material filled in the hole to make each layer The conductive layer is externally connected. Traditionally, for self-alignment, the filling of the contact hole with conductive material is done before the deposition of the bit line hard mask layer. However, the hard mask material may be redeposited in the contact hole. This may cause problems in the SCpick-up process. Furthermore, the source contact area of the traditional 3D stacked semiconductor structure is an open area (open area) when the word line is etched (such as ion reactive etching). The influence of the word line process on the source contact area (WL loading effect) is more serious than the effect of the memory cell area. Traditionally, the source contact area requires a thicker hard mask layer to protect against possible damage during word line etching. Furthermore, the source contact and the bit line of the conventional stacked structure are built on the same level, which increases the difficulty of alignment between the source contact and the upper conductive plug during the process of receiving the source contact.

Contents of the invention

The invention relates to a three-dimensional stacked semiconductor structure and a related manufacturing method. According to an embodiment, the step of patterning the source contact (filling the contact hole with conductive material) is performed after the deposition of a hard mask layer (such as a dielectric layer) for the bit line, so that the conductive material in the contact hole is compatible with the hard mask layer. The mask layer (such as a dielectric layer) is at the same level. Furthermore, in one embodiment, a conductive strap spans over the plurality of source contacts. Therefore, the three-dimensional stacked semiconductor structure of the embodiment has a lower source contact resistance, a stable structure capable of reducing the WL loading effect, and has good electronic characteristics of reliability.

According to an embodiment, a three-dimensional stacked semiconductor structure is provided, comprising: a plurality of stacks formed on a substrate, at least one contact hole vertically formed in one of the stacks, a Conductors are formed in the contact holes, and a charging trapping layer is formed at least on sidewalls of these stacked layers. One of the stacks includes a multi-layered pillar formed by alternately stacking multiple insulating layers and multiple conductive layers, and a dielectric layer is formed on the multi-layered pillar. Contact holes pass through the corresponding stacked dielectric layers, the insulating layers and the conductive layers. Conductors in the contact holes connect the conductive layers of the corresponding stack. Wherein, the upper surface of the conductor is higher than the upper surface of the corresponding stacked multi-layer pillars.

According to an embodiment, a method of fabricating a three-dimensional stacked semiconductor structure is provided, comprising: forming a plurality of stacks on a substrate, wherein one of the stacks includes a multilayer pillar having a plurality of insulating layers and a multilayer Conductive layers are stacked alternately, and a dielectric layer is formed on the multi-layer column; at least one contact hole is formed perpendicular to one of these stacks, and the contact hole passes through the dielectric layer of the corresponding stack, these insulating layer and these conductive layers; filling a conductor in the contact hole and connecting the conductive layers of the corresponding stack, wherein an upper surface of the conductor is higher than an upper surface of the multilayer pillar corresponding to the stack; forming a charge Capture layers are located at least at the sidewalls of these stacks.

In order to have a better understanding of the above and other aspects of the present invention, the following specific embodiments are described in detail in conjunction with the accompanying drawings. However, the protection scope of the present invention should be determined by the appended claims.

Description of drawings

FIG. 1 is a perspective view of a 3D stacked semiconductor structure.

FIG. 2 is a schematic cross-sectional view of a source contact region of a part of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.

FIG. 3 is a top view of a part of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.

4A to FIG. 11A and FIG. 4B to FIG. 11B illustrate a manufacturing method of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.

FIG. 12 is a schematic diagram of another way of connecting the source contact.

【Symbol Description】

11: Array area

13: Fan-out area

102, 103, 104, 105, 112, 113, 114, 115: semiconductor strip

102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A: ladder structure

128: Source line

20, 40: Substrate

21, 41: Lamination

21P, 41P: multi-layer cylinder

211, 411: insulating layer

213, 413: conductive layer

23, 43: hard mask layer

23a, 43a: upper surface of the hard mask layer

24, 44: Contact hole

25, 45: Conductor

25a, 45a: the upper surface of the conductor

26, 46: charge trapping layer

27, 47: Conductive strip

48: isolation layer

49: Conductive embolism

49': Conductive trace

Rsc: source contact area

125-1WL, ..., 125-N WL, WL: word line

BL: bit line

109, 119, SSL: serial selection line

126, 127, GSL: ground selection line

Detailed ways

In an embodiment of the present disclosure, a three-dimensional stacked semiconductor structure and related manufacturing methods are presented. The three-dimensional stacked semiconductor structure proposed in the embodiment has a lower source contact (source contacts) resistance, a stable structure that can reduce the impact of the word line process (WL loading effect), and good reliability (reliability) electronic characteristics . Moreover, the three-dimensional stacked semiconductor structure of the embodiment has simple steps in fabrication, and can be completed without using time-consuming and expensive processes.

Embodiments of the present invention have a wide variety of applications. For example, it can be applied to a three-dimensional flash memory, such as a fan-out area of a three-dimensional NAND flash memory, but the present invention is not limited to this application. The following are related embodiments, together with figures, to illustrate the three-dimensional stacked semiconductor structure proposed by the present invention and the related manufacturing method in detail. However, the present invention is not limited thereto. The descriptions in the embodiments, such as detailed structures, process steps and material applications, etc., are for illustration purposes only, and are not intended to limit the protection scope of the present invention.

Also, not all possible embodiments of the present invention are shown. Changes and modifications can be made to the structure and process without departing from the spirit and scope of the present invention, so as to meet the needs of practical application processes. Therefore, other implementation aspects not proposed in the present invention may also be applicable. Furthermore, the size ratios in the drawings are not drawn to the same proportions as the actual products. Therefore, the specification and illustrations are only used to describe the embodiments, rather than to limit the protection scope of the present invention.

According to an embodiment, the step of patterning the source contacts of the three-dimensional stacked semiconductor structure is performed after the hard mask deposition of the bit lines, the material of the hard mask layer is, for example, a dielectric layer material. FIG. 2 is a schematic cross-sectional view of a source contact region of a part of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention. A semiconductor structure of an embodiment includes a plurality of stacks 21 formed on a substrate 20, and one of the stacks 21 includes a multi-layered pillar 21P and a hard mask layer (hard mask layer) 23 is formed on the multi-layer pillars 21P. The multi-layer pillar 21P is formed by alternately stacking multiple insulating layers 211 (such as oxide layers) and multiple conductive layers 213 (such as polysilicon layers). The hard mask layer 23 is formed on the uppermost insulating layer 211 of the multilayer pillars 21P. The material of the hard mask layer 23 is, for example, a material of a dielectric layer, but the invention is not limited thereto.

The semiconductor structure of the embodiment also includes a stack 21 in which at least one contact hole 24 is vertically formed, and the contact hole 24 passes through the hard mask layer 23 of the corresponding stack 21, the insulating layers 211 and These conductive layers 213. Two contact holes 24 are shown in FIG. 2 , but of course the present invention does not limit the number of contact holes. Moreover, a conductor (conductor) 25 is formed in the contact hole 24 and connects the conductive layers 213 of the corresponding stack 21 (ie, where the contact hole 24 extends).

The semiconductor structure of the embodiment also includes a charge trapping layer (charging trapping layer) 26, such as an ONO layer (oxide layer-nitride layer-oxide layer) or an ONONO layer (oxide layer-nitride layer-oxide layer-nitride layer) - oxide layer) is formed at least at the sidewalls of these stacks 21. As shown in FIG. 2, the charge trapping layer 26 is formed at the sidewall of the stack 21, and an upper surface 25a of the conductor 25 and an upper surface 23a of the hard mask layer 23 are exposed, and are not trapped by charges. Layer 26 covers.

The above-mentioned conductors 25 can be used as source contacts of the three-dimensional stacked semiconductor structure of an embodiment. As shown in FIG. 2 , an upper surface 25 a of the conductor 25 is higher than an upper surface of the multi-layer pillar 21P corresponding to the stack 21 . In one embodiment, the upper surface 25 a of the conductor 25 is substantially aligned with the upper surface 23 a of the hard mask layer 23 .

According to an embodiment, a conductive strap 27 is further formed above the stacks 21 and contacts the charge trapping layer 26 . Wherein, the conductive strip 27 is formed on and across the conductor 25 in the contact hole 24 . The conductive strip 27 is electrically connected to the conductor 25 in the contact hole 24 and the charge trapping layer 26 at the sidewall of the stack 21 . FIG. 3 is a top view of a part of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention, wherein a conductive strip 27 is formed on the conductor 25 in the contact hole 24 and parallel to a plurality of word lines (WL).

According to an embodiment, the conductive strip 27 is a source contact strap contacting the contact, thereby reducing the resistance of the contact. In one embodiment, the conductive strips 27 and the word lines can be made of the same material at the same time. Furthermore, the conductive strip 27 of the embodiment is built in the source contact region (SC region), therefore, the source contact (ie, the conductor 25) is covered and protected by the conductive strip 27 (instead of the source contact in the traditional structure being Covered by the bit line hard mask layer (/dielectric layer), thereby reducing the impact of the word line process on the source contact area (WL loading effect). Furthermore, since the patterning step of the source contact in the embodiment is performed after the deposition of the bit line hard mask layer, no material of the hard mask layer will be deposited in the source contact.

A fabrication method for a three-dimensional stacked semiconductor structure is proposed as follows. However, the present invention is not limited to the details of the structure and steps, but may be appropriately adjusted and changed depending on the requirements of the process or practical application.

4A to 11A and 4B to 11B illustrate a manufacturing method of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention. 4A , FIG. 5A , FIG. 6A , . 4B, 5B, 6B, . . . 11B are cross-sectional views along the section line AA of FIG. 4A, 5A, 6A, . . . 11A, respectively. Wherein, the position of the section line AA corresponds to a source contact region.

As shown in FIG. 4A and FIG. 4B, a plurality of stacked layers 41 are formed on a substrate 40, including multiple layers of insulating layers 411 (such as oxide layers) and multiple layers of conductive layers 413 (such as polysilicon layers) stacked alternately to form A multi-layered pillar 41P in a stack 41, and a hard mask layer 43 is formed on the uppermost insulating layer 411 of the multi-layered pillar 41P. The material of the hard mask layer 43 may be a dielectric material, such as silicon nitride or oxide, deposited on the insulating layer 411 .

As shown in FIG. 5A and FIG. 5B , at least one contact hole 44 is vertically formed, and the contact hole 44 passes through the hard mask layer 43 , the insulating layers 411 and the conductive layers 413 .

After the step of patterning the source contact as shown in FIGS. 5A and 5B , a conductive material is filled in the contact hole 44 to form a source contact. In one embodiment, a conductive layer (material such as N+ polysilicon) is deposited on the hard mask layer 43 and fills the contact hole 44 , and then the conductive layer is planarized to form the conductor 45 in the contact hole 44 . In one embodiment, the planarization of the conductive layer is performed by chemical mechanical polishing (CMP) or other suitable steps. As shown in FIGS. 6A and 6B , the upper surface 45 a of the conductor 45 is substantially aligned with the upper surface 43 a of the hard mask layer 43 . According to the manufacturing method of the embodiment, the upper surface 45 a of the conductor 45 is higher than the upper surface of the uppermost insulating layer 411 .

As shown in FIGS. 7A and 7B , the structure of FIG. 6B is then patterned to form bit lines (BL) and stack 41 . In one embodiment, when the APF process is used to pattern the bit lines, no damage will be caused to the hard mask layer (/dielectric layer) of the bit lines. As shown in FIG. 7B, a bit line (BL) is formed between two stacks 41, and each stack 41 has a source contact (ie, conductor 45). Wherein, each stack 41 includes a multi-layered pillar (multi-layered pillar) 41P and a hard mask layer 43 is formed on the multi-layered pillar 41P, and a multi-layered pillar 41P includes several layers of insulating layers 411 and several layers. The conductive layers 413 are stacked alternately; the conductors 45 filled in the contact holes 44 vertically pass through the hard mask layer 43 , the insulating layer 411 and the conductive layer 413 corresponding to the stacked layers 41 .

Afterwards, a charge trapping layer 46 (such as an ONO layer or an ONONO layer) is formed on at least the sidewalls of the stacks 41 and the bit lines. In the present invention, different steps can be used to make this structure, such as the steps in FIG. 8B and FIG. 9B .

As shown in FIGS. 8A and 8B , a charge trapping layer 46 , such as an ONO layer or an ONONO layer, is deposited to cover the stack 41 , the bit line (BL) and the substrate. Afterwards, remove a part (such as the upper portion) of the charge trapping layer 46 to expose the upper surface 45a of the conductor 45, the upper surface of the bit line and the upper surface 43a of the hard mask layer 43, as shown in FIG. 9A and FIG. 9B. In one embodiment, a photolithography process can be applied to a photoresist to define (open) the source contact region Rsc, and only the upper portion of the charge trapping layer 46 corresponding to the source contact region Rsc is removed, as shown in FIG. 9A shown. The region outside the source contact region Rsc is still covered by the charge trapping layer 46 . In another embodiment, no photoresist is used, but all stack layers 41 and the upper part of the charge trapping layer 46 of the bit line (BL) are removed, which is also applicable. The present invention is not limited to this. The charge trapping layer 46 is removed by, for example, reactive ion etching (RIE) to expose the conductor 45 in the contact hole 44 . Furthermore, an organic dielectric layer (ODL, organic dielectric layer)/SHB process can be used to overcome the problem of the structure height of the conductor 45 .

Afterwards, a conductive strap 47 is formed on and across (as shown in FIG. 3 ) above these stacked layers 41 and corresponds to the source contact region Rsc. As shown in FIGS. 10A and 10B , conductive strips 47 and multiple word lines (WL) may be formed over stack 41 and bit lines (BL) at the same time. Therefore, the conductive strips 47 and the word lines of the embodiment can be made of the same material. In one embodiment, the conductive strips 47 and the word lines include, for example, polysilicon (fabricated by a salicide process). However, the present invention is not limited thereto. The materials of the conductive strips 47 and the word lines can be the same or different, and can be manufactured at the same time or not. The materials can be properly selected according to the needs of actual applications.

As shown in FIG. 10A , the conductive strips 47 are arranged parallel to the word lines (WL) and spaced apart from each other by a distance. As shown in FIG. 10 , the conductive strip 47 is electrically connected to the conductor 45 in the contact hole 44 (eg, contacts the upper surface 45 a of the conductor 45 ) and the charge trapping layer 46 . The conductive strips 47 also contact the upper surface 43 a of the hard mask layer 43 .

After that, a conducting portion is formed on the conductive strip 47 to receive the signal from the source contact (such as the conductor 45 ). Wherein, the conductive part is separated from the conductor 45 and the hard mask layer 43 by a distance. In an embodiment, the conductive portion may be a conductive line or a conductive plug.

As shown in FIG. 11A and FIG. 11B, an isolation layer (such as an inner layer dielectric layer ILD) 48 is formed on the conductive strip 47, and a plurality of holes are formed in the isolation layer 48 and pass through the isolation layer 48, and then a conductive A material such as tungsten or other suitable metal fills the holes. As shown in FIG. 11B , a conductive plug 49 is formed in the hole of the isolation layer 48 . Wherein, the conductive plug 49 is electrically connected to the conductor 45 in the contact hole 44 through the conductive strip 47 . In addition, as shown in FIG. 12 , which shows a schematic diagram of another way of loading source contacts, wherein the conductive part is a conductive trace 49' formed above the conductive strip 47 and across the stacks 41. The conductive wire 49' is, for example, tungsten, or the same material as the word line, or other suitable conductive material.

According to the structure of the embodiment, that is, the construction of the conductive body 45, the conductive strip 47 and the conductive part (49/49'), there is no need to consider whether there is a problem of misalignment between the conductive plug and the source contact. Therefore, the three-dimensional stacked semiconductor structure proposed in the embodiment has electronic properties with good reliability.

According to the above-mentioned embodiments, the patterning of the source contact in the three-dimensional stacked semiconductor structure is performed after the hard mask layer (dielectric material) of the bit line is deposited, and no hard mask layer is deposited on the source contact. Material. Furthermore, as the conductor 25/45 of a source contact of the three-dimensional stacked semiconductor structure of the embodiment protrudes from the upper surface of the multi-layer pillar 21P/41P, that is, it is higher than the height of the conventional source contact, thus reducing the The resistance of the source contact. Moreover, the conductive strip strap27/47 of the embodiment is constructed in the source contact area, so that the source contact (ie, the conductor 25) is protected by the conductive strip 27 (instead of the source contact in the traditional structure being protected by the hard bit line). Mask layer coverage), thereby reducing the impact of the word line process on the source contact area (WLloading effect). Furthermore, the conductive strips 27 / 47 of the embodiment can be made of the same material as the word lines at the same time, the manufacturing steps are simple and time-saving, and are suitable for mass production.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (9)

1. A three-dimensional stacked semiconductor structure (3D stacked semiconductor structure), comprising: A plurality of stacks are formed on a substrate, and each of the stacks includes: A multi-layered pillar (multi-layered pillar) is formed by alternately stacking multiple insulating layers and multiple conductive layers; a dielectric layer (dielectric layer) is formed on the multi-layer pillar; At least two contact holes (contact holes) are respectively vertically formed in at least two of the stacked layers, and the at least two contact holes pass through the dielectric layer, the insulating layers and the conductive layers of the corresponding stacked layers; At least two conductors are formed in the at least two contact holes and connected to the corresponding conductive layers of the stack; a charging trapping layer is formed at least at sidewalls of the stacks; and a conductive strip is formed on the stacked layers and contacts the charge trapping layer, the conductive strip straddles the at least two conductors to connect the at least two conductors; Wherein the upper surfaces of the at least two electrical conductors are higher than the upper surfaces of the corresponding stacked multi-layer pillars. 2. The three-dimensional stacked semiconductor structure according to claim 1, wherein the conductive strip contacts the upper surface of the at least two electrical conductors and an upper surface of the dielectric layer. 3. The three-dimensional stacked semiconductor structure according to claim 1, further comprising a conducting portion formed on the conductive strip, wherein the conducting portion is connected to the dielectric layer and the at least two contact holes. The two conductors are separated by a distance. 4. The three-dimensional stacked semiconductor structure according to claim 1, further comprising: an isolating layer is formed on the conductive strip; and at least one conductive plug is formed in the isolation layer and passes through the isolation layer, Wherein the conductive plug is electrically connected to the at least two conductors in the at least two contact holes through the conductive strip. 5. A method for manufacturing a three-dimensional stacked semiconductor structure, comprising: forming a plurality of stacks on a substrate, each of the stacks comprising: A multi-layered pillar (multi-layered pillar) is formed by alternately stacking multiple insulating layers and multiple conductive layers; a dielectric layer (dielectric layer) is formed on the multi-layer pillar; vertically forming at least two contact holes (contact holes) in at least two of the stacked layers, and the at least two contact holes pass through the dielectric layer, the insulating layers and the conductive layers of the corresponding stacked layers; Filling at least two conductors in the at least two contact holes and connecting the corresponding conductive layers of the stack, wherein the upper surface of the at least two conductors is higher than that of the corresponding multi-layer pillar of the stack upper surface; forming a charge trapping layer at least at the sidewalls of the stacks; A conductive strip is formed on the stacked layers and contacts the charge trapping layer, and the conductive strip crosses the at least two conductors to connect the at least two conductors. 6. The method of claim 5, wherein the conductive strip contacts the upper surface of the at least two electrical conductors and an upper surface of the dielectric layer. 7. The method of claim 6, wherein the three-dimensional stacked semiconductor structure has a plurality of word lines, and the conductive strip is made of the same material as the word lines. 8. The method according to claim 5, further comprising forming a conducting portion on the conductive strip, wherein the conducting portion is connected to the dielectric layer and the at least two conductors in the at least two contact holes separated by a distance. 9. The method of claim 5, further comprising forming an isolating layer on the conductive strip; forming at least one hole in and through the isolation layer; and forming a conductive plug in the hole of the isolation layer, Wherein, the conductive plug is electrically connected to the at least two conductors in the at least two contact holes through the conductive strip.