CN104637864B - The method for improving data holding ability - Google Patents
The method for improving data holding ability Download PDFInfo
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- CN104637864B CN104637864B CN201310567433.0A CN201310567433A CN104637864B CN 104637864 B CN104637864 B CN 104637864B CN 201310567433 A CN201310567433 A CN 201310567433A CN 104637864 B CN104637864 B CN 104637864B
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- metal interconnecting
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 88
- 239000002184 metal Substances 0.000 claims abstract description 88
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000011248 coating agent Substances 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 118
- 239000011229 interlayer Substances 0.000 claims description 18
- 238000000137 annealing Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 239000005368 silicate glass Substances 0.000 claims description 4
- 239000005383 fluoride glass Substances 0.000 claims description 3
- 230000005055 memory storage Effects 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 2
- 241000720974 Protium Species 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a kind of method for improving data holding ability, including：Multiple layer metal interconnection layer is sequentially formed on a semiconductor substrate, is forming the second metal interconnecting layer with being annealed respectively after the 3rd metal interconnecting layer.For the present invention by forming the second metal interconnecting layer with being annealed respectively after the 3rd metal interconnecting layer, the hydrogen ion introduced during avoiding the formation of coating causes semiconductor devices data holding ability to drift about；The performance of semiconductor devices will not be impacted simultaneously.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of raising data holding during making metal interconnecting layer
The method of ability.
Background technology
The manufacture of semiconductor crystal wafer is subjected to series of process flow.It is all that the flow includes etching and photoetching etc.
Different semiconductor wafer process steps, each of which step can all influence the final circuit knot of single-chip on the semiconductor crystal wafer
The formation of structure.The main secondary technique of two classes can be divided on traditional manufacturing process.The first main secondary technique can be described as
FEOL（Front end of line, FEOL）, and second of main secondary technique can be described as last part technology（back
End of line, BEOL）.
Traditional FEOL is by the laser labelling of wafer, and next shallow trench isolation formation, formed p-well and
The ion implanting of N traps, the etching of polysilicon, and the ion note in a variety of regions such as the drain electrode of injection transistor arrangement and source electrode
Enter.
In the last part technology of semiconductor devices, when making semiconductor integrated circuit, after semiconductor device layer is formed, need
Metal interconnecting layer is formed on semiconductor device layer, every layer of metal interconnecting layer includes metal interconnecting wires and interlayer dielectric layer
（Inter Layer dielectric, ILD）, this just needs manufacture groove and connecting hole after interlayer dielectric layer, so
The deposited metal in above-mentioned groove and connecting hole afterwards, the metal of deposition is metal interconnecting wires, typically mutual as metal from copper
Link material.
In the prior art in order to prevent copper from diffusing into interlayer dielectric layer, preferably it is limited in groove and connecting hole, typically
Using tantalum（Ta）And tantalum nitride（TaN）Laminated construction, as the barrier film between metal interconnecting wires and interlayer dielectric layer.Interlayer
Dielectric layer typically uses low-k（low-K）Insulation material layer, for example, containing silicon, oxygen, carbon, protium similar oxide
（Oxide）Black diamond material, undoped with silicate glass（USG）, fluoride glass（FSG）Deng.
Then coating is formed on the surface of the metal interconnecting wires and interlayer dielectric layer, the material of the coating is nitrogen
SiClx, but the formation of silicon nitride can introduce H ions, the data holding ability for the semiconductor devices for causing to ultimately form floats
Move.
Therefore, how to avoid causing shadow to the data holding ability of semiconductor devices during metal interconnecting layer is formed
Ring, turn into the technical problem of current urgent need to resolve
The content of the invention
The invention provides a kind of method for improving data holding ability, to solve to make metal interconnecting layer in the prior art
During, the problem of deposited copper metal interconnection line and coating cause semiconductor devices data holding ability to drift about.
The method provided by the invention for improving data holding ability, including：
Semi-conductive substrate is provided, sequentially formed thereon including the first metal interconnecting layer, the second metal interconnecting layer and the
Multiple layer metal interconnection layer including three metal interconnecting layers；
The second metal interconnecting layer is being formed with being annealed respectively after the 3rd metal interconnecting layer.
Further, the temperature of the annealing is 350 DEG C~450 DEG C.
Further, the time of the annealing is 25min~35min.
Further, four to eight layers of metal interconnecting layer are sequentially formed in the Semiconductor substrate.
Further, the metal interconnecting layer includes metal interconnecting wires and interlayer dielectric layer.
Further, the material of the metal interconnecting wires is copper.
Further, the interlayer dielectric layer includes：Carbonado BD, undoped with silicate glass USG or fluorination
Glass FSG.
Further, the metal interconnecting layer also includes the covering positioned at the metal interconnecting wires and inter-level dielectric layer surface
Layer.
Further, the material of the coating is silicon nitride.
Further, before the first metal interconnecting layer is formed, in addition to, memory dress is formed on the semiconductor substrate
Put.
Further, after multiple layer metal interconnection layer is formed, in addition to, form passivation layer and aluminium pad.
Compared with prior art, the present invention has advantages below：
The method provided by the invention for improving data holding ability, by forming the second metal interconnecting layer and the 3rd metal
Annealed respectively after interconnection layer, the hydrogen ion introduced during avoiding the formation of coating causes semiconductor devices data to protect
Hold the drift of ability；Simultaneously because simply increase annealing process will not impact to the performance of semiconductor devices.
Brief description of the drawings
The flow chart of the method for the raising data holding ability that Fig. 1 is provided by one embodiment of the invention.
The metal interconnecting layer structural representation that Fig. 2 is provided by one embodiment of the invention.
Embodiment
The method of raising data holding ability proposed by the present invention is done further below in conjunction with the drawings and specific embodiments
Describe in detail.According to following explanation and claims, advantages and features of the invention will become apparent from, it should be noted that, accompanying drawing
Non- accurately ratio is used using very simplified form and, be only used for conveniently, lucidly aiding in illustrating of the invention implement
The purpose of example.
The flow chart of the method for the raising data holding ability that Fig. 1 is provided by one embodiment of the invention, as shown in figure 1,
A kind of method for improving data holding ability proposed by the present invention, comprises the following steps：
Step S01：Semi-conductive substrate is provided, is formed on the first metal interconnecting layer；
Step S02：The second metal interconnecting layer is formed on first metal interconnecting layer, and is annealed；
Step S03：The 3rd metal interconnecting layer is formed on second metal interconnecting layer, and is annealed；
Step S04：Continuation forms remaining metal interconnecting layer on the 3rd metal interconnecting layer.
Fig. 2 is the metal interconnecting layer structural representation that one embodiment of the invention provides, and be refer to shown in Fig. 1, and combines figure
2, describe the method proposed by the present invention for improving data holding ability in detail：
Step S01：Semi-conductive substrate 1 is provided, is formed on the first metal interconnecting layer 10.
The Semiconductor substrate 1 can be monocrystalline silicon or SiGe or silicon-on-insulator（Silicon on
Insulator, SOI）.In the present embodiment, before the first metal interconnecting layer 10 is formed, formed in the Semiconductor substrate 1
Memory storage（Memory device）, the method for forming the memory storage is ordinary skill in the art means, is not made herein
Specifically describe.
The method for forming the first metal interconnecting layer 10, specifically, being sequentially depositing to form etching stopping on semiconductor substrate 1
Layer 2 and interlayer dielectric layer 11.The material of etching stop layer 2 can be one kind or its combination in silica, silicon nitride；Institute
State interlayer dielectric layer 11 and typically use low-K insulation material layers, for example, containing silicon, oxygen, carbon, protium similar oxide it is black
Diamond material, undoped with silicate glass or fluoride glass etc..
The interlayer dielectric layer 11 is performed etching, etching stopping forms groove and connecting hole on etching stop layer 2；So
Afterwards by PVD methods, on the bottom and side wall of groove, TaN layers, Ta layers are sputtered in the bottom of connecting hole and side wall successively；According to
The secondary Ta layers and TaN layers for etching away connecting hole bottom, exposes the etching stop layer 2, is exposing the surface of etching stop layer 2
And splash-proofing sputtering metal Ta layers are continued on the surface of Ta layers, are connected as one with the Ta layers formed before（Not by TaN layers and Ta in Fig. 2
Layer makes a distinction, and is only represented with 12）.The above-mentioned barrier film being made up of TaN and Ta is a kind of specific embodiment, in other implementations
In example, the method for other formation barrier films can be used or well known to a person skilled in the art other materials.
Further, metal material 13, in the present embodiment, the metal material 13 are filled in the groove and connecting hole
For copper, the metal material 13 of the excess surface of interlayer dielectric layer 11 is then removed by the method for cmp, to dew
Go out the interlayer dielectric layer 11；Then coating is formed on the interlayer dielectric layer 11 and metal material 13, ultimately forms gold
Belong to interconnection layer 10.The material of the coating is silicon nitride.
Step S02：The second metal interconnecting layer 20 is formed on first metal interconnecting layer 10, and is annealed.
In the present embodiment, deposition forms interlayer dielectric layer on the first metal layer 10, then using with forming first
The identical process of metal interconnecting layer 10, forms the second metal interconnecting layer 20 on first metal interconnecting layer 10, goes forward side by side
Row annealing.The temperature of the annealing is 350 DEG C~450 DEG C, such as 350 DEG C, 400 DEG C, 450 DEG C, wherein preferable annealing temperature
For 400 DEG C；The time of annealing is 25min~35min, such as 25min, 30min, 35min, wherein preferable annealing time is
30min。
Step S03：The 3rd metal interconnecting layer 30 is formed on second metal interconnecting layer 20, and is annealed.
In the present embodiment, using with formed the identical process of the second metal interconnecting layer 20, it is mutual in second metal
The 3rd metal interconnecting layer 30 is even formed on layer 20, and is annealed.The temperature of the annealing is 350 DEG C~450 DEG C, such as 350
DEG C, 400 DEG C, 450 DEG C, wherein preferable annealing temperature be 400 DEG C；The time of annealing is 25min~35min, such as 25min,
30min, 35min, wherein preferable annealing time is 30min.
Step S04：Continuation forms remaining metal interconnecting layer on the 3rd metal interconnecting layer 30.
Remaining metal interconnecting layer is formed according to being actually needed on the 3rd metal level 30, in general semiconductor device
Part is, it is necessary to form four to eight layers of metal interconnecting layer, i.e., mutual in the 3rd metal successively using the process described in step S02
Required metal interconnecting layer, such as the interconnection of the 4th metal interconnecting layer, fifth metal interconnection layer, the 6th metal are even formed on layer 30
Layer, the 7th metal interconnecting layer or low eight metal interconnecting layer, the specific number of plies are determined by being actually needed.
Then, formed by chemical vapor deposition or metal sputtering processes on the semiconductor device structure of above-mentioned formation
Aluminum cushion layer, aluminium pad is formed using plasma method etch away sections aluminum cushion layer, the aluminium pad interconnects with the most last layer metal
Layer electrical connection, then re-forms passivation layer, and the passivation layer is thinned until exposing the top of aluminium pad.
In the present embodiment, the second metal interconnecting layer is being formed with being annealed respectively after the 3rd metal interconnecting layer, can be with
Cancel the annealing process in the prior art after aluminium pad and passivation layer is formed, compared with prior art, only increase is annealed together
Technique.
In summary, the method provided by the invention for improving data holding ability, by forming the second metal interconnecting layer
With being annealed respectively after the 3rd metal interconnecting layer, the hydrogen ion introduced during avoiding the formation of coating causes semiconductor
The drift of device data holding capacity；Simultaneously because simply increase annealing process will not cause shadow to the performance of semiconductor devices
Ring.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (9)
1. a kind of method for improving data holding ability, applied in the last part technology of semiconductor devices, including：Half is provided to lead
Body substrate, sequentially formed thereon including the first metal interconnecting layer, the second metal interconnecting layer and the 3rd metal interconnecting layer
Multiple layer metal interconnection layer, it is characterised in that every layer of metal interconnecting layer includes metal interconnecting wires, interlayer dielectric layer and positioned at gold
Belong to interconnection line and the coating of inter-level dielectric layer surface, form the coating of the second metal interconnecting layer and the 3rd metal interconnecting layer
Annealed respectively afterwards.
2. the method for data holding ability is improved as claimed in claim 1, it is characterised in that the temperature of the annealing is 350
DEG C~450 DEG C.
3. the method for data holding ability is improved as claimed in claim 2, it is characterised in that the time of the annealing is
25min~35min.
4. the method for data holding ability is improved as claimed in claim 1, it is characterised in that in the Semiconductor substrate successively
Form four to eight layers of metal interconnecting layer.
5. the method for data holding ability is improved as claimed in claim 1, it is characterised in that the material of the metal interconnecting wires
For copper.
6. the method for data holding ability is improved as claimed in claim 1, it is characterised in that the interlayer dielectric layer includes：
Carbonado BD, undoped with silicate glass USG or fluoride glass FSG.
7. the method for data holding ability is improved as claimed in claim 1, it is characterised in that the material of the coating is nitrogen
SiClx.
8. the method for the raising data holding ability as described in any one in claim 1~7, it is characterised in that formed
Before first metal interconnecting layer, in addition to, memory storage is formed on the semiconductor substrate.
9. the method for the raising data holding ability as described in any one in claim 1~7, it is characterised in that formed
After multiple layer metal interconnection layer, in addition to, form passivation layer and aluminium pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310567433.0A CN104637864B (en) | 2013-11-14 | 2013-11-14 | The method for improving data holding ability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310567433.0A CN104637864B (en) | 2013-11-14 | 2013-11-14 | The method for improving data holding ability |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104637864A CN104637864A (en) | 2015-05-20 |
| CN104637864B true CN104637864B (en) | 2017-11-24 |
Family
ID=53216449
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|---|---|---|---|---|
| CN1877841A (en) * | 2005-06-09 | 2006-12-13 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
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| CN1992199A (en) * | 2005-12-29 | 2007-07-04 | 美格纳半导体有限会社 | Method for forming metal interconnection in image sensor |
| CN101728316A (en) * | 2008-10-31 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor chip with low warpage |
| CN102130046A (en) * | 2010-01-15 | 2011-07-20 | 诺发系统有限公司 | Interfacial layers for electromigration resistance improvement in damascene interconnects |
| CN102443830A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method for improving copper electroplating process |
-
2013
- 2013-11-14 CN CN201310567433.0A patent/CN104637864B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1922731A (en) * | 2004-04-30 | 2007-02-28 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| CN1877841A (en) * | 2005-06-09 | 2006-12-13 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| CN1992199A (en) * | 2005-12-29 | 2007-07-04 | 美格纳半导体有限会社 | Method for forming metal interconnection in image sensor |
| CN101728316A (en) * | 2008-10-31 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor chip with low warpage |
| CN102130046A (en) * | 2010-01-15 | 2011-07-20 | 诺发系统有限公司 | Interfacial layers for electromigration resistance improvement in damascene interconnects |
| CN102443830A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method for improving copper electroplating process |
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Effective date of registration: 20190906 Address after: 100176 9 Wenchang Avenue, Beijing Economic and Technological Development Zone Co-patentee after: Zhongxin International Integrated Circuit Manufacturing (Shanghai) Co., Ltd. Patentee after: Zhongxin North Integrated Circuit Manufacturing (Beijing) Co., Ltd. Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Zhongxin International Integrated Circuit Manufacturing (Shanghai) Co., Ltd. |
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