CN104658929A - Packaging method and device for flip chip - Google Patents
Packaging method and device for flip chip Download PDFInfo
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- CN104658929A CN104658929A CN201410163880.4A CN201410163880A CN104658929A CN 104658929 A CN104658929 A CN 104658929A CN 201410163880 A CN201410163880 A CN 201410163880A CN 104658929 A CN104658929 A CN 104658929A
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- chip
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000012856 packing Methods 0.000 claims description 19
- 238000005520 cutting process Methods 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 238000011161 development Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 238000012536 packaging technology Methods 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 18
- 239000010949 copper Substances 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 13
- 238000003698 laser cutting Methods 0.000 description 11
- 230000005496 eutectics Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 6
- 230000018109 developmental process Effects 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000004566 building material Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- 230000035800 maturation Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
The invention discloses a packaging method and a packaging device for a flip chip. The method comprises the following steps: S1, bonding a chip and a substrate, wherein the chip comprises at least two electrodes; at least one insulating area used for insulating the electric connection between the electrodes is formed between the electrodes; the substrate comprises at least one conductive area; after the chip is bonded to the substrate, the electrodes are electrically connected through the conductive area; S2, separating the conductive area from the overlapped area of the conductive and the insulating area to form a plurality of conductive sub-areas which are insulated from one another. The conductive area is arranged on the substrate to simultaneously bond all electrodes on the chip, and then the conductive area is separated to form the conductive sub-areas which are bonded to the electrodes on the chip in one-to-one correspondence and are insulated from one another, so that the problem about bulge distance limitation on the substrate in a packaging technology and the problem that alignment accuracy of substrate electrodes and chip electrodes is difficult to control are solved.
Description
Technical field
The present invention relates to a kind of semiconductor packaging, particularly a kind of method for packing of flip-chip and device.
Background technology
In the art, in order to bare chip is arranged on substrate, realize by the multiple joint solder joints be positioned on bare chip and substrate, in the process, various chips encapsulation technology can be applied, as ball grid array (BallGrid Array, BGA), toe-in conjunction, flip-chip etc.In order to ensure miniaturization and the functional diversities of electronic product or communicator, semiconductor packages needs little, the many pin connection of size, two-forty, high power and multifunction.
The increase of the increase of input and output (Input-Output, I/O) number of pins, the increase of High performance IC demand and LED high power requirements, facilitates the development of flip-chip packaging techniques.Flip chip technology (fct) uses and is positioned at multiple salient points (bumps) on multiple bond pads of chip and encapsulation medium direct interconnection.Chip by shortest path towards bond package medium.This technology not only can be applicable to single-chip package, also can be applicable to the larger-size encapsulation of higher integrative levels, and can hold several chip to form the more accurate substrate of larger functional unit.Flip chip technology (fct) uses area array, has and realizes the highest advantage lower with the interconnection inductance of encapsulation with the interconnection density of device.
But traditional flip chip techniques faces the challenge of the bump pitch restriction on substrate.In addition, high-performance FCBGA encapsulation is expensive because of the chip carrier substrate (typical chip carrier substrate comprises 1+2+1 layer building material or more layer building material) of costliness.Reduce with the growth of number of pins much slow because the development of flip chip technology (fct) and bump pitch reduce more than bare chip, therefore, the bump pitch of substrate becomes the bottleneck place of flip-chip line map.Even if following bare chip reduces reducing of bump pitch resolution by surmounting substrate carrier.In order to overcome this technological gap, silicon intermediary layer (silicon interposer) technology and silicon chip clear opening technology (Through Silicon Via, TSV) technology are unique at present and the solution of costliness.Therefore, a kind of modified model flip-chip packaging techniques of industrial circle tight demand, to meet cost benefit and to solve the bump pitch restriction on substrate.
More in addition, along with popularizing of semi-conductor LED illuminating, semi-conductor LED chips uses flip-chip packaged to become trend, at present except the bonding pattern of this common Flip-Chip Using of eutectic, recently the electromagnetic pulse solder bonds mode occurred in addition, as described in patent CN103094135A; The benefit of this bonding pattern is that atom level connects between chip electrode and electrode of substrate, contribute to very much the heat radiation of high-power chip, but find in the process of development, when using electromagnetic pulse welding manner bonding, chip electrode and electrode of substrate alignment precision become the key factor affecting packaging efficiency and finished product.
Summary of the invention
The object of the invention is to solve prior art chips electrode and electrode of substrate alignment precision is poor, salient point exists spacing and limits and the defect of high cost on substrate, there is provided a kind of chip electrode and electrode of substrate alignment precision higher, and the method for packing of lower-cost flip-chip and device.
To achieve these goals, the present invention is by the following technical solutions:
A method for packing for flip-chip, its feature is, it includes following steps:
S1, by a chip and a substrate bonding, wherein, described chip includes at least two electrodes, at least one insulating regions for being electrically connected between isolated described electrode is included between described electrode, described substrate includes at least one conductive region, after described chip and described substrate bonding, be electrically connected by described conductive region between described electrode;
S2, described conductive region is separated with the region of described insulating regions overlap the conduction subregion forming several mutually insulateds from described conductive region.
Herein, prior art all can implant the salient point of several metals usually on the electrode of the chip for upside-down mounting, and then has the electrode in the one side align substrates of salient point to carry out bonding implantation, and precision is subject to the restriction of bump pitch.In the solution of the present invention, owing to being provided with conductive region on substrate, conductive region covers the insulating regions between the electrode of chip after chip and substrate bonding, makes significantly to reduce (because the point-to-point and chip on chip between salient point and the electrode of substrate is very high to required precision with the mode of aiming at of the insulating regions on substrate) the requirement of precision in bonding process.In addition, be electrically connected by the conductive region on substrate between electrode after bonding due to chip, need along the insulating regions between the electrode on chip, electrical connection between the electrode of chip is cut off, therefore the line segment on the region that conductive region can be selected overlapping with the insulating regions of chip, to be separated into the conduction subregion with the electrode of chip several mutually insulateds one to one along these line segments by conductive region.
That is, owing to needing to reduce chip and the required precision of mutually aiming at during substrate bonding, and the insulating regions on chip is aimed at the requirement of precision higher with the insulating regions on substrate mutually, the solution of the present invention, without the insulating regions in optic placode, directly arranges the insulating regions on conductive region covering chip on substrate.So, required precision during bonding is greatly diminished, but the side effect brought be chip electrode between can there is electrical connection, cannot use.In order to eliminate this side effect, after bonding, the electrical connection between needing the electrode of chip is cut off.In other words, the precision of the cutting/blocking-up required for electrical connection between the electrode cutting off chip more easily reaches with the precision (also can be understood as electrode of substrate and chip electrode alignment precision) of aiming at of the insulating regions on substrate relative to the insulating regions on chip.
In addition, can also after this programme it is also understood that substrate for selecting unitary electrode and chip bonding, then the electrode of the electrode unitary electrode of substrate being separated into several and chip bonding one to one.
Preferably, described substrate is single-layer metal substrate.
Preferably, described substrate is multiple layer metal substrate.
That is, use metal substrate, then whole substrate is all conductive region.And metal substrate is relative to the ceramic substrate of prior art, there is the advantage of rapid heat dissipation.
Preferably, described S2 is: use laser to be cut in region overlapping with described insulating regions for described conductive region, makes described conductive region split the conduction subregion forming several mutually insulateds.
Laser beam processing (LBM, Laser Beam Machining) is the high energy beam processing utilizing energy density very high laser beam that workpiece material is melted, vaporize and evaporate and removed.Laser is monochromatic light, intensity is high, coherence and good directionality, by a series of optical system, laser beam focus can be become spot diameter little to several microns, energy density up to 108 ~ 109W/cm2, and can make any fusible, nondecomposable material fusing, evaporation, vaporization and reach the object of processing within even shorter time some thousandths of second.Laser beam processing is mainly used in a series of processing technologys such as material forming and modification such as punching, cutting, welding and surface treatment.In the past in two times more than ten years, laser beam process technology obtains and extremely develops rapidly, and obtains commercial Application widely.
Herein, laser cutting more easily reaches a higher precision, and in other words, the cost that the cost that laser cutting reaches a degree of precision increases relative to the alignment precision increasing chip paster bonding is much lower.And cutting forms the conduction subregion of mutually insulated, be intended to the electrical connection disconnected between the electrode of chip.
Preferably, described S2 is:
In the mode of mechanical grinding or cutting, region overlapping with described insulating regions for described conductive region is cut, make described conductive region split the conduction subregion forming several mutually insulateds.
Herein, the mode adopting mechanical grinding or cutting is also feasible.
Preferably, described S2 is:
Adopt the mode of development by zonal corrosion overlapping with described insulating regions for described conductive region, expose described insulating regions, make described conductive region be separated the conduction subregion forming several mutually insulateds.
Herein, can also use as modes such as developments, on substrate, etch-proof layer is smeared by after substrate and chip bonding, and expose the conductive region position overlapping with the insulating regions on chip, after eroding the conductor on the conductive region position overlapping with the insulating regions on chip, the electrical connection between the electrode of chip also can disconnect.
Preferably, described conductive region offers at least one groove, described groove is for exposing the upper figure recognition feature of the one side of the bonding of described chip and described substrate.
Herein, during owing to carrying out machine cuts or laser cutting substrate, need accurately to locate the position of the insulating regions on chip, therefore after groove is set, from the one side of the non-bonding chip of substrate, can pattern recognition technique be used, in the position of groove, identification be carried out to the figure recognition feature on chip.Such as, when insulating regions is a thin straight line, two grooves can be set and exposes one section of this thin straight line respectively for figure identification, also can expose figure identification point on chip on other positions by groove, indirectly the position of insulating regions be located.
The invention still further relates to a kind of packaging system of flip-chip, it includes one by the bonding apparatus of chip bonding in a substrate, its feature is, the packaging system of described flip-chip uses the method for packing of flip-chip as above, described chip includes at least two electrodes, at least one insulating regions for being electrically connected between isolated described electrode is included between described electrode, described substrate includes at least one conductive region, after described chip and described substrate bonding, be electrically connected by described conductive region between described electrode;
Herein, bonding apparatus can be the device adopting the technique such as eutectic or Reflow Soldering, because the technique such as eutectic or Reflow Soldering is the conventional means of prior art, repeats no more herein.
The packaging system of described flip-chip also includes described conductive region to be separated the conduction subregion forming several mutually insulateds by one separator for the region from described conductive region and described insulating regions overlap.
Preferably, region overlapping with described insulating regions for described conductive region is cut for using laser by described separator, makes described conductive region split the conduction subregion forming several mutually insulateds.
Preferably, described separator is used for being cut in region overlapping with described insulating regions for described conductive region in the mode of mechanical grinding or cutting, makes described conductive region split the conduction subregion forming several mutually insulateds.
Positive progressive effect of the present invention is: by arrange on substrate conductive region simultaneously with all electrode bondings on chip, again this conductive region is separated and is formed and bonding and the conduction subregion of mutually insulated one to one of the electrode on chip, solve the problem of the bump pitch restriction in encapsulation technology on substrate at lower cost, and electrode of substrate and the unmanageable problem of chip electrode alignment precision.
Accompanying drawing explanation
Fig. 1 is that multiple chips of the embodiment of the present invention 1 are placed on substrate looks up perspective structure schematic diagram.
Fig. 2 is the structural representation of the chip of the embodiment of the present invention 1.
Fig. 3 is the structural representation after the one single chip of the embodiment of the present invention 1 and substrate bonding.
Fig. 4 is the structural representation after corresponding position that the substrate of the embodiment of the present invention 1 prolongs position of insulating between chip electrode separates.
Fig. 5 is the flow chart of the method for packing of the flip-chip of the embodiment of the present invention 1.
Embodiment
Mode below by embodiment further illustrates the present invention, but does not therefore limit the present invention among described scope of embodiments.
Embodiment 1
Fig. 5 is the flow chart of the method for packing of the flip-chip of the present embodiment, and as shown in Figure 5, the method for packing of the flip-chip that the present embodiment relates to includes following steps:
Step 1, by a chip and a substrate bonding, wherein, chip includes at least two electrodes, at least one insulating regions for being electrically connected between isolated electrode is included between electrode, substrate includes at least one conductive region, after chip and substrate bonding, be electrically connected by conductive region between electrode;
Region overlapping with insulating regions for conductive region is cut by step 2, use laser, makes conductive region split the conduction subregion forming several mutually insulateds.
Wherein, conductive region offers at least one groove, groove is for exposing the upper figure recognition feature of the one side of the bonding of chip and substrate.
Below the method for packing of above-mentioned flip-chip is further described.
Fig. 1 is that multiple chips of the present embodiment are placed on substrate looks up perspective structure schematic diagram, Fig. 2 is the structural representation of the chip of the present embodiment, Fig. 3 is the structural representation after the one single chip of the present embodiment and substrate bonding, Fig. 4 is the structural representation after corresponding position that the substrate of the present embodiment prolongs position of insulating between chip electrode separates, as shown in figures 1-4
Chip 100 is of a size of long 1000 microns, wide 1000 microns, thickness 335 microns, bottom is electrode zone, positive electrode 102 is of a size of 945X75 micron, and negative electrode 105 is of a size of 945X795 micron, and between positive electrode 102 and negative electrode 105, spacing distance is 75 microns;
First, prepared substrate, substrate includes the copper sheet 101 that several surperficial gold-tin alloy AuSn20 thickness of coating are 150 micron thickness of 15 microns, each copper sheet 101 is all corresponding with a chips 100, copper sheet 101 planar dimension is the square of 2000 microns × 2000 microns, be described as a unit below
Substrate is put into laser cutting operation desk, confirm the central point of each copper sheet 101 on this substrate (namely, the central point of 2000 microns × 2000 micro unit), prolonging this central point cuts open long 400 microns to the direction on parallel units square limit, the groove 103 of wide 20 microns, then in these groove 103 both sides (groove center line) at a distance of 250 microns of parallel grooves 103 cutting out same size in place.(being convenient to identification location when follow-up chip placement 100 and laser cutting electrode).
That is, substrate made of copper is divided into several copper sheet 101 unit, each copper sheet 101 goes out three for exposing the groove 103 (see Fig. 4) of the figure recognition feature of the electrode gap 104 of chip 100 by laser cutting.
Be placed on by the electrode surface of chip 100 on the gold-tin alloy coating face of copper sheet 101, copper sheet 101 center is aimed at chip 100 center, and makes electrode gap 104 as the insulating regions on chip 100 perpendicular to three grooves 103.
The substrate being placed with chip is put into eutectic furnace, realizes bonding, because eutectic technology exists maturation process, do not repeat them here.
The chip and substrate that complete bonding are put into laser cutting operation desk, chip under, substrate is above.Specific to the copper sheet 101 of each unit, laser cutting platform is according to the position through the electrode gap 104 between the positive electrode 102 of groove 103 grab chips 100 on each copper sheet 101 and negative electrode 105, copper sheet 101 is cut open along electrode gap 104, copper sheet 101 is isolated as being electrically connected with the positive electrode 102 of chip 100 and negative electrode 105 respectively and the conduction subregion 111 of mutually insulated and the subregion 112 that conducts electricity.Finally the connection between multiple copper sheet 101 is cut off, form the separate unit of chip and substrate package.Due to the existing maturation process such as identification and cutting accuracy of laser cutting, no longer repeat at this.
In addition, the present embodiment also relates to a kind of packaging system of flip-chip, and this packaging system includes an eutectic device and a laser cutting device, and uses the method for packing of flip-chip described above.
Embodiment 2
Embodiment 2 provides a kind of method for packing and device of flip-chip, and embodiment 2 is with the difference of embodiment 1:
After substrate and chip 100 bonding, after positioning according to the electrode gap 104 on groove 103 pairs of chips 100, each on substrate lays a barrier tape on the position at copper sheet 101 counter electrode interval 104, then on substrate, smears etch-proof layer.
Afterwards, barrier tape is opened, so just expose the position that copper sheet 101 is overlapping with the electrode gap 104 on chip 100, after eroding the conductor (i.e. copper) on the position of leading above-mentioned exposure, the state being electrical connectors be in disconnection between the electrode of chip 100.
Although the foregoing describe the specific embodiment of the present invention, it will be understood by those of skill in the art that this only illustrates, protection scope of the present invention is defined by the appended claims.Those skilled in the art is under the prerequisite not deviating from principle of the present invention and essence; various changes or modifications can be made to these execution modes; such as; do not use laser cutting copper sheet; and adopt the conductive region on the mode separating base plates such as machine cuts; or adopt the substrate that other metal/alloy etc. are made, then or do not adopt eutectic bonding and adopt reflow soldering process etc., but these change and amendment all falls into protection scope of the present invention.
Claims (10)
1. a method for packing for flip-chip, is characterized in that, it includes following steps:
S1, by a chip and a substrate bonding, wherein, described chip includes at least two electrodes, at least one insulating regions for being electrically connected between isolated described electrode is included between described electrode, described substrate includes at least one conductive region, after described chip and described substrate bonding, be electrically connected by described conductive region between described electrode;
S2, described conductive region is separated with the region of described insulating regions overlap the conduction subregion forming several mutually insulateds from described conductive region.
2. the method for packing of flip-chip as claimed in claim 1, it is characterized in that, described substrate is single-layer metal substrate.
3. the method for packing of flip-chip as claimed in claim 1, it is characterized in that, described substrate is multiple layer metal substrate.
4. the method for packing of flip-chip as claimed in claim 1, it is characterized in that, described S2 is:
Use laser to be cut in region overlapping with described insulating regions for described conductive region, make described conductive region split the conduction subregion forming several mutually insulateds.
5. the method for packing of flip-chip as claimed in claim 1, it is characterized in that, described S2 is:
In the mode of mechanical grinding or cutting, region overlapping with described insulating regions for described conductive region is cut, make described conductive region split the conduction subregion forming several mutually insulateds.
6. the method for packing of flip-chip as claimed in claim 1, it is characterized in that, described S2 is:
Adopt the mode of development by zonal corrosion overlapping with described insulating regions for described conductive region, expose described insulating regions, make described conductive region be separated the conduction subregion forming several mutually insulateds.
7. the method for packing of the flip-chip as described in Claims 1 to 5, is characterized in that, described conductive region offers at least one groove, and described groove is for exposing the upper figure recognition feature of the one side of the bonding of described chip and described substrate.
8. the packaging system of a flip-chip, it includes one by the bonding apparatus of chip bonding in a substrate, it is characterized in that, the packaging system of described flip-chip uses the method for packing of the flip-chip according to any one of claim 1 ~ 7, described chip includes at least two electrodes, at least one insulating regions for being electrically connected between isolated described electrode is included between described electrode, described substrate includes at least one conductive region, after described chip and described substrate bonding, be electrically connected by described conductive region between described electrode;
The packaging system of described flip-chip also includes described conductive region to be separated the conduction subregion forming several mutually insulateds by one separator for the region from described conductive region and described insulating regions overlap.
9. the packaging system of flip-chip as claimed in claim 8, it is characterized in that, region overlapping with described insulating regions for described conductive region is cut for using laser by described separator, makes described conductive region split the conduction subregion forming several mutually insulateds.
10. the packaging system of flip-chip as claimed in claim 8, it is characterized in that, described separator is used for being cut in region overlapping with described insulating regions for described conductive region in the mode of mechanical grinding or cutting, makes described conductive region split the conduction subregion forming several mutually insulateds.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410163880.4A CN104658929A (en) | 2014-04-22 | 2014-04-22 | Packaging method and device for flip chip |
| PCT/CN2015/075218 WO2015161731A1 (en) | 2014-04-22 | 2015-03-27 | Encapsulation method and device for flip chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410163880.4A CN104658929A (en) | 2014-04-22 | 2014-04-22 | Packaging method and device for flip chip |
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| CN104658929A true CN104658929A (en) | 2015-05-27 |
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|---|---|---|---|
| CN201410163880.4A Pending CN104658929A (en) | 2014-04-22 | 2014-04-22 | Packaging method and device for flip chip |
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| Country | Link |
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| CN (1) | CN104658929A (en) |
| WO (1) | WO2015161731A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946250A (en) * | 2017-12-20 | 2018-04-20 | 中科院微电子研究所昆山分所 | A kind of method for packing of semiconductor chip and semiconductor chip |
| US10985300B2 (en) | 2015-09-11 | 2021-04-20 | Quan Ke | Encapsulation method for flip chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000077725A (en) * | 1998-08-27 | 2000-03-14 | Shichizun Denshi:Kk | Semiconductor package and manufacturing method thereof |
| US20030059979A1 (en) * | 2001-09-25 | 2003-03-27 | Yasunari Ukita | Semiconductor device-manufacturing method |
| CN1527370A (en) * | 2002-11-15 | 2004-09-08 | ��ʽ���������Ƽ� | Manufacturing method of semiconductor device |
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| US7049177B1 (en) * | 2004-01-28 | 2006-05-23 | Asat Ltd. | Leadless plastic chip carrier with standoff contacts and die attach pad |
| EP2084744A2 (en) * | 2006-10-27 | 2009-08-05 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| CN101350381B (en) * | 2007-07-18 | 2011-03-02 | 晶科电子（广州）有限公司 | Salient point LED and manufacturing method thereof |
| TWI397964B (en) * | 2011-01-19 | 2013-06-01 | Unisem Mauritius Holdings Ltd | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| CN103094135A (en) * | 2011-11-01 | 2013-05-08 | 柯全 | Encapsulation method for flip chip |
| US8877555B2 (en) * | 2012-11-16 | 2014-11-04 | Alpha & Omega Semiconductor, Inc. | Flip-chip semiconductor chip packing method |
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2014
- 2014-04-22 CN CN201410163880.4A patent/CN104658929A/en active Pending
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2015
- 2015-03-27 WO PCT/CN2015/075218 patent/WO2015161731A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000077725A (en) * | 1998-08-27 | 2000-03-14 | Shichizun Denshi:Kk | Semiconductor package and manufacturing method thereof |
| US20030059979A1 (en) * | 2001-09-25 | 2003-03-27 | Yasunari Ukita | Semiconductor device-manufacturing method |
| CN1527370A (en) * | 2002-11-15 | 2004-09-08 | ��ʽ���������Ƽ� | Manufacturing method of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10985300B2 (en) | 2015-09-11 | 2021-04-20 | Quan Ke | Encapsulation method for flip chip |
| CN107946250A (en) * | 2017-12-20 | 2018-04-20 | 中科院微电子研究所昆山分所 | A kind of method for packing of semiconductor chip and semiconductor chip |
| CN107946250B (en) * | 2017-12-20 | 2024-04-09 | 昆山微电子技术研究院 | Semiconductor chip and packaging method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2015161731A1 (en) | 2015-10-29 |
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