CN104733475A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN104733475A CN104733475A CN201510137753.1A CN201510137753A CN104733475A CN 104733475 A CN104733475 A CN 104733475A CN 201510137753 A CN201510137753 A CN 201510137753A CN 104733475 A CN104733475 A CN 104733475A
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- Prior art keywords
- contact hole
- layer
- passivation layer
- drain electrode
- organic insulator
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- 239000000758 substrate Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 14
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 14
- 239000010936 titanium Substances 0.000 claims abstract description 14
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 239000002184 metal Substances 0.000 claims description 53
- 239000012212 insulator Substances 0.000 claims description 50
- 238000002161 passivation Methods 0.000 claims description 47
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 11
- 239000011733 molybdenum Substances 0.000 claims description 11
- 229910052750 molybdenum Inorganic materials 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 13
- 239000004411 aluminium Substances 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000003325 tomography Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides an array substrate. The array substrate comprises a base plate, and a grid, a grid insulating layer, a metal oxide semiconductor layer, a source and drain electrode layer, a passivating layer, an organic insulating layer and a pixel electrode layer which are sequentially formed on the base plate. First contact holes are formed in the portions, located above a drain of the source and drain electrode layer, of the passivating layer and the organic insulating layer. The drain of the source and drain electrode layer is connected with the pixel electrode layer through the first contact holes. The aperture of the first contact hole of the passivating layer is larger than that of the first contact hole of the organic insulating layer. The aperture of the first contact hole of the passivating layer is larger than that of the first contact hole of the organic insulating layer, and therefore the organic insulating layer can cover a fault between the passivating layer and under-drain metallic titanium, and the problems that due to the fact that the reverse chamfering between the organic insulating layer and the passivating layer happens to the contact holes, wire breakage of the pixel electrode layer is caused, and pixel electrodes can not be charged are solved.
Description
Technical field
The present invention relates to flat display technology field, particularly relate to a kind of array base palte and manufacture method thereof.
Background technology
At present, in the technology utilizing sull field-effect transistor driving liquid crystal displays, metallic aluminium can be frequent as wiring material, but the activity of aluminium is comparatively strong, atoms diffuse can occur, and changes the inherent characteristic of adjacent materials.Isolation layer generally can be used to carry out the infiltration of barrier metal aluminium, and isolation layer adopts Titanium or metal molybdenum usually.So the distribution three-decker often on array base palte, i.e. titanium/aluminium/titanium or molybdenum/aluminium/molybdenum.In order to cost-saving, source and drain metal wiring adopts titanium/aluminium or molybdenum/aluminium lamination, namely removes the isolation layer above aluminium.The preparation process of prior art array base palte comprises the steps:
The first step, on the transparent substrate, depositing metal films, this metallic film etches grid.
Second step, formation gate insulator.
3rd step, deposition of amorphous silicon films, etch pattern on the thin film, forms amorphous silicon semiconductor layer.
4th step, depositing metal films, this metallic film forms metal level, and described metal level comprises data wire and source-drain electrode.
5th step, formation passivation layer.
6th step, on above array base palte, be coated with organic insulator.
7th step, organic insulator to be exposed; And develop, peel off the organic insulator of contact hole position, engrave contact hole.
8th step, dry quarter is carried out to the passivation layer of contact hole position, remove the passivation layer of contact hole position.
9th step, wet etching is carried out to the metallic aluminium come out in contact hole region.
Tenth step, deposition ITO pattern, and form pixel electrode and be connected with drain electrode by contact hole.
As indicated with 1, wherein, passivation layer (not shown) is transparent to the structural representation of the array base palte pixel region that prior art is prepared, and covers the overwhelming majority of transparency carrier, and ITO electrode layer is connected with drain electrode by contact hole.Be illustrated in figure 2 the schematic cross-section of AA ' position in Fig. 1, be included on transparency carrier 00 and form grid 01, gate insulator 02, amorphous silicon semiconductor layer 03, drain metal layer 04, passivation layer 05, organic insulator 06, contact hole 07 and ITO layer 08 successively.Wherein, drain metal layer 04 comprises leaks upper metal Al layer 41 and the metal level 42 that leaks down, and lower metal layer is titanium or molybdenum.In leakage, metal A l exposed portion branch is fallen by wet etching, so the tomography that there will be passivation layer and leak down between metal, the pixel electrode layer along AA ' profile direction can break, but pixel electrode layer can successfully be connected with metal under source and drain.It is to prevent passivation layer from spending quarter that semiconductive amorphous silicon layer 03 is arranged between gate insulator and drain metal layer, causes pixel electrode layer to be connected conducting with the grid metal level of below.
In the manufacture process of metal oxide array base palte, metal oxide semiconductor layer is used to replace amorphous silicon layer to serve as contact hole blocking layer 03, be illustrated in fig. 3 shown below, in contact hole 07 process at dry quarter, because metal oxide cannot by dry quarter, plasma is caused to etch to side direction in a large number, the etching speed of passivation layer 05 is made to be far longer than the etching speed of organic insulator 06, the reverse chamfering 09 between organic insulator and passivation layer that caused contact hole position to occur, this can cause the broken string of pixel electrode layer, cannot charge to pixel electrode.
Summary of the invention
In order to solve the problem of prior art, the present invention discloses a kind of array base palte, comprising: a substrate, and the grid formed successively on the substrate, gate insulator, metal oxide semiconductor layer, source-drain electrode layer, passivation layer, organic insulator and pixel electrode layer;
Described passivation layer above the drain electrode being positioned at described source-drain electrode layer and described organic insulator are formed with the first contact hole, and the drain electrode of described source-drain electrode layer is connected with described pixel electrode layer by this first contact hole; Wherein, the first described contact hole comprises concentric passivation layer first contact hole and organic insulator first contact hole; The aperture of described passivation layer first contact hole is greater than the aperture of described organic insulator first contact hole.
Further, the shape of described passivation layer first contact hole and organic insulator first contact hole is circular or square.
Further, described drain electrode comprises the upper metal level of leakage and the metal level that leaks down; Wherein, in described leakage, metal level is Al metal, and the described metal level that leaks down is titanium or molybdenum.
The present invention gives a kind of manufacture method of array base palte, comprises the steps:
The first step, on the transparent substrate, depositing metal films, this metallic film etches grid;
Second step, formation gate insulator;
3rd step, depositing metal oxide film, form oxide semiconductor layer;
4th step, on above step basis, form metal level, this metal level comprises data wire, source electrode and drain electrode;
5th step, in step 4, form passivation layer;
6th step, above array base palte is coated with photoresist and photoresist is exposed, and photoresist is developed, the passivation layer of the first contact hole position is exposed.
7th step, formation passivation layer first contact hole;
8th step, metal level in the leakage exposing drain electrode corresponding to the first contact hole position to be etched away;
9th step, to above array base palte coating organic insulator;
Tenth step, formation organic insulator first contact hole;
11 step, form pixel electrode layer, pixel electrode layer is connected with drain electrode by the first contact hole that passivation layer and organic insulator are formed.
Further, the aperture of organic insulator first contact hole in step 10 is less than the aperture of described passivation layer first contact hole.
Further, in step 8, metal oxide semiconductor layer is etched away.
Beneficial effect: according to technical scheme of the present invention, the first contact hole due to passivation layer is greater than the first contact hole of organic insulator, so the tomography that organic insulator can cover passivation layer and leak down between Titanium, the phenomenon that breaks can not be there is in later pixel electrode when covering, solve contact hole position and occur the reverse chamfering between organic insulator and passivation layer, and cause the broken string of pixel electrode layer, cannot to the problem of pixel electrode charging.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing array base palte pixel region;
Fig. 2 is the schematic cross-section of AA ' position in Fig. 1;
Fig. 3 is the schematic cross-section of BB ' position in Fig. 1;
Fig. 4 is the structural representation of array base palte pixel region of the present invention;
Fig. 5 is the schematic cross-section of AA ' position in Fig. 4;
Fig. 6 a is the schematic cross-section of second embodiment of the invention step 1 to the array base palte of step 4;
Fig. 6 b is the schematic cross-section of the array base palte of second embodiment of the invention step 5;
Fig. 6 c is the schematic cross-section of the array base palte of second embodiment of the invention step 7;
Fig. 6 d is the schematic cross-section of the array base palte of second embodiment of the invention step 8;
Fig. 6 e is the schematic cross-section of the array base palte of second embodiment of the invention step 9;
Fig. 6 f is the schematic cross-section of the array base palte of second embodiment of the invention step 10.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
The invention provides a kind of array base palte, as shown in Figure 4, Fig. 5 is the schematic cross-section of AA ' position in Fig. 4 to the structural representation of this array base palte pixel region, is described array base palte of the present invention below in conjunction with Fig. 4 and Fig. 5.
Array base palte of the present invention comprises: substrate 10, and the grid 11 formed successively on the substrate, gate insulator 12, metal oxide semiconductor layer, source-drain electrode layer, passivation layer 15, organic insulator 16 and pixel electrode layer 18.Wherein, the passivation layer be positioned at above the drain electrode 14 of source-drain electrode layer and organic insulator are formed with the first contact hole 17, the drain electrode 14 of described source-drain electrode layer is connected with described pixel electrode layer 18 by this first contact hole 17; The first described contact hole comprises concentric passivation layer first contact hole and organic insulator first contact hole; The aperture of described passivation layer first contact hole is greater than the aperture of described organic insulator first contact hole; Described passivation layer first contact hole and organic insulator first contact hole are circular, square or other shapes; Described source-drain electrode layer comprises metal level and source and drain lower metal layer in source and drain, and in source and drain, metal level is Al, and source and drain lower metal layer is lower metal layer is titanium or molybdenum; As shown in Figure 5, drain electrode 14 comprises the upper metal level 41 of leakage and the metal level 42 that leaks down, and in leakage, metal level 41 is Al, and the metal level 42 that leaks down is for titanium or molybdenum.
In the present embodiment, because passivation layer first contact hole is greater than organic insulator first contact hole, so the tomography that organic insulator can cover passivation layer and leak down between Titanium, when later pixel electrode covers, the phenomenon that breaks can not be there is.
The present invention gives the manufacture method of a kind of array base palte of the second embodiment, and the method comprises the steps:
The first step, on the transparent substrate 10, depositing metal films, this metallic film etches grid 11
Second step, formation gate insulator 12;
3rd step, depositing metal oxide film, etch pattern on the thin film, forms oxide semiconductor layer 13;
4th step, on above step basis, first deposit one deck titanium or molybdenum film, then deposit one deck Al metallic film, form metal level; This metal level comprises draws together data wire (not shown), source electrode (not shown) and drain electrode 14, as shown in Figure 6 a, drain electrode 14 comprises metal level 41 and lower floor in leakage that upper strata is Al metal is the metal level 42 that leaks down of titanium or molybdenum.
5th step, in step 4, form passivation layer 15, as shown in Figure 6 b.
6th step, above array base palte is coated with photoresist and photoresist is exposed, and photoresist is developed, the passivation layer of the first contact hole position is exposed.
7th step, dry quarter is carried out to the passivation layer exposed, form passivation layer first contact hole 71, as fig. 6 c.
8th step, carrying out wet etching to exposing metal level 41 in leakage corresponding to the first contact hole position, retaining to leak down metal level 41; To leakage on metal level carry out wet etching time, metal oxide semiconductor layer 13 is also etched away; As shown in fig 6d.
9th step, to above array base palte coating organic insulator 16, as shown in fig 6e.
Tenth step, expose organic insulator 16, organic insulator corresponding to passivation layer first contact hole 71 position is removed in development, and form organic insulator first contact hole 72, as shown in Figure 6 f, the aperture of this contact hole is less than the aperture of the first contact hole 71.
11 step, deposition ITO pattern, and form pixel electrode layer 18, and pixel electrode layer 18 is connected with drain electrode 14 by the first contact hole 17 that passivation layer and organic insulator are formed, as shown in Figure 5.
The present invention, by twice contact hole technique of passivation layer and organic insulator, solves in metal oxide array base palte the reverse chamfering occurred between organic insulator and passivation layer.
Claims (6)
1. an array base palte, comprising: a substrate, and the grid formed successively on the substrate, gate insulator, metal oxide semiconductor layer, source-drain electrode layer, passivation layer, organic insulator and pixel electrode layer;
Described passivation layer above the drain electrode being positioned at described source-drain electrode layer and described organic insulator are formed with the first contact hole, and the drain electrode of described source-drain electrode layer is connected with described pixel electrode layer by this first contact hole; Wherein, the first described contact hole comprises concentric passivation layer first contact hole and organic insulator first contact hole; The aperture of described passivation layer first contact hole is greater than the aperture of described organic insulator first contact hole.
2. a kind of array base palte according to claim 1, is characterized in that: the shape of described passivation layer first contact hole and organic insulator first contact hole is for circular or square.
3. a kind of array base palte according to claim 1, is characterized in that: described drain electrode comprises the upper metal level of leakage and the metal level that leaks down; Wherein, in described leakage, metal level is Al metal, and the described metal level that leaks down is titanium or molybdenum.
4. a manufacture method for array base palte, comprises the steps:
The first step, on the transparent substrate, depositing metal films, this metallic film etches grid;
Second step, formation gate insulator;
3rd step, depositing metal oxide film, form oxide semiconductor layer;
4th step, on above step basis, form metal level, this metal level comprises data wire, source electrode and drain electrode;
5th step, in step 4, form passivation layer;
6th step, above array base palte is coated with photoresist and photoresist is exposed, and photoresist is developed, the passivation layer of the first contact hole position is exposed.
7th step, formation passivation layer first contact hole;
8th step, metal level in the leakage exposing drain electrode corresponding to the first contact hole position to be etched away;
9th step, to above array base palte coating organic insulator;
Tenth step, formation organic insulator first contact hole;
11 step, form pixel electrode layer, pixel electrode layer is connected with drain electrode by the first contact hole that passivation layer and organic insulator are formed.
5. a kind of array base palte according to claim 4, is characterized in that: the aperture of organic insulator first contact hole in step 10 is less than the aperture of described passivation layer first contact hole.
6. a kind of array base palte according to claim 4, is characterized in that: etch away metal oxide semiconductor layer in step 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510137753.1A CN104733475A (en) | 2015-03-26 | 2015-03-26 | Array substrate and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510137753.1A CN104733475A (en) | 2015-03-26 | 2015-03-26 | Array substrate and manufacturing method thereof |
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| CN104733475A true CN104733475A (en) | 2015-06-24 |
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| CN201510137753.1A Pending CN104733475A (en) | 2015-03-26 | 2015-03-26 | Array substrate and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106095189A (en) * | 2016-06-29 | 2016-11-09 | 南京中电熊猫液晶显示科技有限公司 | A kind of In Cell touch-control array base palte and manufacture method thereof |
| CN106229347A (en) * | 2016-08-24 | 2016-12-14 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and manufacture method thereof |
| CN106684097A (en) * | 2017-01-03 | 2017-05-17 | 京东方科技集团股份有限公司 | Substrate and manufacturing method therefor and display panel |
| CN111244108A (en) * | 2020-01-16 | 2020-06-05 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106095189A (en) * | 2016-06-29 | 2016-11-09 | 南京中电熊猫液晶显示科技有限公司 | A kind of In Cell touch-control array base palte and manufacture method thereof |
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| CN106229347A (en) * | 2016-08-24 | 2016-12-14 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and manufacture method thereof |
| CN106229347B (en) * | 2016-08-24 | 2019-06-07 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and its manufacturing method |
| CN106684097A (en) * | 2017-01-03 | 2017-05-17 | 京东方科技集团股份有限公司 | Substrate and manufacturing method therefor and display panel |
| CN111244108A (en) * | 2020-01-16 | 2020-06-05 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
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Application publication date: 20150624 |