CN104765625B - Sleep mode starting method, memory control circuit unit and memory device - Google Patents

Abstract

The present invention provides a sleep mode activation method, a memory control circuit unit and a storage device. The method comprises: when receiving a device sleep function activation instruction from a host system, determining whether a device sleep signal pin of a memory storage device is at a second logic level opposite to a first logic level; and if so, activating the device sleep function of the memory storage device, wherein the memory storage device enters a sleep mode in response to the device sleep signal pin being at the first logic level.

Description

Sleep mode startup method, memory control circuit unit and storage device

technical field

The invention relates to a dormant mode startup method, a memory control circuit unit and a memory device.

Background technique

Since rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of data non-volatility, power saving, small size, no mechanical structure, fast read and write speed, etc., in recent years, rewritable non-volatile memory The memory industry has become a very popular part of the electronics industry. For example, a solid-state drive using flash memory as a storage medium has been widely used as a hard disk of a computer host to improve the access performance of the computer. In addition, due to the rising awareness of environmental protection, green technology has become the goal of electronics manufacturers. In order to prevent the disk from continuing to consume power when the user is not using it, the SSD has been designed to support the Device Sleep Signal protocol. However, since the device sleep signal is transmitted through one of the pins of the power connection interface, in an example where the power supply interface of the host system does not support the device sleep signal protocol, when the host system is turned on, the solid state drive will The signal on the supply interface directly enters the sleep mode by malfunction and cannot be operated.

Contents of the invention

The invention provides a method for starting a dormant mode, a memory control circuit unit and a storage device, which can effectively avoid entering the dormant mode by mistake.

Accordingly, an embodiment of the invention provides a sleep mode activation method for a memory storage device. The method for initiating the sleep mode includes: (a) when receiving an instruction to activate the device sleep function from the host system, judging whether the level signal on the device sleep signal pin of the memory storage device is at a second logic level different from the first logic level; and (b) if the level signal on the device sleep signal pin of the memory storage device is judged to be at a second logic level in step (a), enabling the device sleep function of the memory storage device. In addition, the above sleep mode activation method further includes: (c) after enabling the device sleep function of the memory storage device, detecting whether the level signal on the device sleep signal pin of the memory storage device changes from the second logic level to the first logic level; and (d) if in step (c) it is detected that the level signal on the device sleep signal pin of the memory storage device changes from the second logic level to the first logic level, enabling the memory storage device to enter sleep mode.

In an embodiment of the present invention, the method for starting the sleep mode further includes: if it is judged in step (a) that the level signal on the device sleep signal pin of the memory storage device is not at the second logic level, not turning on the memory Device hibernation function for storage devices.

In an embodiment of the present invention, the above-mentioned first logic level is a high logic level and the second logic level is a low logic level.

In an embodiment of the present invention, the sleep mode startup method further includes: after the memory storage device enters the sleep mode, detecting whether the level signal on the device sleep signal pin of the memory storage device changes from the first logic level to a second logic level; and resuming the memory storage device from the sleep mode to the operational mode if a change in level signal on the device sleep signal pin of the memory storage device is detected from the first logic level to the second logic level.

In an embodiment of the present invention, the device sleep signal pin is configured on the power connection interface of the memory storage device.

An embodiment of the present invention provides a memory control circuit unit, which includes a host interface, a memory interface, and a memory management circuit. The host interface is used to electrically connect to the host system. The memory interface is used to electrically connect to the rewritable non-volatile memory module. The above-mentioned memory management circuit is electrically connected to the memory interface and the host interface, and is used for receiving an instruction for enabling the device sleep function from the host system through the host interface. When receiving an instruction to enable the device sleep function from the host system through the host interface, the memory management circuit judges whether the level signal on the device sleep signal pin of the memory storage device is at a second logic level different from the first logic level . If it is determined that the level signal on the device sleep signal pin is at the second logic level, the memory management circuit enables the device sleep function of the memory storage device. In addition, after the device sleep function of the memory storage device is turned on, the memory management circuit is also used to detect whether the level signal on the device sleep signal pin changes from the second logic level to the first logic level. If it is detected that the level signal on the device sleep signal pin on the power connection interface changes from the second logic level to the first logic level, the memory management circuit starts to enter the sleep mode.

In one embodiment of the present invention, if it is judged that the level signal on the device sleep signal pin is not at the second logic level after receiving an instruction to enable the device sleep function from the host system through the data connection interface, the memory management circuit Do not enable the device hibernation function of the memory storage device.

In an embodiment of the present invention, the power connection interface is a SATA power connection interface and the data connection interface is a SATAT connection interface.

In an embodiment of the present invention, the signal output pin is configured in a power supply connection interface of the host system, and the signal output pin outputs a voltage of 3.3 volts.

In an embodiment of the present invention, the above memory management circuit is also used to detect whether the level signal on the device sleep signal pin of the memory storage device changes from the first logic level to the second logic level after entering the sleep mode. flat. If it is detected that the level signal on the device sleep signal pin of the memory storage device changes from the first logic level to the second logic level, the above memory management circuit is also used to recover from the sleep mode to the operation mode.

An embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. The rewritable non-volatile memory module has multiple physical erasing units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used for receiving an instruction for enabling the device sleep function from the host system through the data connection interface. When receiving a device sleep function instruction from the host system through the data connection interface, the memory control circuit unit judges whether the level signal on the device sleep signal pin is at a second logic level different from the first logic level. If it is determined that the level signal on the device sleep signal pin is at the second logic level, the memory control circuit unit enables the device sleep function of the memory storage device. In addition, after the device sleep function of the memory storage device is turned on, the memory control circuit unit is also used to detect whether the level signal on the device sleep signal pin changes from the second logic level to the first logic level. If it is detected that the level signal on the device sleep signal pin on the power connection interface changes from the second logic level to the first logic level, the memory control circuit unit starts to enter the sleep mode.

In an embodiment of the present invention, if it is judged that the level signal on the device sleep signal pin is not at the second logic level after receiving an instruction to enable the device sleep function from the host system through the data connection interface, the memory control circuit unit Do not enable the device hibernation function of the memory storage device.

In an embodiment of the present invention, the memory control circuit unit is further configured to detect whether the level signal on the sleep signal pin of the device changes from the first logic level to the second logic level after entering the sleep mode. If it is detected that the level signal on the device sleep signal pin on the power connection interface changes from the first logic level to the second logic level, the memory control circuit unit is also used to restore from the sleep mode to the operation mode.

In an embodiment of the present invention, the connection interface unit further includes a power connection interface, and the device sleep signal pin is configured on the power connection interface.

An embodiment of the present invention provides a memory control circuit unit, which includes a host interface, a memory interface, and a memory management circuit. The host interface is used to electrically connect to the host system. The memory interface is used to electrically connect to the rewritable non-volatile memory module. The above-mentioned memory management circuit is electrically connected to the memory interface and the host interface, and is used for receiving an instruction for enabling the device sleep function from the host system through the host interface. In addition, the host interface has a data connection interface and a power connection interface, the data connection interface is used to receive at least one set of differential signals transmitted by the first transmission line, the power connection interface is used to receive at least one input power transmitted by the second transmission line, the first The transmission line and the second transmission line are independent of each other. Furthermore, when receiving a device sleep function instruction from the host system through the host interface, the memory management circuit determines whether the level signal on the first pin of the power connection interface is at a predetermined logic level. If it is determined that the level signal on the first pin is at a predetermined logic level, the memory management circuit enables the device sleep function of the memory storage device. In addition, after the device sleep function of the memory storage device is turned on, the memory management circuit is also used to detect whether the level signal on the device sleep signal pin is the first logic level. If it is detected that the level signal on the sleep signal pin of the device is at the first logic level, the memory management circuit starts to enter the sleep mode.

In an embodiment of the present invention, the above-mentioned first pin is different from the device sleep signal pin of the power connection interface.

In an embodiment of the present invention, if the level on the first pin is 3.3 volts, the memory management circuit does not enable the device sleep function of the memory storage device.

In an embodiment of the present invention, the aforementioned predetermined logic level is different from the first logic level.

Based on the above, the sleep mode activation method, the memory control circuit unit, and the storage device of the above-mentioned embodiment confirm whether the device sleep signal pin of the memory storage device is correctly electrically connected to the device sleep signal with support when receiving the device sleep function instruction. Protocol pins, thus effectively avoiding entering sleep mode by mistake.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a host system and a memory storage device according to an embodiment;

2 is a schematic diagram of a computer, an input/output device and a memory storage device according to an embodiment of the present invention;

3 is a schematic diagram of a host system and a memory storage device according to another embodiment of the present invention;

FIG. 4 is a schematic block diagram of the memory storage device shown in FIG. 1;

5 is a schematic block diagram of a memory control circuit unit shown according to an embodiment;

6 is a schematic diagram of a bus connection interface and a power supply connection interface for connecting a memory storage device and a host system according to an embodiment of the present invention;

Fig. 7 is a flow chart of a method for starting a sleep mode according to an embodiment.

Explanation of reference signs:

1000: host system;

1100: computer;

1102: microprocessor;

1104: random access memory;

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212: U disk;

1214: memory card;

1216: SSD;

1310: digital camera;

1312: SD card;

1314: MMC card;

1316: memory stick;

1318: CF card;

1320: embedded storage device;

100: memory storage device;

102: connect the interface unit;

102a: data connection interface;

102b: power connection interface;

104: memory control circuit unit;

106: a rewritable non-volatile memory module;

202: memory management circuit;

204: host interface;

206: memory interface;

208: buffer memory;

210: power management circuit;

212: error checking and correction circuit;

410(0)～410(N): Entity erasing unit;

602: bus connection interface;

604: power supply connection interface;

612: device sleep signal pin;

622: signal output pin;

S701 , S703 , S705 , S707 , S709 , S711 , S713 , and S715 : steps in a method for starting a sleep mode.

Detailed ways

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system and a memory storage device according to an embodiment.

Referring to FIG. 1 , the host system 1000 generally includes a computer 1100 and an input/output (input/output, I/O for short) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM for short) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202 , a keyboard 1204 , a monitor 1206 and a printer 1208 as shown in FIG. 2 . It must be understood that the device shown in FIG. 2 is not limited to the input/output device 1106, and the input/output device 1106 may also include other devices.

In the embodiment of the present invention, the memory storage device 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into or read from the memory storage device 100 through the operations of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a U disk 1212, a memory card 1214, or a solid state drive (Solid State Drive, SSD for short) 1216 as shown in FIG. 2 .

In general, host system 1000 is any system that can cooperate substantially with memory storage device 100 to store data. Although in this embodiment, the host system 1000 is described as a computer system, however, in another embodiment of the present invention, the host system 1000 may be a system such as a digital camera, a video camera, a communication device, an audio player, or a video player. . For example, when the host system is a digital camera (video camera) 1310, the rewritable non-volatile memory storage device is an SD card 1312, an MMC card 1314, a storage stick (memory stick) 1316, a CF card 1318 or An embedded storage device 1320 (as shown in FIG. 3 ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC for short). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 4 is a schematic block diagram of the memory storage device shown in FIG. 1 .

Referring to FIG. 4 , the memory storage device 100 includes a connection interface unit 102 , a memory control circuit unit 104 and a rewritable non-volatile memory module 106 .

The connection interface unit 102 includes a data connection interface 102a and a power connection interface 102b. The data connection interface 102a is used to connect to the bus connection interface of the host system 1000, and the power connection interface 102b is used to connect to the power supply connection interface of the host system 1000. Especially, in this embodiment, the data connection interface 102a can be used to receive at least one set of differential signals, and the power connection interface 102b has a device sleep signal (device sleep signal) pin to support the device sleep signal (device sleep signal) protocol. In another embodiment, the power connection interface 102b is used to receive at most two different input power sources, such as 5V and 12V. In another embodiment, the power connection interface 102b is not used for receiving 3.3V input power. Specifically, the host system 1000 supporting the protocol with device sleep can control the signal output pin electrically connected to the device sleep signal pin in the power supply connection interface to instruct the memory storage device 100 to enter the sleep mode. For example, if the host system 1000 controls the level signal on the signal output pin electrically connected to the device sleep signal pin in the power supply connection interface to be at the first logic level, then the device sleep signal pin of the power supply connection interface 102b The level signal of the signal will also be at the first logic level so that the memory storage device 100 will start to enter the sleep mode accordingly; and if the host system 1000 controls the signal output pin in the power supply connection When the level signal on the pin is at the second logic level, the level signal on the device sleep signal pin of the power connection interface 102b is also at the second logic level so that the memory storage device 100 will operate normally accordingly. Here, the first logic level and the second logic level can be set according to different designs, for example, in this embodiment, the first logic level is a high logic level and the second logic level is opposite to The low logic level of the first logic level, and in this embodiment, the high logic level is when the voltage level is higher than a predetermined value, it can be judged as a high logic level, and conversely, the low logic level Flat means that when the voltage level is lower than a predetermined value, it can be judged as a low logic level.

In this embodiment, the connection interface unit 102 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 102 may also be a device that complies with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE for short) )1394 standard, Peripheral Component Interconnect Express (PCI Express for short) standard, Universal Serial Bus (Universal Serial Bus, USB for short) standard, Ultra High Speed-I (UHS-I for short) interface Standard, Ultra High Speed-II (UHS-II for short) interface standard, Secure Digital (SD for short) interface standard, Memory Stick (MS for short) interface standard, Multimedia memory card (Multi Media Card (MMC for short) interface standard, Compact Flash (CF for short) interface standard, Integrated Device Electronics (IDE for short) standard or other suitable standards. In this embodiment, the connection interface unit and the memory control circuit unit can be packaged in a chip, or arranged outside a chip including the memory control circuit unit.

The memory control circuit unit 104 is used to execute a plurality of logic gates or control instructions implemented in the form of hardware or firmware, and write data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000, Read and erase operations.

The rewritable non-volatile memory module 106 is electrically connected to the memory control circuit unit 104 and used for storing data written by the host system 1000 . The rewritable non-volatile memory module 106 has physical erasing units 410(0)˜410(N). For example, the physical erase units 410(0)˜410(N) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has a plurality of physical programming units, wherein the physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.

In more detail, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. Entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. Each physical programming unit generally includes a data bit area and a redundant bit area. The data bit area contains multiple physical access addresses for storing user data, and the redundant bit area is used for storing system data (eg, control information and error correction code). In this embodiment, the data bit area of each physical programming unit includes 4 physical access addresses, and the size of one physical access address is 512 bytes. However, in other embodiments, the data bit area may also include more or less physical access addresses, and the present invention does not limit the size and number of physical access addresses. For example, in one embodiment, the physical erasing unit is a physical block, and the physical programming unit is a physical page or a physical sector, but the invention is not limited thereto.

In this embodiment, the rewritable non-volatile memory module 106 is a multi-level memory cell (Multi LevelCell, referred to as MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits of data in a memory cell) memory module). However, the present invention is not limited thereto, and the rewritable non-volatile memory module 106 may also be a single-level storage cell (Single Level Cell, referred to as SLC) NAND flash memory module (that is, one storage unit can store 1 bit data flash memory module), complex layer storage unit (Trinary Level Cell, referred to as TLC) NAND flash memory module (that is, a flash memory module that can store 3 bits of data in a storage unit), other flash memory module or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an embodiment.

Referring to FIG. 5 , the memory control circuit unit 104 includes a memory management circuit 202 , a host interface 204 and a memory interface 206 .

The memory management circuit 202 is used to control the overall operation of the memory control circuit unit 104 . Specifically, the memory management circuit 202 has a plurality of control instructions, and when the memory storage device 100 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data.

In this embodiment, the control commands of the memory management circuit 202 are implemented in the form of firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 100 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another embodiment of the present invention, the control instructions of the memory management circuit 202 can also be stored in a specific area of the rewritable non-volatile memory module 106 in the form of program code (for example, the system area dedicated to storing system data in the memory module )middle. In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a driver code, and when the memory control circuit unit 104 is enabled, the microprocessor unit will first execute the driver code segment to store the data stored in the rewritable non-volatile memory module 106. The control instructions are loaded into the random access memory of the memory management circuit 202 . Afterwards, the microprocessor unit runs these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another embodiment of the present invention, the control instructions of the memory management circuit 202 may also be implemented in a hardware form. For example, the memory management circuit 202 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. Wherein, the storage unit management circuit is used to manage the physical erasing unit of the rewritable non-volatile memory module 106; the memory writing circuit is used to issue a write command to the rewritable non-volatile memory module 106 to write data into the rewritable nonvolatile memory module 106; the memory read circuit is used to issue a read instruction to the rewritable nonvolatile memory module 106 to read from the rewritable nonvolatile memory module 106 Data; the memory erasing circuit is used to issue an erase command to the rewritable non-volatile memory module 106 to erase data from the rewritable non-volatile memory module 106; and the data processing circuit is used to process the data to be written Data input to the rewritable non-volatile memory module 106 and data read from the rewritable non-volatile memory module 106.

The host interface 204 is electrically connected to the memory management circuit 202 and is used to electrically connect to the connection interface unit 102 to receive and identify commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this embodiment, the host interface 204 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may also be compatible with PATA standard, IEEE1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 206 is electrically connected to the memory management circuit 202 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 will be converted into a format acceptable to the rewritable nonvolatile memory module 106 via the memory interface 206 .

In an embodiment of the present invention, the memory control circuit unit 104 further includes a buffer memory 208 , a power management circuit 210 and an error checking and correction circuit 212 .

The buffer memory 208 is electrically connected to the memory management circuit 202 and used for temporarily storing data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106 .

The power management circuit 210 is electrically connected to the memory management circuit 202 and used to control the power of the memory storage device 100 .

The error checking and correcting circuit 212 is electrically connected to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correcting circuit 212 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code) for the data corresponding to the write command. , ECC Code for short), and the memory management circuit 202 will write the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module 106 . Afterwards, when the memory management circuit 202 reads data from the rewritable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 212 will read the error checking and correction code according to the error checking and correction code. The correction code performs error checking and correction procedures on the read data.

6 is a schematic diagram of a bus connection interface and a power supply connection interface for connecting a memory storage device to a host system according to an embodiment of the present invention.

Referring to FIG. 6 , the bus connection interface 602 is electrically connected to the control chipset (not shown) of the host system 1000 and used to connect with the data connection interface 102 a of the memory storage device 100 . The power supply connection interface 604 is electrically connected to a power supply (not shown) of the host system 1000 and used to connect with the power connection interface 102 b of the memory storage device 100 .

As mentioned above, in this embodiment, the power connection interface 102b has a device sleep signal pin 612, wherein when the power supply connection interface 604 is electrically connected to the power connection interface 102b, the signal output pin 622 of the power supply connection interface 604 will be It is electrically connected to the device sleep signal pin 612 . For example, when the host system 1000 is powered on, the signal output pin 622 will output a voltage signal of 3.3 volts to provide the power required by the electrically connected devices.

In particular, as mentioned above, if the signal output pin 622 electrically connected to the device sleep signal pin 612 is used to support the device sleep signal protocol, in the normal operation state of the memory storage device 100, the host system 1000 is the control signal The level signal on the output pin 622 is at the second logic level (ie, does not enable the memory storage device 100 to enter the device sleep mode), so that the level signal on the device sleep signal pin 612 is also at the second logic level. Based on this, the memory control circuit unit 104 (or the memory management circuit 202 ) will operate normally according to the state of the device sleep signal pin 612 . If the signal output pin 622 is not used to support the device sleep signal protocol, the host system 1000 will not use the signal output pin 622 to output the device sleep control signal. Therefore, after the host system 1000 is powered on, if the signal output pin The level signal on 622 at the first logic level may cause the memory storage device 100 to malfunction and directly enter the device sleep mode.

Therefore, if the host system 1000 supports the device sleep signal protocol, in a specific specification, the signal output pin 622 used to connect the device sleep signal pin 612 should be correctly electrically connected to the chip set of the host system 1000 ( not shown) to control the memory storage device 100 to enter the sleep mode. In this embodiment, when the host system 1000 transmits an instruction to enable the device sleep function to the memory storage device 100 through the bus connection interface 602, the memory control circuit unit 104 (or the memory management circuit 202) will determine the signal on the device sleep signal pin 612 Whether the level signal is at the second logic level. If the level signal on the device sleep signal pin 612 is at the second logic level, the memory control circuit unit 104 determines that the device sleep signal pin 612 has been correctly connected to a signal output pin supporting the device sleep signal protocol. On the contrary, if the level signal on the device sleep signal pin 612 is at the first logic level, the memory control circuit unit 104 will determine that the device sleep signal pin 612 is not connected to a signal output pin supporting the device sleep signal protocol.

Especially, if the device sleep signal pin 612 has been correctly connected to the signal output pin supporting the device sleep signal protocol, the memory control circuit unit 104 (or the memory management circuit 202) will enable the device sleep function, and the host system When the 1000 indicates that the signal output pin 622 of the device sleep signal pin 612 starts to enter the sleep mode (for example, the level of the control signal output pin 622 changes from the second logic level to the first logic level), the memory control The circuit unit 104 (or the memory management circuit 202 ) activates the sleep mode, so that the memory storage device 100 stops operating and is in a state of low power consumption.

Fig. 7 is a flow chart of a method for starting a sleep mode according to an embodiment.

Please refer to FIG. 7, in step S701, the memory control circuit unit 104 (or memory management circuit 202) receives an instruction to enable the device sleep function through the data connection interface 102a, and in step S703, the memory control circuit unit 104 (or memory management circuit 202) The circuit 202) will determine whether the level signal on the device sleep signal pin 612 on the power connection interface 102b is at a second logic level opposite to the first logic level.

If the level signal on the device sleep signal pin 612 on the power connection interface 102b of the memory storage device 100 is at the second logic level, in step S705, the memory control circuit unit 104 (or memory management circuit 202) will turn on the device Sleep function.

Next, in step S707, the memory control circuit unit 104 (or the memory management circuit 202) detects whether the state of the device sleep signal pin 612 on the power connection interface 102b changes from the second logic level to the first logic level.

If it is detected in step S707 that the state of the device sleep signal pin 612 on the power connection interface 102b changes from the second logic level to the first logic level, in step S709, the memory control circuit unit 104 (or memory management circuit 202) will start to enter sleep mode.

If it is not detected in step S707 that the state of the device sleep signal pin 612 on the power connection interface 102b changes from the second logic level to the first logic level, step S707 will be executed repeatedly.

After step S709, in step S711, the memory control circuit unit 104 (or the memory management circuit 202) will detect whether the state of the device sleep signal pin 612 on the power connection interface 102b changes from the first logic level to the second logic level. flat.

If it is detected in step S711 that the state of the device sleep signal pin 612 on the power connection interface 102b changes from the first logic level to the second logic level, in step S713, the memory control circuit unit 104 (or memory management circuit 202) will return to the operation mode from the sleep mode, and then step S707 will be executed.

If it is not detected in step S711 that the state of the device sleep signal pin 612 on the power connection interface 102b changes from the first logic level to the second logic level, step S711 will be executed repeatedly.

If it is judged in step S703 that the level signal on the device sleep signal pin 612 on the power connection interface 102b of the memory storage device 100 is not at the second logic level, in step S715, the memory control circuit unit 104 (or memory management Circuit 202) does not enable the device sleep function.

It is worth mentioning that in this embodiment, the memory control circuit unit 104 (or the memory management circuit 202) determines whether to enable the device sleep function according to the level signal on the device sleep signal pin 612 on the power connection interface 102b . However, the present invention is not limited thereto. In another embodiment of the present invention, the memory control circuit unit 104 (or the memory management circuit 202 ) may also determine whether to enable the device sleep function according to other pins on the power connection interface 102b. For example, when receiving an instruction to enable the device sleep function from the host system 1000 through the host interface 204, the memory control circuit unit 104 (or the memory management circuit 202) determines that the unused pin of the power connection interface 102b (hereinafter referred to as the first Whether the level signal on the pin) is at a predetermined logic level. If it is judged that the level signal on the first pin is at a predetermined logic level, the memory control circuit unit 104 (or the memory management circuit 202) will enable the device sleep function of the memory storage device 100, and if it detects When the level of the device sleep signal pin of the power connection interface 102b is at the first logic level, it starts to enter the sleep mode. Especially, if the level of the first pin is 3.3 volts, the memory control circuit unit 104 (or the memory management circuit 202 ) will not enable the device sleep function of the memory storage device 100 .

To sum up, the method for starting the sleep mode, the memory control circuit unit, and the storage device of the embodiments of the present invention identify the logic level state of the device sleep signal pin on the power connection interface when receiving the device sleep function enable command to Judging whether the signal output pin connected to the device sleep signal pin supports the device sleep signal protocol, thereby avoiding misjudgment and entering the sleep mode.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (19)

1. a kind of suspend mode starts method, which is characterized in that be used for a memory storage apparatus, which starts method Including：

(a) when receiving enabling device sleep mode instruction from a host system, judge the one of the memory storage apparatus Whether the level signal on device sleep signal pin is in one second logic level different from one first logic level；

If (b) at the level signal on the device sleep signal pin for judging the memory storage apparatus in step (a) When second logic level, a device sleep mode of the memory storage apparatus is opened；

(c) after the device sleep mode for opening the memory storage apparatus, the dress of the memory storage apparatus is detected Set whether the level signal on sleep signal pin from second logic level changes into first logic level；And

If (d) detecting the level signal on the device sleep signal pin of the memory storage apparatus in step (c) When changing into first logic level from second logic level, starts the memory storage apparatus and enter the suspend mode.

2. suspend mode according to claim 1 starts method, which is characterized in that further include：

If judging that the device sleep signal pin of the memory storage apparatus is not at second logic electricity in step (a) Usually, it is not turned on the device sleep mode of the memory storage apparatus.

3. suspend mode according to claim 1 starts method, which is characterized in that first logic level is a high logic Level and second logic level are a low logic level.

4. suspend mode according to claim 1 starts method, which is characterized in that further include：

After the memory storage apparatus enters the suspend mode, the device sleep signal for detecting the memory storage apparatus is drawn Whether level signal on foot from first logic level changes into second logic level；And

If detecting that the level signal on the device sleep signal pin of the memory storage apparatus is electric from first logic It is flat when changing into second logic level, so that the memory storage apparatus is restored from the suspend mode to an operation mode.

5. suspend mode according to claim 1 starts method, which is characterized in that the device sleep signal pin configuration exists On one electric power connection interface of the memory storage apparatus.

6. a kind of memorizer control circuit unit, which is characterized in that for one memory storage apparatus of control, including：

One host interface, to be electrically connected to a host system；

One memory interface is electrically connected to a reproducible nonvolatile memorizer module；And

One memory management circuitry is electrically connected to the memory interface and the host interface, and to pass through the host interface Enabling device sleep mode instruction is received from the host system；

Wherein when receiving enabling device sleep mode instruction from the host system by the host interface, the memory pipe Whether the level signal on one device sleep signal pin of the reason circuit judges memory storage apparatus is in is patrolled with one first Collect one second different logic level of level；

If judge that the device sleep signal pin is in second logic level, which opens the storage One device sleep mode of device storage device；

Wherein after the device sleep mode for opening the memory storage apparatus, the memory management circuitry is also detecting Whether level signal on the device sleep signal pin from second logic level changes into one first logic level；

If detecting that the level signal on the device sleep signal pin changes into first logic from second logic level When level, which initially enters suspend mode.

7. memorizer control circuit unit according to claim 6, which is characterized in that the device sleep signal pin configuration On an electric power connection interface of the memory storage apparatus.

8. memorizer control circuit unit according to claim 7, which is characterized in that if passing through Datalink Interface The level signal on the device sleep signal pin is judged after receiving enabling device sleep mode instruction from the host system When being not at second logic level, which is not turned on the device suspend mode work(of the memory storage apparatus Energy.

9. memorizer control circuit unit according to claim 6, which is characterized in that first logic level is that a height is patrolled It is a low logic level to collect level and second logic level.

10. memorizer control circuit unit according to claim 8, which is characterized in that the electric power connection interface is a string Row Advanced Technology Attachment electric power connection interface and the Datalink Interface are a Serial Advanced Technology Attachment connecting interface.

11. memorizer control circuit unit according to claim 7, which is characterized in that signal output pin is configured at this In the power supply supply connecting interface of host system, and the signal output pin exports one 3.3 volts of voltages.

12. memorizer control circuit unit according to claim 6, which is characterized in that the memory management circuitry is also used Whether after entering the suspend mode, to detect the level signal on the device sleep signal pin of the memory storage apparatus Second logic level is changed into from first logic level；

If wherein detecting that level signal on the device sleep signal pin of the memory storage apparatus first is patrolled from this When volume level changes into second logic level, the memory management circuitry from the suspend mode also restoring to an operation mould Formula.

13. a kind of memory storage apparatus, which is characterized in that including：

One connecting interface unit, is electrically connected to a host system, which includes a Datalink Interface；

One reproducible nonvolatile memorizer module has multiple entity erased cells；And

One memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould Block,

Wherein the memorizer control circuit unit fills to receive an enabling from the host system by the Datalink Interface Sleep mode instruction is set,

Wherein when receiving enabling device sleep mode instruction from the host system by the Datalink Interface, the storage Whether device control circuit unit judges the level signal on a device sleep signal pin in opposite with one first logic level One second logic level；

If judge that the level signal on the device sleep signal pin is in second logic level, memory control electricity Road unit opens a device sleep mode；

Wherein after opening the device sleep mode, the memorizer control circuit unit is also detecting the device sleep signal Whether level signal on pin from second logic level changes into one first logic level；

If detecting that the level signal on the device sleep signal pin changes into first logic from second logic level When level, which initially enters suspend mode.

14. memory storage apparatus according to claim 13, which is characterized in that the connecting interface unit further includes an electricity The source connecting interface and device sleep signal pin configuration is on the electric power connection interface.

15. memory storage apparatus according to claim 13, which is characterized in that if passing through the Datalink Interface The level signal on the device sleep signal pin is judged after receiving enabling device sleep mode instruction from the host system When being not at second logic level, which is not turned on the device suspend mode of the memory storage apparatus Function.

16. memory storage apparatus according to claim 13, which is characterized in that first logic level is a high logic Level and second logic level are a low logic level.

17. memory storage apparatus according to claim 14, which is characterized in that the electric power connection interface is one serial high Grade Technical Appendix electric power connection interface and the Datalink Interface are a Serial Advanced Technology Attachment connecting interface.

18. memory storage apparatus according to claim 14, which is characterized in that signal output pin is configured in the host In the power supply supply connecting interface of system, and the signal output pin exports one 3.3 volts of voltages.

19. memory storage apparatus according to claim 13, which is characterized in that the memorizer control circuit unit is also used After entering the suspend mode, to detect whether the level signal on the device sleep signal pin changes from first logic level Become second logic level；

If wherein detect level signal on the device sleep signal pin from first logic level change into this second When logic level, the memorizer control circuit unit from the suspend mode also restoring to an operation mode.